alim15x3.c 14 KB

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  1. /*
  2. * Copyright (C) 1998-2000 Michel Aubry, Maintainer
  3. * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
  4. * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
  5. *
  6. * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
  7. * May be copied or modified under the terms of the GNU General Public License
  8. * Copyright (C) 2002 Alan Cox
  9. * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw>
  10. * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
  11. * Copyright (C) 2007 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
  12. *
  13. * (U)DMA capable version of ali 1533/1543(C), 1535(D)
  14. *
  15. **********************************************************************
  16. * 9/7/99 --Parts from the above author are included and need to be
  17. * converted into standard interface, once I finish the thought.
  18. *
  19. * Recent changes
  20. * Don't use LBA48 mode on ALi <= 0xC4
  21. * Don't poke 0x79 with a non ALi northbridge
  22. * Don't flip undefined bits on newer chipsets (fix Fujitsu laptop hang)
  23. * Allow UDMA6 on revisions > 0xC4
  24. *
  25. * Documentation
  26. * Chipset documentation available under NDA only
  27. *
  28. */
  29. #include <linux/module.h>
  30. #include <linux/types.h>
  31. #include <linux/kernel.h>
  32. #include <linux/pci.h>
  33. #include <linux/ide.h>
  34. #include <linux/init.h>
  35. #include <linux/dmi.h>
  36. #include <asm/io.h>
  37. #define DRV_NAME "alim15x3"
  38. /*
  39. * ALi devices are not plug in. Otherwise these static values would
  40. * need to go. They ought to go away anyway
  41. */
  42. static u8 m5229_revision;
  43. static u8 chip_is_1543c_e;
  44. static struct pci_dev *isa_dev;
  45. /**
  46. * ali_set_pio_mode - set host controller for PIO mode
  47. * @drive: drive
  48. * @pio: PIO mode number
  49. *
  50. * Program the controller for the given PIO mode.
  51. */
  52. static void ali_set_pio_mode(ide_drive_t *drive, const u8 pio)
  53. {
  54. ide_hwif_t *hwif = drive->hwif;
  55. struct pci_dev *dev = to_pci_dev(hwif->dev);
  56. struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
  57. int s_time = t->setup, a_time = t->active, c_time = t->cycle;
  58. u8 s_clc, a_clc, r_clc;
  59. unsigned long flags;
  60. int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
  61. int port = hwif->channel ? 0x5c : 0x58;
  62. int portFIFO = hwif->channel ? 0x55 : 0x54;
  63. u8 cd_dma_fifo = 0, unit = drive->dn & 1;
  64. if ((s_clc = (s_time * bus_speed + 999) / 1000) >= 8)
  65. s_clc = 0;
  66. if ((a_clc = (a_time * bus_speed + 999) / 1000) >= 8)
  67. a_clc = 0;
  68. if (!(r_clc = (c_time * bus_speed + 999) / 1000 - a_clc - s_clc)) {
  69. r_clc = 1;
  70. } else {
  71. if (r_clc >= 16)
  72. r_clc = 0;
  73. }
  74. local_irq_save(flags);
  75. /*
  76. * PIO mode => ATA FIFO on, ATAPI FIFO off
  77. */
  78. pci_read_config_byte(dev, portFIFO, &cd_dma_fifo);
  79. if (drive->media==ide_disk) {
  80. if (unit) {
  81. pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0x0F) | 0x50);
  82. } else {
  83. pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0xF0) | 0x05);
  84. }
  85. } else {
  86. if (unit) {
  87. pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0x0F);
  88. } else {
  89. pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0xF0);
  90. }
  91. }
  92. pci_write_config_byte(dev, port, s_clc);
  93. pci_write_config_byte(dev, port + unit + 2, (a_clc << 4) | r_clc);
  94. local_irq_restore(flags);
  95. }
  96. /**
  97. * ali_udma_filter - compute UDMA mask
  98. * @drive: IDE device
  99. *
  100. * Return available UDMA modes.
  101. *
  102. * The actual rules for the ALi are:
  103. * No UDMA on revisions <= 0x20
  104. * Disk only for revisions < 0xC2
  105. * Not WDC drives on M1543C-E (?)
  106. */
  107. static u8 ali_udma_filter(ide_drive_t *drive)
  108. {
  109. if (m5229_revision > 0x20 && m5229_revision < 0xC2) {
  110. if (drive->media != ide_disk)
  111. return 0;
  112. if (chip_is_1543c_e &&
  113. strstr((char *)&drive->id[ATA_ID_PROD], "WDC "))
  114. return 0;
  115. }
  116. return drive->hwif->ultra_mask;
  117. }
  118. /**
  119. * ali_set_dma_mode - set host controller for DMA mode
  120. * @drive: drive
  121. * @speed: DMA mode
  122. *
  123. * Configure the hardware for the desired IDE transfer mode.
  124. */
  125. static void ali_set_dma_mode(ide_drive_t *drive, const u8 speed)
  126. {
  127. ide_hwif_t *hwif = drive->hwif;
  128. struct pci_dev *dev = to_pci_dev(hwif->dev);
  129. u8 speed1 = speed;
  130. u8 unit = drive->dn & 1;
  131. u8 tmpbyte = 0x00;
  132. int m5229_udma = (hwif->channel) ? 0x57 : 0x56;
  133. if (speed == XFER_UDMA_6)
  134. speed1 = 0x47;
  135. if (speed < XFER_UDMA_0) {
  136. u8 ultra_enable = (unit) ? 0x7f : 0xf7;
  137. /*
  138. * clear "ultra enable" bit
  139. */
  140. pci_read_config_byte(dev, m5229_udma, &tmpbyte);
  141. tmpbyte &= ultra_enable;
  142. pci_write_config_byte(dev, m5229_udma, tmpbyte);
  143. /*
  144. * FIXME: Oh, my... DMA timings are never set.
  145. */
  146. } else {
  147. pci_read_config_byte(dev, m5229_udma, &tmpbyte);
  148. tmpbyte &= (0x0f << ((1-unit) << 2));
  149. /*
  150. * enable ultra dma and set timing
  151. */
  152. tmpbyte |= ((0x08 | ((4-speed1)&0x07)) << (unit << 2));
  153. pci_write_config_byte(dev, m5229_udma, tmpbyte);
  154. if (speed >= XFER_UDMA_3) {
  155. pci_read_config_byte(dev, 0x4b, &tmpbyte);
  156. tmpbyte |= 1;
  157. pci_write_config_byte(dev, 0x4b, tmpbyte);
  158. }
  159. }
  160. }
  161. /**
  162. * ali_dma_check - DMA check
  163. * @drive: target device
  164. * @cmd: command
  165. *
  166. * Returns 1 if the DMA cannot be performed, zero on success.
  167. */
  168. static int ali_dma_check(ide_drive_t *drive, struct ide_cmd *cmd)
  169. {
  170. if (m5229_revision < 0xC2 && drive->media != ide_disk) {
  171. if (cmd->tf_flags & IDE_TFLAG_WRITE)
  172. return 1; /* try PIO instead of DMA */
  173. }
  174. return 0;
  175. }
  176. /**
  177. * init_chipset_ali15x3 - Initialise an ALi IDE controller
  178. * @dev: PCI device
  179. *
  180. * This function initializes the ALI IDE controller and where
  181. * appropriate also sets up the 1533 southbridge.
  182. */
  183. static int init_chipset_ali15x3(struct pci_dev *dev)
  184. {
  185. unsigned long flags;
  186. u8 tmpbyte;
  187. struct pci_dev *north = pci_get_slot(dev->bus, PCI_DEVFN(0,0));
  188. m5229_revision = dev->revision;
  189. isa_dev = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
  190. local_irq_save(flags);
  191. if (m5229_revision < 0xC2) {
  192. /*
  193. * revision 0x20 (1543-E, 1543-F)
  194. * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E)
  195. * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7
  196. */
  197. pci_read_config_byte(dev, 0x4b, &tmpbyte);
  198. /*
  199. * clear bit 7
  200. */
  201. pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F);
  202. /*
  203. * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
  204. */
  205. if (m5229_revision >= 0x20 && isa_dev) {
  206. pci_read_config_byte(isa_dev, 0x5e, &tmpbyte);
  207. chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0;
  208. }
  209. goto out;
  210. }
  211. /*
  212. * 1543C-B?, 1535, 1535D, 1553
  213. * Note 1: not all "motherboard" support this detection
  214. * Note 2: if no udma 66 device, the detection may "error".
  215. * but in this case, we will not set the device to
  216. * ultra 66, the detection result is not important
  217. */
  218. /*
  219. * enable "Cable Detection", m5229, 0x4b, bit3
  220. */
  221. pci_read_config_byte(dev, 0x4b, &tmpbyte);
  222. pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08);
  223. /*
  224. * We should only tune the 1533 enable if we are using an ALi
  225. * North bridge. We might have no north found on some zany
  226. * box without a device at 0:0.0. The ALi bridge will be at
  227. * 0:0.0 so if we didn't find one we know what is cooking.
  228. */
  229. if (north && north->vendor != PCI_VENDOR_ID_AL)
  230. goto out;
  231. if (m5229_revision < 0xC5 && isa_dev)
  232. {
  233. /*
  234. * set south-bridge's enable bit, m1533, 0x79
  235. */
  236. pci_read_config_byte(isa_dev, 0x79, &tmpbyte);
  237. if (m5229_revision == 0xC2) {
  238. /*
  239. * 1543C-B0 (m1533, 0x79, bit 2)
  240. */
  241. pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04);
  242. } else if (m5229_revision >= 0xC3) {
  243. /*
  244. * 1553/1535 (m1533, 0x79, bit 1)
  245. */
  246. pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02);
  247. }
  248. }
  249. out:
  250. /*
  251. * CD_ROM DMA on (m5229, 0x53, bit0)
  252. * Enable this bit even if we want to use PIO.
  253. * PIO FIFO off (m5229, 0x53, bit1)
  254. * The hardware will use 0x54h and 0x55h to control PIO FIFO.
  255. * (Not on later devices it seems)
  256. *
  257. * 0x53 changes meaning on later revs - we must no touch
  258. * bit 1 on them. Need to check if 0x20 is the right break.
  259. */
  260. if (m5229_revision >= 0x20) {
  261. pci_read_config_byte(dev, 0x53, &tmpbyte);
  262. if (m5229_revision <= 0x20)
  263. tmpbyte = (tmpbyte & (~0x02)) | 0x01;
  264. else if (m5229_revision == 0xc7 || m5229_revision == 0xc8)
  265. tmpbyte |= 0x03;
  266. else
  267. tmpbyte |= 0x01;
  268. pci_write_config_byte(dev, 0x53, tmpbyte);
  269. }
  270. pci_dev_put(north);
  271. pci_dev_put(isa_dev);
  272. local_irq_restore(flags);
  273. return 0;
  274. }
  275. /*
  276. * Cable special cases
  277. */
  278. static const struct dmi_system_id cable_dmi_table[] = {
  279. {
  280. .ident = "HP Pavilion N5430",
  281. .matches = {
  282. DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
  283. DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
  284. },
  285. },
  286. {
  287. .ident = "Toshiba Satellite S1800-814",
  288. .matches = {
  289. DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
  290. DMI_MATCH(DMI_PRODUCT_NAME, "S1800-814"),
  291. },
  292. },
  293. { }
  294. };
  295. static int ali_cable_override(struct pci_dev *pdev)
  296. {
  297. /* Fujitsu P2000 */
  298. if (pdev->subsystem_vendor == 0x10CF &&
  299. pdev->subsystem_device == 0x10AF)
  300. return 1;
  301. /* Mitac 8317 (Winbook-A) and relatives */
  302. if (pdev->subsystem_vendor == 0x1071 &&
  303. pdev->subsystem_device == 0x8317)
  304. return 1;
  305. /* Systems by DMI */
  306. if (dmi_check_system(cable_dmi_table))
  307. return 1;
  308. return 0;
  309. }
  310. /**
  311. * ali_cable_detect - cable detection
  312. * @hwif: IDE interface
  313. *
  314. * This checks if the controller and the cable are capable
  315. * of UDMA66 transfers. It doesn't check the drives.
  316. * But see note 2 below!
  317. *
  318. * FIXME: frobs bits that are not defined on newer ALi devicea
  319. */
  320. static u8 ali_cable_detect(ide_hwif_t *hwif)
  321. {
  322. struct pci_dev *dev = to_pci_dev(hwif->dev);
  323. unsigned long flags;
  324. u8 cbl = ATA_CBL_PATA40, tmpbyte;
  325. local_irq_save(flags);
  326. if (m5229_revision >= 0xC2) {
  327. /*
  328. * m5229 80-pin cable detection (from Host View)
  329. *
  330. * 0x4a bit0 is 0 => primary channel has 80-pin
  331. * 0x4a bit1 is 0 => secondary channel has 80-pin
  332. *
  333. * Certain laptops use short but suitable cables
  334. * and don't implement the detect logic.
  335. */
  336. if (ali_cable_override(dev))
  337. cbl = ATA_CBL_PATA40_SHORT;
  338. else {
  339. pci_read_config_byte(dev, 0x4a, &tmpbyte);
  340. if ((tmpbyte & (1 << hwif->channel)) == 0)
  341. cbl = ATA_CBL_PATA80;
  342. }
  343. }
  344. local_irq_restore(flags);
  345. return cbl;
  346. }
  347. #ifndef CONFIG_SPARC64
  348. /**
  349. * init_hwif_ali15x3 - Initialize the ALI IDE x86 stuff
  350. * @hwif: interface to configure
  351. *
  352. * Obtain the IRQ tables for an ALi based IDE solution on the PC
  353. * class platforms. This part of the code isn't applicable to the
  354. * Sparc systems.
  355. */
  356. static void __devinit init_hwif_ali15x3 (ide_hwif_t *hwif)
  357. {
  358. u8 ideic, inmir;
  359. s8 irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6,
  360. 1, 11, 0, 12, 0, 14, 0, 15 };
  361. int irq = -1;
  362. if (isa_dev) {
  363. /*
  364. * read IDE interface control
  365. */
  366. pci_read_config_byte(isa_dev, 0x58, &ideic);
  367. /* bit0, bit1 */
  368. ideic = ideic & 0x03;
  369. /* get IRQ for IDE Controller */
  370. if ((hwif->channel && ideic == 0x03) ||
  371. (!hwif->channel && !ideic)) {
  372. /*
  373. * get SIRQ1 routing table
  374. */
  375. pci_read_config_byte(isa_dev, 0x44, &inmir);
  376. inmir = inmir & 0x0f;
  377. irq = irq_routing_table[inmir];
  378. } else if (hwif->channel && !(ideic & 0x01)) {
  379. /*
  380. * get SIRQ2 routing table
  381. */
  382. pci_read_config_byte(isa_dev, 0x75, &inmir);
  383. inmir = inmir & 0x0f;
  384. irq = irq_routing_table[inmir];
  385. }
  386. if(irq >= 0)
  387. hwif->irq = irq;
  388. }
  389. }
  390. #else
  391. #define init_hwif_ali15x3 NULL
  392. #endif /* CONFIG_SPARC64 */
  393. /**
  394. * init_dma_ali15x3 - set up DMA on ALi15x3
  395. * @hwif: IDE interface
  396. * @d: IDE port info
  397. *
  398. * Set up the DMA functionality on the ALi 15x3.
  399. */
  400. static int __devinit init_dma_ali15x3(ide_hwif_t *hwif,
  401. const struct ide_port_info *d)
  402. {
  403. struct pci_dev *dev = to_pci_dev(hwif->dev);
  404. unsigned long base = ide_pci_dma_base(hwif, d);
  405. if (base == 0)
  406. return -1;
  407. hwif->dma_base = base;
  408. if (ide_pci_check_simplex(hwif, d) < 0)
  409. return -1;
  410. if (ide_pci_set_master(dev, d->name) < 0)
  411. return -1;
  412. if (!hwif->channel)
  413. outb(inb(base + 2) & 0x60, base + 2);
  414. printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
  415. hwif->name, base, base + 7);
  416. if (ide_allocate_dma_engine(hwif))
  417. return -1;
  418. return 0;
  419. }
  420. static const struct ide_port_ops ali_port_ops = {
  421. .set_pio_mode = ali_set_pio_mode,
  422. .set_dma_mode = ali_set_dma_mode,
  423. .udma_filter = ali_udma_filter,
  424. .cable_detect = ali_cable_detect,
  425. };
  426. static const struct ide_dma_ops ali_dma_ops = {
  427. .dma_host_set = ide_dma_host_set,
  428. .dma_setup = ide_dma_setup,
  429. .dma_start = ide_dma_start,
  430. .dma_end = ide_dma_end,
  431. .dma_test_irq = ide_dma_test_irq,
  432. .dma_lost_irq = ide_dma_lost_irq,
  433. .dma_check = ali_dma_check,
  434. .dma_timer_expiry = ide_dma_sff_timer_expiry,
  435. .dma_sff_read_status = ide_dma_sff_read_status,
  436. };
  437. static const struct ide_port_info ali15x3_chipset __devinitdata = {
  438. .name = DRV_NAME,
  439. .init_chipset = init_chipset_ali15x3,
  440. .init_hwif = init_hwif_ali15x3,
  441. .init_dma = init_dma_ali15x3,
  442. .port_ops = &ali_port_ops,
  443. .dma_ops = &sff_dma_ops,
  444. .pio_mask = ATA_PIO5,
  445. .swdma_mask = ATA_SWDMA2,
  446. .mwdma_mask = ATA_MWDMA2,
  447. };
  448. /**
  449. * alim15x3_init_one - set up an ALi15x3 IDE controller
  450. * @dev: PCI device to set up
  451. *
  452. * Perform the actual set up for an ALi15x3 that has been found by the
  453. * hot plug layer.
  454. */
  455. static int __devinit alim15x3_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  456. {
  457. struct ide_port_info d = ali15x3_chipset;
  458. u8 rev = dev->revision, idx = id->driver_data;
  459. /* don't use LBA48 DMA on ALi devices before rev 0xC5 */
  460. if (rev <= 0xC4)
  461. d.host_flags |= IDE_HFLAG_NO_LBA48_DMA;
  462. if (rev >= 0x20) {
  463. if (rev == 0x20)
  464. d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
  465. if (rev < 0xC2)
  466. d.udma_mask = ATA_UDMA2;
  467. else if (rev == 0xC2 || rev == 0xC3)
  468. d.udma_mask = ATA_UDMA4;
  469. else if (rev == 0xC4)
  470. d.udma_mask = ATA_UDMA5;
  471. else
  472. d.udma_mask = ATA_UDMA6;
  473. d.dma_ops = &ali_dma_ops;
  474. } else {
  475. d.host_flags |= IDE_HFLAG_NO_DMA;
  476. d.mwdma_mask = d.swdma_mask = 0;
  477. }
  478. if (idx == 0)
  479. d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
  480. return ide_pci_init_one(dev, &d, NULL);
  481. }
  482. static const struct pci_device_id alim15x3_pci_tbl[] = {
  483. { PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5229), 0 },
  484. { PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5228), 1 },
  485. { 0, },
  486. };
  487. MODULE_DEVICE_TABLE(pci, alim15x3_pci_tbl);
  488. static struct pci_driver alim15x3_pci_driver = {
  489. .name = "ALI15x3_IDE",
  490. .id_table = alim15x3_pci_tbl,
  491. .probe = alim15x3_init_one,
  492. .remove = ide_pci_remove,
  493. .suspend = ide_pci_suspend,
  494. .resume = ide_pci_resume,
  495. };
  496. static int __init ali15x3_ide_init(void)
  497. {
  498. return ide_pci_register_driver(&alim15x3_pci_driver);
  499. }
  500. static void __exit ali15x3_ide_exit(void)
  501. {
  502. pci_unregister_driver(&alim15x3_pci_driver);
  503. }
  504. module_init(ali15x3_ide_init);
  505. module_exit(ali15x3_ide_exit);
  506. MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox");
  507. MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE");
  508. MODULE_LICENSE("GPL");