scx200_acb.c 14 KB

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  1. /*
  2. Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>
  3. National Semiconductor SCx200 ACCESS.bus support
  4. Also supports the AMD CS5535 and AMD CS5536
  5. Based on i2c-keywest.c which is:
  6. Copyright (c) 2001 Benjamin Herrenschmidt <benh@kernel.crashing.org>
  7. Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
  8. This program is free software; you can redistribute it and/or
  9. modify it under the terms of the GNU General Public License as
  10. published by the Free Software Foundation; either version 2 of the
  11. License, or (at your option) any later version.
  12. This program is distributed in the hope that it will be useful,
  13. but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. General Public License for more details.
  16. You should have received a copy of the GNU General Public License
  17. along with this program; if not, write to the Free Software
  18. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. */
  20. #include <linux/module.h>
  21. #include <linux/errno.h>
  22. #include <linux/kernel.h>
  23. #include <linux/init.h>
  24. #include <linux/i2c.h>
  25. #include <linux/pci.h>
  26. #include <linux/delay.h>
  27. #include <linux/mutex.h>
  28. #include <asm/io.h>
  29. #include <linux/scx200.h>
  30. #define NAME "scx200_acb"
  31. MODULE_AUTHOR("Christer Weinigel <wingel@nano-system.com>");
  32. MODULE_DESCRIPTION("NatSemi SCx200 ACCESS.bus Driver");
  33. MODULE_LICENSE("GPL");
  34. #define MAX_DEVICES 4
  35. static int base[MAX_DEVICES] = { 0x820, 0x840 };
  36. module_param_array(base, int, NULL, 0);
  37. MODULE_PARM_DESC(base, "Base addresses for the ACCESS.bus controllers");
  38. #define POLL_TIMEOUT (HZ/5)
  39. enum scx200_acb_state {
  40. state_idle,
  41. state_address,
  42. state_command,
  43. state_repeat_start,
  44. state_quick,
  45. state_read,
  46. state_write,
  47. };
  48. static const char *scx200_acb_state_name[] = {
  49. "idle",
  50. "address",
  51. "command",
  52. "repeat_start",
  53. "quick",
  54. "read",
  55. "write",
  56. };
  57. /* Physical interface */
  58. struct scx200_acb_iface {
  59. struct scx200_acb_iface *next;
  60. struct i2c_adapter adapter;
  61. unsigned base;
  62. struct mutex mutex;
  63. /* State machine data */
  64. enum scx200_acb_state state;
  65. int result;
  66. u8 address_byte;
  67. u8 command;
  68. u8 *ptr;
  69. char needs_reset;
  70. unsigned len;
  71. /* PCI device info */
  72. struct pci_dev *pdev;
  73. int bar;
  74. };
  75. /* Register Definitions */
  76. #define ACBSDA (iface->base + 0)
  77. #define ACBST (iface->base + 1)
  78. #define ACBST_SDAST 0x40 /* SDA Status */
  79. #define ACBST_BER 0x20
  80. #define ACBST_NEGACK 0x10 /* Negative Acknowledge */
  81. #define ACBST_STASTR 0x08 /* Stall After Start */
  82. #define ACBST_MASTER 0x02
  83. #define ACBCST (iface->base + 2)
  84. #define ACBCST_BB 0x02
  85. #define ACBCTL1 (iface->base + 3)
  86. #define ACBCTL1_STASTRE 0x80
  87. #define ACBCTL1_NMINTE 0x40
  88. #define ACBCTL1_ACK 0x10
  89. #define ACBCTL1_STOP 0x02
  90. #define ACBCTL1_START 0x01
  91. #define ACBADDR (iface->base + 4)
  92. #define ACBCTL2 (iface->base + 5)
  93. #define ACBCTL2_ENABLE 0x01
  94. /************************************************************************/
  95. static void scx200_acb_machine(struct scx200_acb_iface *iface, u8 status)
  96. {
  97. const char *errmsg;
  98. dev_dbg(&iface->adapter.dev, "state %s, status = 0x%02x\n",
  99. scx200_acb_state_name[iface->state], status);
  100. if (status & ACBST_BER) {
  101. errmsg = "bus error";
  102. goto error;
  103. }
  104. if (!(status & ACBST_MASTER)) {
  105. errmsg = "not master";
  106. goto error;
  107. }
  108. if (status & ACBST_NEGACK) {
  109. dev_dbg(&iface->adapter.dev, "negative ack in state %s\n",
  110. scx200_acb_state_name[iface->state]);
  111. iface->state = state_idle;
  112. iface->result = -ENXIO;
  113. outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
  114. outb(ACBST_STASTR | ACBST_NEGACK, ACBST);
  115. /* Reset the status register */
  116. outb(0, ACBST);
  117. return;
  118. }
  119. switch (iface->state) {
  120. case state_idle:
  121. dev_warn(&iface->adapter.dev, "interrupt in idle state\n");
  122. break;
  123. case state_address:
  124. /* Do a pointer write first */
  125. outb(iface->address_byte & ~1, ACBSDA);
  126. iface->state = state_command;
  127. break;
  128. case state_command:
  129. outb(iface->command, ACBSDA);
  130. if (iface->address_byte & 1)
  131. iface->state = state_repeat_start;
  132. else
  133. iface->state = state_write;
  134. break;
  135. case state_repeat_start:
  136. outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1);
  137. /* fallthrough */
  138. case state_quick:
  139. if (iface->address_byte & 1) {
  140. if (iface->len == 1)
  141. outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1);
  142. else
  143. outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1);
  144. outb(iface->address_byte, ACBSDA);
  145. iface->state = state_read;
  146. } else {
  147. outb(iface->address_byte, ACBSDA);
  148. iface->state = state_write;
  149. }
  150. break;
  151. case state_read:
  152. /* Set ACK if _next_ byte will be the last one */
  153. if (iface->len == 2)
  154. outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1);
  155. else
  156. outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1);
  157. if (iface->len == 1) {
  158. iface->result = 0;
  159. iface->state = state_idle;
  160. outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
  161. }
  162. *iface->ptr++ = inb(ACBSDA);
  163. --iface->len;
  164. break;
  165. case state_write:
  166. if (iface->len == 0) {
  167. iface->result = 0;
  168. iface->state = state_idle;
  169. outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
  170. break;
  171. }
  172. outb(*iface->ptr++, ACBSDA);
  173. --iface->len;
  174. break;
  175. }
  176. return;
  177. error:
  178. dev_err(&iface->adapter.dev,
  179. "%s in state %s (addr=0x%02x, len=%d, status=0x%02x)\n", errmsg,
  180. scx200_acb_state_name[iface->state], iface->address_byte,
  181. iface->len, status);
  182. iface->state = state_idle;
  183. iface->result = -EIO;
  184. iface->needs_reset = 1;
  185. }
  186. static void scx200_acb_poll(struct scx200_acb_iface *iface)
  187. {
  188. u8 status;
  189. unsigned long timeout;
  190. timeout = jiffies + POLL_TIMEOUT;
  191. while (1) {
  192. status = inb(ACBST);
  193. /* Reset the status register to avoid the hang */
  194. outb(0, ACBST);
  195. if ((status & (ACBST_SDAST|ACBST_BER|ACBST_NEGACK)) != 0) {
  196. scx200_acb_machine(iface, status);
  197. return;
  198. }
  199. if (time_after(jiffies, timeout))
  200. break;
  201. cpu_relax();
  202. cond_resched();
  203. }
  204. dev_err(&iface->adapter.dev, "timeout in state %s\n",
  205. scx200_acb_state_name[iface->state]);
  206. iface->state = state_idle;
  207. iface->result = -EIO;
  208. iface->needs_reset = 1;
  209. }
  210. static void scx200_acb_reset(struct scx200_acb_iface *iface)
  211. {
  212. /* Disable the ACCESS.bus device and Configure the SCL
  213. frequency: 16 clock cycles */
  214. outb(0x70, ACBCTL2);
  215. /* Polling mode */
  216. outb(0, ACBCTL1);
  217. /* Disable slave address */
  218. outb(0, ACBADDR);
  219. /* Enable the ACCESS.bus device */
  220. outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2);
  221. /* Free STALL after START */
  222. outb(inb(ACBCTL1) & ~(ACBCTL1_STASTRE | ACBCTL1_NMINTE), ACBCTL1);
  223. /* Send a STOP */
  224. outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
  225. /* Clear BER, NEGACK and STASTR bits */
  226. outb(ACBST_BER | ACBST_NEGACK | ACBST_STASTR, ACBST);
  227. /* Clear BB bit */
  228. outb(inb(ACBCST) | ACBCST_BB, ACBCST);
  229. }
  230. static s32 scx200_acb_smbus_xfer(struct i2c_adapter *adapter,
  231. u16 address, unsigned short flags,
  232. char rw, u8 command, int size,
  233. union i2c_smbus_data *data)
  234. {
  235. struct scx200_acb_iface *iface = i2c_get_adapdata(adapter);
  236. int len;
  237. u8 *buffer;
  238. u16 cur_word;
  239. int rc;
  240. switch (size) {
  241. case I2C_SMBUS_QUICK:
  242. len = 0;
  243. buffer = NULL;
  244. break;
  245. case I2C_SMBUS_BYTE:
  246. len = 1;
  247. buffer = rw ? &data->byte : &command;
  248. break;
  249. case I2C_SMBUS_BYTE_DATA:
  250. len = 1;
  251. buffer = &data->byte;
  252. break;
  253. case I2C_SMBUS_WORD_DATA:
  254. len = 2;
  255. cur_word = cpu_to_le16(data->word);
  256. buffer = (u8 *)&cur_word;
  257. break;
  258. case I2C_SMBUS_I2C_BLOCK_DATA:
  259. len = data->block[0];
  260. if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
  261. return -EINVAL;
  262. buffer = &data->block[1];
  263. break;
  264. default:
  265. return -EINVAL;
  266. }
  267. dev_dbg(&adapter->dev,
  268. "size=%d, address=0x%x, command=0x%x, len=%d, read=%d\n",
  269. size, address, command, len, rw);
  270. if (!len && rw == I2C_SMBUS_READ) {
  271. dev_dbg(&adapter->dev, "zero length read\n");
  272. return -EINVAL;
  273. }
  274. mutex_lock(&iface->mutex);
  275. iface->address_byte = (address << 1) | rw;
  276. iface->command = command;
  277. iface->ptr = buffer;
  278. iface->len = len;
  279. iface->result = -EINVAL;
  280. iface->needs_reset = 0;
  281. outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1);
  282. if (size == I2C_SMBUS_QUICK || size == I2C_SMBUS_BYTE)
  283. iface->state = state_quick;
  284. else
  285. iface->state = state_address;
  286. while (iface->state != state_idle)
  287. scx200_acb_poll(iface);
  288. if (iface->needs_reset)
  289. scx200_acb_reset(iface);
  290. rc = iface->result;
  291. mutex_unlock(&iface->mutex);
  292. if (rc == 0 && size == I2C_SMBUS_WORD_DATA && rw == I2C_SMBUS_READ)
  293. data->word = le16_to_cpu(cur_word);
  294. #ifdef DEBUG
  295. dev_dbg(&adapter->dev, "transfer done, result: %d", rc);
  296. if (buffer) {
  297. int i;
  298. printk(" data:");
  299. for (i = 0; i < len; ++i)
  300. printk(" %02x", buffer[i]);
  301. }
  302. printk("\n");
  303. #endif
  304. return rc;
  305. }
  306. static u32 scx200_acb_func(struct i2c_adapter *adapter)
  307. {
  308. return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
  309. I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
  310. I2C_FUNC_SMBUS_I2C_BLOCK;
  311. }
  312. /* For now, we only handle combined mode (smbus) */
  313. static const struct i2c_algorithm scx200_acb_algorithm = {
  314. .smbus_xfer = scx200_acb_smbus_xfer,
  315. .functionality = scx200_acb_func,
  316. };
  317. static struct scx200_acb_iface *scx200_acb_list;
  318. static DEFINE_MUTEX(scx200_acb_list_mutex);
  319. static __init int scx200_acb_probe(struct scx200_acb_iface *iface)
  320. {
  321. u8 val;
  322. /* Disable the ACCESS.bus device and Configure the SCL
  323. frequency: 16 clock cycles */
  324. outb(0x70, ACBCTL2);
  325. if (inb(ACBCTL2) != 0x70) {
  326. pr_debug(NAME ": ACBCTL2 readback failed\n");
  327. return -ENXIO;
  328. }
  329. outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1);
  330. val = inb(ACBCTL1);
  331. if (val) {
  332. pr_debug(NAME ": disabled, but ACBCTL1=0x%02x\n",
  333. val);
  334. return -ENXIO;
  335. }
  336. outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2);
  337. outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1);
  338. val = inb(ACBCTL1);
  339. if ((val & ACBCTL1_NMINTE) != ACBCTL1_NMINTE) {
  340. pr_debug(NAME ": enabled, but NMINTE won't be set, "
  341. "ACBCTL1=0x%02x\n", val);
  342. return -ENXIO;
  343. }
  344. return 0;
  345. }
  346. static __init struct scx200_acb_iface *scx200_create_iface(const char *text,
  347. struct device *dev, int index)
  348. {
  349. struct scx200_acb_iface *iface;
  350. struct i2c_adapter *adapter;
  351. iface = kzalloc(sizeof(*iface), GFP_KERNEL);
  352. if (!iface) {
  353. printk(KERN_ERR NAME ": can't allocate memory\n");
  354. return NULL;
  355. }
  356. adapter = &iface->adapter;
  357. i2c_set_adapdata(adapter, iface);
  358. snprintf(adapter->name, sizeof(adapter->name), "%s ACB%d", text, index);
  359. adapter->owner = THIS_MODULE;
  360. adapter->algo = &scx200_acb_algorithm;
  361. adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
  362. adapter->dev.parent = dev;
  363. mutex_init(&iface->mutex);
  364. return iface;
  365. }
  366. static int __init scx200_acb_create(struct scx200_acb_iface *iface)
  367. {
  368. struct i2c_adapter *adapter;
  369. int rc;
  370. adapter = &iface->adapter;
  371. rc = scx200_acb_probe(iface);
  372. if (rc) {
  373. printk(KERN_WARNING NAME ": probe failed\n");
  374. return rc;
  375. }
  376. scx200_acb_reset(iface);
  377. if (i2c_add_adapter(adapter) < 0) {
  378. printk(KERN_ERR NAME ": failed to register\n");
  379. return -ENODEV;
  380. }
  381. mutex_lock(&scx200_acb_list_mutex);
  382. iface->next = scx200_acb_list;
  383. scx200_acb_list = iface;
  384. mutex_unlock(&scx200_acb_list_mutex);
  385. return 0;
  386. }
  387. static __init int scx200_create_pci(const char *text, struct pci_dev *pdev,
  388. int bar)
  389. {
  390. struct scx200_acb_iface *iface;
  391. int rc;
  392. iface = scx200_create_iface(text, &pdev->dev, 0);
  393. if (iface == NULL)
  394. return -ENOMEM;
  395. iface->pdev = pdev;
  396. iface->bar = bar;
  397. rc = pci_enable_device_io(iface->pdev);
  398. if (rc)
  399. goto errout_free;
  400. rc = pci_request_region(iface->pdev, iface->bar, iface->adapter.name);
  401. if (rc) {
  402. printk(KERN_ERR NAME ": can't allocate PCI BAR %d\n",
  403. iface->bar);
  404. goto errout_free;
  405. }
  406. iface->base = pci_resource_start(iface->pdev, iface->bar);
  407. rc = scx200_acb_create(iface);
  408. if (rc == 0)
  409. return 0;
  410. pci_release_region(iface->pdev, iface->bar);
  411. pci_dev_put(iface->pdev);
  412. errout_free:
  413. kfree(iface);
  414. return rc;
  415. }
  416. static int __init scx200_create_isa(const char *text, unsigned long base,
  417. int index)
  418. {
  419. struct scx200_acb_iface *iface;
  420. int rc;
  421. iface = scx200_create_iface(text, NULL, index);
  422. if (iface == NULL)
  423. return -ENOMEM;
  424. if (!request_region(base, 8, iface->adapter.name)) {
  425. printk(KERN_ERR NAME ": can't allocate io 0x%lx-0x%lx\n",
  426. base, base + 8 - 1);
  427. rc = -EBUSY;
  428. goto errout_free;
  429. }
  430. iface->base = base;
  431. rc = scx200_acb_create(iface);
  432. if (rc == 0)
  433. return 0;
  434. release_region(base, 8);
  435. errout_free:
  436. kfree(iface);
  437. return rc;
  438. }
  439. /* Driver data is an index into the scx200_data array that indicates
  440. * the name and the BAR where the I/O address resource is located. ISA
  441. * devices are flagged with a bar value of -1 */
  442. static struct pci_device_id scx200_pci[] = {
  443. { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_BRIDGE),
  444. .driver_data = 0 },
  445. { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SC1100_BRIDGE),
  446. .driver_data = 0 },
  447. { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA),
  448. .driver_data = 1 },
  449. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA),
  450. .driver_data = 2 }
  451. };
  452. static struct {
  453. const char *name;
  454. int bar;
  455. } scx200_data[] = {
  456. { "SCx200", -1 },
  457. { "CS5535", 0 },
  458. { "CS5536", 0 }
  459. };
  460. static __init int scx200_scan_pci(void)
  461. {
  462. int data, dev;
  463. int rc = -ENODEV;
  464. struct pci_dev *pdev;
  465. for(dev = 0; dev < ARRAY_SIZE(scx200_pci); dev++) {
  466. pdev = pci_get_device(scx200_pci[dev].vendor,
  467. scx200_pci[dev].device, NULL);
  468. if (pdev == NULL)
  469. continue;
  470. data = scx200_pci[dev].driver_data;
  471. /* if .bar is greater or equal to zero, this is a
  472. * PCI device - otherwise, we assume
  473. that the ports are ISA based
  474. */
  475. if (scx200_data[data].bar >= 0)
  476. rc = scx200_create_pci(scx200_data[data].name, pdev,
  477. scx200_data[data].bar);
  478. else {
  479. int i;
  480. pci_dev_put(pdev);
  481. for (i = 0; i < MAX_DEVICES; ++i) {
  482. if (base[i] == 0)
  483. continue;
  484. rc = scx200_create_isa(scx200_data[data].name,
  485. base[i],
  486. i);
  487. }
  488. }
  489. break;
  490. }
  491. return rc;
  492. }
  493. static int __init scx200_acb_init(void)
  494. {
  495. int rc;
  496. pr_debug(NAME ": NatSemi SCx200 ACCESS.bus Driver\n");
  497. rc = scx200_scan_pci();
  498. /* If at least one bus was created, init must succeed */
  499. if (scx200_acb_list)
  500. return 0;
  501. return rc;
  502. }
  503. static void __exit scx200_acb_cleanup(void)
  504. {
  505. struct scx200_acb_iface *iface;
  506. mutex_lock(&scx200_acb_list_mutex);
  507. while ((iface = scx200_acb_list) != NULL) {
  508. scx200_acb_list = iface->next;
  509. mutex_unlock(&scx200_acb_list_mutex);
  510. i2c_del_adapter(&iface->adapter);
  511. if (iface->pdev) {
  512. pci_release_region(iface->pdev, iface->bar);
  513. pci_dev_put(iface->pdev);
  514. }
  515. else
  516. release_region(iface->base, 8);
  517. kfree(iface);
  518. mutex_lock(&scx200_acb_list_mutex);
  519. }
  520. mutex_unlock(&scx200_acb_list_mutex);
  521. }
  522. module_init(scx200_acb_init);
  523. module_exit(scx200_acb_cleanup);