vmwgfx_drv.c 20 KB

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  1. /**************************************************************************
  2. *
  3. * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
  4. * All Rights Reserved.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. **************************************************************************/
  27. #include "drmP.h"
  28. #include "vmwgfx_drv.h"
  29. #include "ttm/ttm_placement.h"
  30. #include "ttm/ttm_bo_driver.h"
  31. #include "ttm/ttm_object.h"
  32. #include "ttm/ttm_module.h"
  33. #define VMWGFX_DRIVER_NAME "vmwgfx"
  34. #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
  35. #define VMWGFX_CHIP_SVGAII 0
  36. #define VMW_FB_RESERVATION 0
  37. /**
  38. * Fully encoded drm commands. Might move to vmw_drm.h
  39. */
  40. #define DRM_IOCTL_VMW_GET_PARAM \
  41. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
  42. struct drm_vmw_getparam_arg)
  43. #define DRM_IOCTL_VMW_ALLOC_DMABUF \
  44. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
  45. union drm_vmw_alloc_dmabuf_arg)
  46. #define DRM_IOCTL_VMW_UNREF_DMABUF \
  47. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
  48. struct drm_vmw_unref_dmabuf_arg)
  49. #define DRM_IOCTL_VMW_CURSOR_BYPASS \
  50. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
  51. struct drm_vmw_cursor_bypass_arg)
  52. #define DRM_IOCTL_VMW_CONTROL_STREAM \
  53. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
  54. struct drm_vmw_control_stream_arg)
  55. #define DRM_IOCTL_VMW_CLAIM_STREAM \
  56. DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
  57. struct drm_vmw_stream_arg)
  58. #define DRM_IOCTL_VMW_UNREF_STREAM \
  59. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
  60. struct drm_vmw_stream_arg)
  61. #define DRM_IOCTL_VMW_CREATE_CONTEXT \
  62. DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
  63. struct drm_vmw_context_arg)
  64. #define DRM_IOCTL_VMW_UNREF_CONTEXT \
  65. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
  66. struct drm_vmw_context_arg)
  67. #define DRM_IOCTL_VMW_CREATE_SURFACE \
  68. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
  69. union drm_vmw_surface_create_arg)
  70. #define DRM_IOCTL_VMW_UNREF_SURFACE \
  71. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
  72. struct drm_vmw_surface_arg)
  73. #define DRM_IOCTL_VMW_REF_SURFACE \
  74. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
  75. union drm_vmw_surface_reference_arg)
  76. #define DRM_IOCTL_VMW_EXECBUF \
  77. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
  78. struct drm_vmw_execbuf_arg)
  79. #define DRM_IOCTL_VMW_FIFO_DEBUG \
  80. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FIFO_DEBUG, \
  81. struct drm_vmw_fifo_debug_arg)
  82. #define DRM_IOCTL_VMW_FENCE_WAIT \
  83. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
  84. struct drm_vmw_fence_wait_arg)
  85. /**
  86. * The core DRM version of this macro doesn't account for
  87. * DRM_COMMAND_BASE.
  88. */
  89. #define VMW_IOCTL_DEF(ioctl, func, flags) \
  90. [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func}
  91. /**
  92. * Ioctl definitions.
  93. */
  94. static struct drm_ioctl_desc vmw_ioctls[] = {
  95. VMW_IOCTL_DEF(DRM_IOCTL_VMW_GET_PARAM, vmw_getparam_ioctl,
  96. DRM_AUTH | DRM_UNLOCKED),
  97. VMW_IOCTL_DEF(DRM_IOCTL_VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
  98. DRM_AUTH | DRM_UNLOCKED),
  99. VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
  100. DRM_AUTH | DRM_UNLOCKED),
  101. VMW_IOCTL_DEF(DRM_IOCTL_VMW_CURSOR_BYPASS,
  102. vmw_kms_cursor_bypass_ioctl,
  103. DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
  104. VMW_IOCTL_DEF(DRM_IOCTL_VMW_CONTROL_STREAM, vmw_overlay_ioctl,
  105. DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
  106. VMW_IOCTL_DEF(DRM_IOCTL_VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
  107. DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
  108. VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
  109. DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
  110. VMW_IOCTL_DEF(DRM_IOCTL_VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
  111. DRM_AUTH | DRM_UNLOCKED),
  112. VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
  113. DRM_AUTH | DRM_UNLOCKED),
  114. VMW_IOCTL_DEF(DRM_IOCTL_VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
  115. DRM_AUTH | DRM_UNLOCKED),
  116. VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
  117. DRM_AUTH | DRM_UNLOCKED),
  118. VMW_IOCTL_DEF(DRM_IOCTL_VMW_REF_SURFACE, vmw_surface_reference_ioctl,
  119. DRM_AUTH | DRM_UNLOCKED),
  120. VMW_IOCTL_DEF(DRM_IOCTL_VMW_EXECBUF, vmw_execbuf_ioctl,
  121. DRM_AUTH | DRM_UNLOCKED),
  122. VMW_IOCTL_DEF(DRM_IOCTL_VMW_FIFO_DEBUG, vmw_fifo_debug_ioctl,
  123. DRM_AUTH | DRM_ROOT_ONLY | DRM_MASTER | DRM_UNLOCKED),
  124. VMW_IOCTL_DEF(DRM_IOCTL_VMW_FENCE_WAIT, vmw_fence_wait_ioctl,
  125. DRM_AUTH | DRM_UNLOCKED)
  126. };
  127. static struct pci_device_id vmw_pci_id_list[] = {
  128. {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
  129. {0, 0, 0}
  130. };
  131. static char *vmw_devname = "vmwgfx";
  132. static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
  133. static void vmw_master_init(struct vmw_master *);
  134. static void vmw_print_capabilities(uint32_t capabilities)
  135. {
  136. DRM_INFO("Capabilities:\n");
  137. if (capabilities & SVGA_CAP_RECT_COPY)
  138. DRM_INFO(" Rect copy.\n");
  139. if (capabilities & SVGA_CAP_CURSOR)
  140. DRM_INFO(" Cursor.\n");
  141. if (capabilities & SVGA_CAP_CURSOR_BYPASS)
  142. DRM_INFO(" Cursor bypass.\n");
  143. if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
  144. DRM_INFO(" Cursor bypass 2.\n");
  145. if (capabilities & SVGA_CAP_8BIT_EMULATION)
  146. DRM_INFO(" 8bit emulation.\n");
  147. if (capabilities & SVGA_CAP_ALPHA_CURSOR)
  148. DRM_INFO(" Alpha cursor.\n");
  149. if (capabilities & SVGA_CAP_3D)
  150. DRM_INFO(" 3D.\n");
  151. if (capabilities & SVGA_CAP_EXTENDED_FIFO)
  152. DRM_INFO(" Extended Fifo.\n");
  153. if (capabilities & SVGA_CAP_MULTIMON)
  154. DRM_INFO(" Multimon.\n");
  155. if (capabilities & SVGA_CAP_PITCHLOCK)
  156. DRM_INFO(" Pitchlock.\n");
  157. if (capabilities & SVGA_CAP_IRQMASK)
  158. DRM_INFO(" Irq mask.\n");
  159. if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
  160. DRM_INFO(" Display Topology.\n");
  161. if (capabilities & SVGA_CAP_GMR)
  162. DRM_INFO(" GMR.\n");
  163. if (capabilities & SVGA_CAP_TRACES)
  164. DRM_INFO(" Traces.\n");
  165. }
  166. static int vmw_request_device(struct vmw_private *dev_priv)
  167. {
  168. int ret;
  169. vmw_kms_save_vga(dev_priv);
  170. ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
  171. if (unlikely(ret != 0)) {
  172. DRM_ERROR("Unable to initialize FIFO.\n");
  173. return ret;
  174. }
  175. return 0;
  176. }
  177. static void vmw_release_device(struct vmw_private *dev_priv)
  178. {
  179. vmw_fifo_release(dev_priv, &dev_priv->fifo);
  180. vmw_kms_restore_vga(dev_priv);
  181. }
  182. static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
  183. {
  184. struct vmw_private *dev_priv;
  185. int ret;
  186. dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
  187. if (unlikely(dev_priv == NULL)) {
  188. DRM_ERROR("Failed allocating a device private struct.\n");
  189. return -ENOMEM;
  190. }
  191. memset(dev_priv, 0, sizeof(*dev_priv));
  192. dev_priv->dev = dev;
  193. dev_priv->vmw_chipset = chipset;
  194. mutex_init(&dev_priv->hw_mutex);
  195. mutex_init(&dev_priv->cmdbuf_mutex);
  196. rwlock_init(&dev_priv->resource_lock);
  197. idr_init(&dev_priv->context_idr);
  198. idr_init(&dev_priv->surface_idr);
  199. idr_init(&dev_priv->stream_idr);
  200. ida_init(&dev_priv->gmr_ida);
  201. mutex_init(&dev_priv->init_mutex);
  202. init_waitqueue_head(&dev_priv->fence_queue);
  203. init_waitqueue_head(&dev_priv->fifo_queue);
  204. atomic_set(&dev_priv->fence_queue_waiters, 0);
  205. atomic_set(&dev_priv->fifo_queue_waiters, 0);
  206. INIT_LIST_HEAD(&dev_priv->gmr_lru);
  207. dev_priv->io_start = pci_resource_start(dev->pdev, 0);
  208. dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
  209. dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
  210. mutex_lock(&dev_priv->hw_mutex);
  211. dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
  212. if (dev_priv->capabilities & SVGA_CAP_GMR) {
  213. dev_priv->max_gmr_descriptors =
  214. vmw_read(dev_priv,
  215. SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
  216. dev_priv->max_gmr_ids =
  217. vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
  218. }
  219. dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
  220. dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
  221. dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
  222. dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
  223. mutex_unlock(&dev_priv->hw_mutex);
  224. vmw_print_capabilities(dev_priv->capabilities);
  225. if (dev_priv->capabilities & SVGA_CAP_GMR) {
  226. DRM_INFO("Max GMR ids is %u\n",
  227. (unsigned)dev_priv->max_gmr_ids);
  228. DRM_INFO("Max GMR descriptors is %u\n",
  229. (unsigned)dev_priv->max_gmr_descriptors);
  230. }
  231. DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
  232. dev_priv->vram_start, dev_priv->vram_size / 1024);
  233. DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
  234. dev_priv->mmio_start, dev_priv->mmio_size / 1024);
  235. ret = vmw_ttm_global_init(dev_priv);
  236. if (unlikely(ret != 0))
  237. goto out_err0;
  238. vmw_master_init(&dev_priv->fbdev_master);
  239. ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
  240. dev_priv->active_master = &dev_priv->fbdev_master;
  241. ret = ttm_bo_device_init(&dev_priv->bdev,
  242. dev_priv->bo_global_ref.ref.object,
  243. &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET,
  244. false);
  245. if (unlikely(ret != 0)) {
  246. DRM_ERROR("Failed initializing TTM buffer object driver.\n");
  247. goto out_err1;
  248. }
  249. ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
  250. (dev_priv->vram_size >> PAGE_SHIFT));
  251. if (unlikely(ret != 0)) {
  252. DRM_ERROR("Failed initializing memory manager for VRAM.\n");
  253. goto out_err2;
  254. }
  255. dev_priv->mmio_mtrr = drm_mtrr_add(dev_priv->mmio_start,
  256. dev_priv->mmio_size, DRM_MTRR_WC);
  257. dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
  258. dev_priv->mmio_size);
  259. if (unlikely(dev_priv->mmio_virt == NULL)) {
  260. ret = -ENOMEM;
  261. DRM_ERROR("Failed mapping MMIO.\n");
  262. goto out_err3;
  263. }
  264. dev_priv->tdev = ttm_object_device_init
  265. (dev_priv->mem_global_ref.object, 12);
  266. if (unlikely(dev_priv->tdev == NULL)) {
  267. DRM_ERROR("Unable to initialize TTM object management.\n");
  268. ret = -ENOMEM;
  269. goto out_err4;
  270. }
  271. dev->dev_private = dev_priv;
  272. if (!dev->devname)
  273. dev->devname = vmw_devname;
  274. if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
  275. ret = drm_irq_install(dev);
  276. if (unlikely(ret != 0)) {
  277. DRM_ERROR("Failed installing irq: %d\n", ret);
  278. goto out_no_irq;
  279. }
  280. }
  281. ret = pci_request_regions(dev->pdev, "vmwgfx probe");
  282. dev_priv->stealth = (ret != 0);
  283. if (dev_priv->stealth) {
  284. /**
  285. * Request at least the mmio PCI resource.
  286. */
  287. DRM_INFO("It appears like vesafb is loaded. "
  288. "Ignore above error if any. Entering stealth mode.\n");
  289. ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
  290. if (unlikely(ret != 0)) {
  291. DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
  292. goto out_no_device;
  293. }
  294. vmw_kms_init(dev_priv);
  295. vmw_overlay_init(dev_priv);
  296. } else {
  297. ret = vmw_request_device(dev_priv);
  298. if (unlikely(ret != 0))
  299. goto out_no_device;
  300. vmw_kms_init(dev_priv);
  301. vmw_overlay_init(dev_priv);
  302. vmw_fb_init(dev_priv);
  303. }
  304. return 0;
  305. out_no_device:
  306. if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
  307. drm_irq_uninstall(dev_priv->dev);
  308. if (dev->devname == vmw_devname)
  309. dev->devname = NULL;
  310. out_no_irq:
  311. ttm_object_device_release(&dev_priv->tdev);
  312. out_err4:
  313. iounmap(dev_priv->mmio_virt);
  314. out_err3:
  315. drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
  316. dev_priv->mmio_size, DRM_MTRR_WC);
  317. (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
  318. out_err2:
  319. (void)ttm_bo_device_release(&dev_priv->bdev);
  320. out_err1:
  321. vmw_ttm_global_release(dev_priv);
  322. out_err0:
  323. ida_destroy(&dev_priv->gmr_ida);
  324. idr_destroy(&dev_priv->surface_idr);
  325. idr_destroy(&dev_priv->context_idr);
  326. idr_destroy(&dev_priv->stream_idr);
  327. kfree(dev_priv);
  328. return ret;
  329. }
  330. static int vmw_driver_unload(struct drm_device *dev)
  331. {
  332. struct vmw_private *dev_priv = vmw_priv(dev);
  333. DRM_INFO(VMWGFX_DRIVER_NAME " unload.\n");
  334. if (!dev_priv->stealth) {
  335. vmw_fb_close(dev_priv);
  336. vmw_kms_close(dev_priv);
  337. vmw_overlay_close(dev_priv);
  338. vmw_release_device(dev_priv);
  339. pci_release_regions(dev->pdev);
  340. } else {
  341. vmw_kms_close(dev_priv);
  342. vmw_overlay_close(dev_priv);
  343. pci_release_region(dev->pdev, 2);
  344. }
  345. if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
  346. drm_irq_uninstall(dev_priv->dev);
  347. if (dev->devname == vmw_devname)
  348. dev->devname = NULL;
  349. ttm_object_device_release(&dev_priv->tdev);
  350. iounmap(dev_priv->mmio_virt);
  351. drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
  352. dev_priv->mmio_size, DRM_MTRR_WC);
  353. (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
  354. (void)ttm_bo_device_release(&dev_priv->bdev);
  355. vmw_ttm_global_release(dev_priv);
  356. ida_destroy(&dev_priv->gmr_ida);
  357. idr_destroy(&dev_priv->surface_idr);
  358. idr_destroy(&dev_priv->context_idr);
  359. idr_destroy(&dev_priv->stream_idr);
  360. kfree(dev_priv);
  361. return 0;
  362. }
  363. static void vmw_postclose(struct drm_device *dev,
  364. struct drm_file *file_priv)
  365. {
  366. struct vmw_fpriv *vmw_fp;
  367. vmw_fp = vmw_fpriv(file_priv);
  368. ttm_object_file_release(&vmw_fp->tfile);
  369. if (vmw_fp->locked_master)
  370. drm_master_put(&vmw_fp->locked_master);
  371. kfree(vmw_fp);
  372. }
  373. static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
  374. {
  375. struct vmw_private *dev_priv = vmw_priv(dev);
  376. struct vmw_fpriv *vmw_fp;
  377. int ret = -ENOMEM;
  378. vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
  379. if (unlikely(vmw_fp == NULL))
  380. return ret;
  381. vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
  382. if (unlikely(vmw_fp->tfile == NULL))
  383. goto out_no_tfile;
  384. file_priv->driver_priv = vmw_fp;
  385. if (unlikely(dev_priv->bdev.dev_mapping == NULL))
  386. dev_priv->bdev.dev_mapping =
  387. file_priv->filp->f_path.dentry->d_inode->i_mapping;
  388. return 0;
  389. out_no_tfile:
  390. kfree(vmw_fp);
  391. return ret;
  392. }
  393. static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
  394. unsigned long arg)
  395. {
  396. struct drm_file *file_priv = filp->private_data;
  397. struct drm_device *dev = file_priv->minor->dev;
  398. unsigned int nr = DRM_IOCTL_NR(cmd);
  399. /*
  400. * Do extra checking on driver private ioctls.
  401. */
  402. if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
  403. && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
  404. struct drm_ioctl_desc *ioctl =
  405. &vmw_ioctls[nr - DRM_COMMAND_BASE];
  406. if (unlikely(ioctl->cmd != cmd)) {
  407. DRM_ERROR("Invalid command format, ioctl %d\n",
  408. nr - DRM_COMMAND_BASE);
  409. return -EINVAL;
  410. }
  411. }
  412. return drm_ioctl(filp, cmd, arg);
  413. }
  414. static int vmw_firstopen(struct drm_device *dev)
  415. {
  416. struct vmw_private *dev_priv = vmw_priv(dev);
  417. dev_priv->is_opened = true;
  418. return 0;
  419. }
  420. static void vmw_lastclose(struct drm_device *dev)
  421. {
  422. struct vmw_private *dev_priv = vmw_priv(dev);
  423. struct drm_crtc *crtc;
  424. struct drm_mode_set set;
  425. int ret;
  426. /**
  427. * Do nothing on the lastclose call from drm_unload.
  428. */
  429. if (!dev_priv->is_opened)
  430. return;
  431. dev_priv->is_opened = false;
  432. set.x = 0;
  433. set.y = 0;
  434. set.fb = NULL;
  435. set.mode = NULL;
  436. set.connectors = NULL;
  437. set.num_connectors = 0;
  438. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  439. set.crtc = crtc;
  440. ret = crtc->funcs->set_config(&set);
  441. WARN_ON(ret != 0);
  442. }
  443. }
  444. static void vmw_master_init(struct vmw_master *vmaster)
  445. {
  446. ttm_lock_init(&vmaster->lock);
  447. }
  448. static int vmw_master_create(struct drm_device *dev,
  449. struct drm_master *master)
  450. {
  451. struct vmw_master *vmaster;
  452. DRM_INFO("Master create.\n");
  453. vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
  454. if (unlikely(vmaster == NULL))
  455. return -ENOMEM;
  456. ttm_lock_init(&vmaster->lock);
  457. ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
  458. master->driver_priv = vmaster;
  459. return 0;
  460. }
  461. static void vmw_master_destroy(struct drm_device *dev,
  462. struct drm_master *master)
  463. {
  464. struct vmw_master *vmaster = vmw_master(master);
  465. DRM_INFO("Master destroy.\n");
  466. master->driver_priv = NULL;
  467. kfree(vmaster);
  468. }
  469. static int vmw_master_set(struct drm_device *dev,
  470. struct drm_file *file_priv,
  471. bool from_open)
  472. {
  473. struct vmw_private *dev_priv = vmw_priv(dev);
  474. struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
  475. struct vmw_master *active = dev_priv->active_master;
  476. struct vmw_master *vmaster = vmw_master(file_priv->master);
  477. int ret = 0;
  478. DRM_INFO("Master set.\n");
  479. if (dev_priv->stealth) {
  480. ret = vmw_request_device(dev_priv);
  481. if (unlikely(ret != 0))
  482. return ret;
  483. }
  484. if (active) {
  485. BUG_ON(active != &dev_priv->fbdev_master);
  486. ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
  487. if (unlikely(ret != 0))
  488. goto out_no_active_lock;
  489. ttm_lock_set_kill(&active->lock, true, SIGTERM);
  490. ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
  491. if (unlikely(ret != 0)) {
  492. DRM_ERROR("Unable to clean VRAM on "
  493. "master drop.\n");
  494. }
  495. dev_priv->active_master = NULL;
  496. }
  497. ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
  498. if (!from_open) {
  499. ttm_vt_unlock(&vmaster->lock);
  500. BUG_ON(vmw_fp->locked_master != file_priv->master);
  501. drm_master_put(&vmw_fp->locked_master);
  502. }
  503. dev_priv->active_master = vmaster;
  504. return 0;
  505. out_no_active_lock:
  506. vmw_release_device(dev_priv);
  507. return ret;
  508. }
  509. static void vmw_master_drop(struct drm_device *dev,
  510. struct drm_file *file_priv,
  511. bool from_release)
  512. {
  513. struct vmw_private *dev_priv = vmw_priv(dev);
  514. struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
  515. struct vmw_master *vmaster = vmw_master(file_priv->master);
  516. int ret;
  517. DRM_INFO("Master drop.\n");
  518. /**
  519. * Make sure the master doesn't disappear while we have
  520. * it locked.
  521. */
  522. vmw_fp->locked_master = drm_master_get(file_priv->master);
  523. ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
  524. if (unlikely((ret != 0))) {
  525. DRM_ERROR("Unable to lock TTM at VT switch.\n");
  526. drm_master_put(&vmw_fp->locked_master);
  527. }
  528. ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
  529. if (dev_priv->stealth) {
  530. ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
  531. if (unlikely(ret != 0))
  532. DRM_ERROR("Unable to clean VRAM on master drop.\n");
  533. vmw_release_device(dev_priv);
  534. }
  535. dev_priv->active_master = &dev_priv->fbdev_master;
  536. ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
  537. ttm_vt_unlock(&dev_priv->fbdev_master.lock);
  538. if (!dev_priv->stealth)
  539. vmw_fb_on(dev_priv);
  540. }
  541. static void vmw_remove(struct pci_dev *pdev)
  542. {
  543. struct drm_device *dev = pci_get_drvdata(pdev);
  544. drm_put_dev(dev);
  545. }
  546. static struct drm_driver driver = {
  547. .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
  548. DRIVER_MODESET,
  549. .load = vmw_driver_load,
  550. .unload = vmw_driver_unload,
  551. .firstopen = vmw_firstopen,
  552. .lastclose = vmw_lastclose,
  553. .irq_preinstall = vmw_irq_preinstall,
  554. .irq_postinstall = vmw_irq_postinstall,
  555. .irq_uninstall = vmw_irq_uninstall,
  556. .irq_handler = vmw_irq_handler,
  557. .reclaim_buffers_locked = NULL,
  558. .get_map_ofs = drm_core_get_map_ofs,
  559. .get_reg_ofs = drm_core_get_reg_ofs,
  560. .ioctls = vmw_ioctls,
  561. .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
  562. .dma_quiescent = NULL, /*vmw_dma_quiescent, */
  563. .master_create = vmw_master_create,
  564. .master_destroy = vmw_master_destroy,
  565. .master_set = vmw_master_set,
  566. .master_drop = vmw_master_drop,
  567. .open = vmw_driver_open,
  568. .postclose = vmw_postclose,
  569. .fops = {
  570. .owner = THIS_MODULE,
  571. .open = drm_open,
  572. .release = drm_release,
  573. .unlocked_ioctl = vmw_unlocked_ioctl,
  574. .mmap = vmw_mmap,
  575. .poll = drm_poll,
  576. .fasync = drm_fasync,
  577. #if defined(CONFIG_COMPAT)
  578. .compat_ioctl = drm_compat_ioctl,
  579. #endif
  580. },
  581. .pci_driver = {
  582. .name = VMWGFX_DRIVER_NAME,
  583. .id_table = vmw_pci_id_list,
  584. .probe = vmw_probe,
  585. .remove = vmw_remove
  586. },
  587. .name = VMWGFX_DRIVER_NAME,
  588. .desc = VMWGFX_DRIVER_DESC,
  589. .date = VMWGFX_DRIVER_DATE,
  590. .major = VMWGFX_DRIVER_MAJOR,
  591. .minor = VMWGFX_DRIVER_MINOR,
  592. .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
  593. };
  594. static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  595. {
  596. return drm_get_dev(pdev, ent, &driver);
  597. }
  598. static int __init vmwgfx_init(void)
  599. {
  600. int ret;
  601. ret = drm_init(&driver);
  602. if (ret)
  603. DRM_ERROR("Failed initializing DRM.\n");
  604. return ret;
  605. }
  606. static void __exit vmwgfx_exit(void)
  607. {
  608. drm_exit(&driver);
  609. }
  610. module_init(vmwgfx_init);
  611. module_exit(vmwgfx_exit);
  612. MODULE_AUTHOR("VMware Inc. and others");
  613. MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
  614. MODULE_LICENSE("GPL and additional rights");