radeon_object.c 12 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30. * Dave Airlie
  31. */
  32. #include <linux/list.h>
  33. #include <drm/drmP.h>
  34. #include "radeon_drm.h"
  35. #include "radeon.h"
  36. int radeon_ttm_init(struct radeon_device *rdev);
  37. void radeon_ttm_fini(struct radeon_device *rdev);
  38. static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  39. /*
  40. * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  41. * function are calling it.
  42. */
  43. static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  44. {
  45. struct radeon_bo *bo;
  46. bo = container_of(tbo, struct radeon_bo, tbo);
  47. mutex_lock(&bo->rdev->gem.mutex);
  48. list_del_init(&bo->list);
  49. mutex_unlock(&bo->rdev->gem.mutex);
  50. radeon_bo_clear_surface_reg(bo);
  51. kfree(bo);
  52. }
  53. bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  54. {
  55. if (bo->destroy == &radeon_ttm_bo_destroy)
  56. return true;
  57. return false;
  58. }
  59. void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  60. {
  61. u32 c = 0;
  62. rbo->placement.fpfn = 0;
  63. rbo->placement.lpfn = 0;
  64. rbo->placement.placement = rbo->placements;
  65. rbo->placement.busy_placement = rbo->placements;
  66. if (domain & RADEON_GEM_DOMAIN_VRAM)
  67. rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  68. TTM_PL_FLAG_VRAM;
  69. if (domain & RADEON_GEM_DOMAIN_GTT)
  70. rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
  71. if (domain & RADEON_GEM_DOMAIN_CPU)
  72. rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  73. if (!c)
  74. rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  75. rbo->placement.num_placement = c;
  76. rbo->placement.num_busy_placement = c;
  77. }
  78. int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
  79. unsigned long size, bool kernel, u32 domain,
  80. struct radeon_bo **bo_ptr)
  81. {
  82. struct radeon_bo *bo;
  83. enum ttm_bo_type type;
  84. int r;
  85. if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
  86. rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
  87. }
  88. if (kernel) {
  89. type = ttm_bo_type_kernel;
  90. } else {
  91. type = ttm_bo_type_device;
  92. }
  93. *bo_ptr = NULL;
  94. bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
  95. if (bo == NULL)
  96. return -ENOMEM;
  97. bo->rdev = rdev;
  98. bo->gobj = gobj;
  99. bo->surface_reg = -1;
  100. INIT_LIST_HEAD(&bo->list);
  101. radeon_ttm_placement_from_domain(bo, domain);
  102. /* Kernel allocation are uninterruptible */
  103. r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
  104. &bo->placement, 0, 0, !kernel, NULL, size,
  105. &radeon_ttm_bo_destroy);
  106. if (unlikely(r != 0)) {
  107. if (r != -ERESTARTSYS)
  108. dev_err(rdev->dev,
  109. "object_init failed for (%lu, 0x%08X)\n",
  110. size, domain);
  111. return r;
  112. }
  113. *bo_ptr = bo;
  114. if (gobj) {
  115. mutex_lock(&bo->rdev->gem.mutex);
  116. list_add_tail(&bo->list, &rdev->gem.objects);
  117. mutex_unlock(&bo->rdev->gem.mutex);
  118. }
  119. return 0;
  120. }
  121. int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
  122. {
  123. bool is_iomem;
  124. int r;
  125. if (bo->kptr) {
  126. if (ptr) {
  127. *ptr = bo->kptr;
  128. }
  129. return 0;
  130. }
  131. r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
  132. if (r) {
  133. return r;
  134. }
  135. bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
  136. if (ptr) {
  137. *ptr = bo->kptr;
  138. }
  139. radeon_bo_check_tiling(bo, 0, 0);
  140. return 0;
  141. }
  142. void radeon_bo_kunmap(struct radeon_bo *bo)
  143. {
  144. if (bo->kptr == NULL)
  145. return;
  146. bo->kptr = NULL;
  147. radeon_bo_check_tiling(bo, 0, 0);
  148. ttm_bo_kunmap(&bo->kmap);
  149. }
  150. void radeon_bo_unref(struct radeon_bo **bo)
  151. {
  152. struct ttm_buffer_object *tbo;
  153. if ((*bo) == NULL)
  154. return;
  155. tbo = &((*bo)->tbo);
  156. ttm_bo_unref(&tbo);
  157. if (tbo == NULL)
  158. *bo = NULL;
  159. }
  160. int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
  161. {
  162. int r, i;
  163. radeon_ttm_placement_from_domain(bo, domain);
  164. if (bo->pin_count) {
  165. bo->pin_count++;
  166. if (gpu_addr)
  167. *gpu_addr = radeon_bo_gpu_offset(bo);
  168. return 0;
  169. }
  170. radeon_ttm_placement_from_domain(bo, domain);
  171. for (i = 0; i < bo->placement.num_placement; i++)
  172. bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
  173. r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
  174. if (likely(r == 0)) {
  175. bo->pin_count = 1;
  176. if (gpu_addr != NULL)
  177. *gpu_addr = radeon_bo_gpu_offset(bo);
  178. }
  179. if (unlikely(r != 0))
  180. dev_err(bo->rdev->dev, "%p pin failed\n", bo);
  181. return r;
  182. }
  183. int radeon_bo_unpin(struct radeon_bo *bo)
  184. {
  185. int r, i;
  186. if (!bo->pin_count) {
  187. dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
  188. return 0;
  189. }
  190. bo->pin_count--;
  191. if (bo->pin_count)
  192. return 0;
  193. for (i = 0; i < bo->placement.num_placement; i++)
  194. bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
  195. r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
  196. if (unlikely(r != 0))
  197. dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
  198. return r;
  199. }
  200. int radeon_bo_evict_vram(struct radeon_device *rdev)
  201. {
  202. if (rdev->flags & RADEON_IS_IGP) {
  203. if (rdev->mc.igp_sideport_enabled == false)
  204. /* Useless to evict on IGP chips */
  205. return 0;
  206. }
  207. return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
  208. }
  209. void radeon_bo_force_delete(struct radeon_device *rdev)
  210. {
  211. struct radeon_bo *bo, *n;
  212. struct drm_gem_object *gobj;
  213. if (list_empty(&rdev->gem.objects)) {
  214. return;
  215. }
  216. dev_err(rdev->dev, "Userspace still has active objects !\n");
  217. list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
  218. mutex_lock(&rdev->ddev->struct_mutex);
  219. gobj = bo->gobj;
  220. dev_err(rdev->dev, "%p %p %lu %lu force free\n",
  221. gobj, bo, (unsigned long)gobj->size,
  222. *((unsigned long *)&gobj->refcount));
  223. mutex_lock(&bo->rdev->gem.mutex);
  224. list_del_init(&bo->list);
  225. mutex_unlock(&bo->rdev->gem.mutex);
  226. radeon_bo_unref(&bo);
  227. gobj->driver_private = NULL;
  228. drm_gem_object_unreference(gobj);
  229. mutex_unlock(&rdev->ddev->struct_mutex);
  230. }
  231. }
  232. int radeon_bo_init(struct radeon_device *rdev)
  233. {
  234. /* Add an MTRR for the VRAM */
  235. rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
  236. MTRR_TYPE_WRCOMB, 1);
  237. DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
  238. rdev->mc.mc_vram_size >> 20,
  239. (unsigned long long)rdev->mc.aper_size >> 20);
  240. DRM_INFO("RAM width %dbits %cDR\n",
  241. rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
  242. return radeon_ttm_init(rdev);
  243. }
  244. void radeon_bo_fini(struct radeon_device *rdev)
  245. {
  246. radeon_ttm_fini(rdev);
  247. }
  248. void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
  249. struct list_head *head)
  250. {
  251. if (lobj->wdomain) {
  252. list_add(&lobj->list, head);
  253. } else {
  254. list_add_tail(&lobj->list, head);
  255. }
  256. }
  257. int radeon_bo_list_reserve(struct list_head *head)
  258. {
  259. struct radeon_bo_list *lobj;
  260. int r;
  261. list_for_each_entry(lobj, head, list){
  262. r = radeon_bo_reserve(lobj->bo, false);
  263. if (unlikely(r != 0))
  264. return r;
  265. }
  266. return 0;
  267. }
  268. void radeon_bo_list_unreserve(struct list_head *head)
  269. {
  270. struct radeon_bo_list *lobj;
  271. list_for_each_entry(lobj, head, list) {
  272. /* only unreserve object we successfully reserved */
  273. if (radeon_bo_is_reserved(lobj->bo))
  274. radeon_bo_unreserve(lobj->bo);
  275. }
  276. }
  277. int radeon_bo_list_validate(struct list_head *head, void *fence)
  278. {
  279. struct radeon_bo_list *lobj;
  280. struct radeon_bo *bo;
  281. struct radeon_fence *old_fence = NULL;
  282. int r;
  283. r = radeon_bo_list_reserve(head);
  284. if (unlikely(r != 0)) {
  285. return r;
  286. }
  287. list_for_each_entry(lobj, head, list) {
  288. bo = lobj->bo;
  289. if (!bo->pin_count) {
  290. if (lobj->wdomain) {
  291. radeon_ttm_placement_from_domain(bo,
  292. lobj->wdomain);
  293. } else {
  294. radeon_ttm_placement_from_domain(bo,
  295. lobj->rdomain);
  296. }
  297. r = ttm_bo_validate(&bo->tbo, &bo->placement,
  298. true, false);
  299. if (unlikely(r))
  300. return r;
  301. }
  302. lobj->gpu_offset = radeon_bo_gpu_offset(bo);
  303. lobj->tiling_flags = bo->tiling_flags;
  304. if (fence) {
  305. old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
  306. bo->tbo.sync_obj = radeon_fence_ref(fence);
  307. bo->tbo.sync_obj_arg = NULL;
  308. }
  309. if (old_fence) {
  310. radeon_fence_unref(&old_fence);
  311. }
  312. }
  313. return 0;
  314. }
  315. void radeon_bo_list_unvalidate(struct list_head *head, void *fence)
  316. {
  317. struct radeon_bo_list *lobj;
  318. struct radeon_fence *old_fence;
  319. if (fence)
  320. list_for_each_entry(lobj, head, list) {
  321. old_fence = to_radeon_fence(lobj->bo->tbo.sync_obj);
  322. if (old_fence == fence) {
  323. lobj->bo->tbo.sync_obj = NULL;
  324. radeon_fence_unref(&old_fence);
  325. }
  326. }
  327. radeon_bo_list_unreserve(head);
  328. }
  329. int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
  330. struct vm_area_struct *vma)
  331. {
  332. return ttm_fbdev_mmap(vma, &bo->tbo);
  333. }
  334. int radeon_bo_get_surface_reg(struct radeon_bo *bo)
  335. {
  336. struct radeon_device *rdev = bo->rdev;
  337. struct radeon_surface_reg *reg;
  338. struct radeon_bo *old_object;
  339. int steal;
  340. int i;
  341. BUG_ON(!atomic_read(&bo->tbo.reserved));
  342. if (!bo->tiling_flags)
  343. return 0;
  344. if (bo->surface_reg >= 0) {
  345. reg = &rdev->surface_regs[bo->surface_reg];
  346. i = bo->surface_reg;
  347. goto out;
  348. }
  349. steal = -1;
  350. for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
  351. reg = &rdev->surface_regs[i];
  352. if (!reg->bo)
  353. break;
  354. old_object = reg->bo;
  355. if (old_object->pin_count == 0)
  356. steal = i;
  357. }
  358. /* if we are all out */
  359. if (i == RADEON_GEM_MAX_SURFACES) {
  360. if (steal == -1)
  361. return -ENOMEM;
  362. /* find someone with a surface reg and nuke their BO */
  363. reg = &rdev->surface_regs[steal];
  364. old_object = reg->bo;
  365. /* blow away the mapping */
  366. DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
  367. ttm_bo_unmap_virtual(&old_object->tbo);
  368. old_object->surface_reg = -1;
  369. i = steal;
  370. }
  371. bo->surface_reg = i;
  372. reg->bo = bo;
  373. out:
  374. radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
  375. bo->tbo.mem.mm_node->start << PAGE_SHIFT,
  376. bo->tbo.num_pages << PAGE_SHIFT);
  377. return 0;
  378. }
  379. static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
  380. {
  381. struct radeon_device *rdev = bo->rdev;
  382. struct radeon_surface_reg *reg;
  383. if (bo->surface_reg == -1)
  384. return;
  385. reg = &rdev->surface_regs[bo->surface_reg];
  386. radeon_clear_surface_reg(rdev, bo->surface_reg);
  387. reg->bo = NULL;
  388. bo->surface_reg = -1;
  389. }
  390. int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
  391. uint32_t tiling_flags, uint32_t pitch)
  392. {
  393. int r;
  394. r = radeon_bo_reserve(bo, false);
  395. if (unlikely(r != 0))
  396. return r;
  397. bo->tiling_flags = tiling_flags;
  398. bo->pitch = pitch;
  399. radeon_bo_unreserve(bo);
  400. return 0;
  401. }
  402. void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
  403. uint32_t *tiling_flags,
  404. uint32_t *pitch)
  405. {
  406. BUG_ON(!atomic_read(&bo->tbo.reserved));
  407. if (tiling_flags)
  408. *tiling_flags = bo->tiling_flags;
  409. if (pitch)
  410. *pitch = bo->pitch;
  411. }
  412. int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
  413. bool force_drop)
  414. {
  415. BUG_ON(!atomic_read(&bo->tbo.reserved));
  416. if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
  417. return 0;
  418. if (force_drop) {
  419. radeon_bo_clear_surface_reg(bo);
  420. return 0;
  421. }
  422. if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
  423. if (!has_moved)
  424. return 0;
  425. if (bo->surface_reg >= 0)
  426. radeon_bo_clear_surface_reg(bo);
  427. return 0;
  428. }
  429. if ((bo->surface_reg >= 0) && !has_moved)
  430. return 0;
  431. return radeon_bo_get_surface_reg(bo);
  432. }
  433. void radeon_bo_move_notify(struct ttm_buffer_object *bo,
  434. struct ttm_mem_reg *mem)
  435. {
  436. struct radeon_bo *rbo;
  437. if (!radeon_ttm_bo_is_radeon_bo(bo))
  438. return;
  439. rbo = container_of(bo, struct radeon_bo, tbo);
  440. radeon_bo_check_tiling(rbo, 0, 1);
  441. }
  442. void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
  443. {
  444. struct radeon_bo *rbo;
  445. if (!radeon_ttm_bo_is_radeon_bo(bo))
  446. return;
  447. rbo = container_of(bo, struct radeon_bo, tbo);
  448. radeon_bo_check_tiling(rbo, 0, 0);
  449. }