radeon_gart.c 6.8 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include "drmP.h"
  29. #include "radeon_drm.h"
  30. #include "radeon.h"
  31. #include "radeon_reg.h"
  32. /*
  33. * Common GART table functions.
  34. */
  35. int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
  36. {
  37. void *ptr;
  38. ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size,
  39. &rdev->gart.table_addr);
  40. if (ptr == NULL) {
  41. return -ENOMEM;
  42. }
  43. #ifdef CONFIG_X86
  44. if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
  45. rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  46. set_memory_uc((unsigned long)ptr,
  47. rdev->gart.table_size >> PAGE_SHIFT);
  48. }
  49. #endif
  50. rdev->gart.table.ram.ptr = ptr;
  51. memset((void *)rdev->gart.table.ram.ptr, 0, rdev->gart.table_size);
  52. return 0;
  53. }
  54. void radeon_gart_table_ram_free(struct radeon_device *rdev)
  55. {
  56. if (rdev->gart.table.ram.ptr == NULL) {
  57. return;
  58. }
  59. #ifdef CONFIG_X86
  60. if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
  61. rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  62. set_memory_wb((unsigned long)rdev->gart.table.ram.ptr,
  63. rdev->gart.table_size >> PAGE_SHIFT);
  64. }
  65. #endif
  66. pci_free_consistent(rdev->pdev, rdev->gart.table_size,
  67. (void *)rdev->gart.table.ram.ptr,
  68. rdev->gart.table_addr);
  69. rdev->gart.table.ram.ptr = NULL;
  70. rdev->gart.table_addr = 0;
  71. }
  72. int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
  73. {
  74. int r;
  75. if (rdev->gart.table.vram.robj == NULL) {
  76. r = radeon_bo_create(rdev, NULL, rdev->gart.table_size,
  77. true, RADEON_GEM_DOMAIN_VRAM,
  78. &rdev->gart.table.vram.robj);
  79. if (r) {
  80. return r;
  81. }
  82. }
  83. return 0;
  84. }
  85. int radeon_gart_table_vram_pin(struct radeon_device *rdev)
  86. {
  87. uint64_t gpu_addr;
  88. int r;
  89. r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
  90. if (unlikely(r != 0))
  91. return r;
  92. r = radeon_bo_pin(rdev->gart.table.vram.robj,
  93. RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
  94. if (r) {
  95. radeon_bo_unreserve(rdev->gart.table.vram.robj);
  96. return r;
  97. }
  98. r = radeon_bo_kmap(rdev->gart.table.vram.robj,
  99. (void **)&rdev->gart.table.vram.ptr);
  100. if (r)
  101. radeon_bo_unpin(rdev->gart.table.vram.robj);
  102. radeon_bo_unreserve(rdev->gart.table.vram.robj);
  103. rdev->gart.table_addr = gpu_addr;
  104. return r;
  105. }
  106. void radeon_gart_table_vram_free(struct radeon_device *rdev)
  107. {
  108. int r;
  109. if (rdev->gart.table.vram.robj == NULL) {
  110. return;
  111. }
  112. r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
  113. if (likely(r == 0)) {
  114. radeon_bo_kunmap(rdev->gart.table.vram.robj);
  115. radeon_bo_unpin(rdev->gart.table.vram.robj);
  116. radeon_bo_unreserve(rdev->gart.table.vram.robj);
  117. }
  118. radeon_bo_unref(&rdev->gart.table.vram.robj);
  119. }
  120. /*
  121. * Common gart functions.
  122. */
  123. void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
  124. int pages)
  125. {
  126. unsigned t;
  127. unsigned p;
  128. int i, j;
  129. if (!rdev->gart.ready) {
  130. WARN(1, "trying to unbind memory to unitialized GART !\n");
  131. return;
  132. }
  133. t = offset / RADEON_GPU_PAGE_SIZE;
  134. p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
  135. for (i = 0; i < pages; i++, p++) {
  136. if (rdev->gart.pages[p]) {
  137. pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p],
  138. PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  139. rdev->gart.pages[p] = NULL;
  140. rdev->gart.pages_addr[p] = 0;
  141. for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
  142. radeon_gart_set_page(rdev, t, 0);
  143. }
  144. }
  145. }
  146. mb();
  147. radeon_gart_tlb_flush(rdev);
  148. }
  149. int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
  150. int pages, struct page **pagelist)
  151. {
  152. unsigned t;
  153. unsigned p;
  154. uint64_t page_base;
  155. int i, j;
  156. if (!rdev->gart.ready) {
  157. DRM_ERROR("trying to bind memory to unitialized GART !\n");
  158. return -EINVAL;
  159. }
  160. t = offset / RADEON_GPU_PAGE_SIZE;
  161. p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
  162. for (i = 0; i < pages; i++, p++) {
  163. /* we need to support large memory configurations */
  164. /* assume that unbind have already been call on the range */
  165. rdev->gart.pages_addr[p] = pci_map_page(rdev->pdev, pagelist[i],
  166. 0, PAGE_SIZE,
  167. PCI_DMA_BIDIRECTIONAL);
  168. if (pci_dma_mapping_error(rdev->pdev, rdev->gart.pages_addr[p])) {
  169. /* FIXME: failed to map page (return -ENOMEM?) */
  170. radeon_gart_unbind(rdev, offset, pages);
  171. return -ENOMEM;
  172. }
  173. rdev->gart.pages[p] = pagelist[i];
  174. page_base = rdev->gart.pages_addr[p];
  175. for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
  176. radeon_gart_set_page(rdev, t, page_base);
  177. page_base += RADEON_GPU_PAGE_SIZE;
  178. }
  179. }
  180. mb();
  181. radeon_gart_tlb_flush(rdev);
  182. return 0;
  183. }
  184. int radeon_gart_init(struct radeon_device *rdev)
  185. {
  186. if (rdev->gart.pages) {
  187. return 0;
  188. }
  189. /* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
  190. if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
  191. DRM_ERROR("Page size is smaller than GPU page size!\n");
  192. return -EINVAL;
  193. }
  194. /* Compute table size */
  195. rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
  196. rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
  197. DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
  198. rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
  199. /* Allocate pages table */
  200. rdev->gart.pages = kzalloc(sizeof(void *) * rdev->gart.num_cpu_pages,
  201. GFP_KERNEL);
  202. if (rdev->gart.pages == NULL) {
  203. radeon_gart_fini(rdev);
  204. return -ENOMEM;
  205. }
  206. rdev->gart.pages_addr = kzalloc(sizeof(dma_addr_t) *
  207. rdev->gart.num_cpu_pages, GFP_KERNEL);
  208. if (rdev->gart.pages_addr == NULL) {
  209. radeon_gart_fini(rdev);
  210. return -ENOMEM;
  211. }
  212. return 0;
  213. }
  214. void radeon_gart_fini(struct radeon_device *rdev)
  215. {
  216. if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) {
  217. /* unbind pages */
  218. radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
  219. }
  220. rdev->gart.ready = false;
  221. kfree(rdev->gart.pages);
  222. kfree(rdev->gart.pages_addr);
  223. rdev->gart.pages = NULL;
  224. rdev->gart.pages_addr = NULL;
  225. }