intel_crt.c 14 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/i2c.h>
  27. #include "drmP.h"
  28. #include "drm.h"
  29. #include "drm_crtc.h"
  30. #include "drm_crtc_helper.h"
  31. #include "intel_drv.h"
  32. #include "i915_drm.h"
  33. #include "i915_drv.h"
  34. static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
  35. {
  36. struct drm_device *dev = encoder->dev;
  37. struct drm_i915_private *dev_priv = dev->dev_private;
  38. u32 temp, reg;
  39. if (IS_IRONLAKE(dev))
  40. reg = PCH_ADPA;
  41. else
  42. reg = ADPA;
  43. temp = I915_READ(reg);
  44. temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  45. temp &= ~ADPA_DAC_ENABLE;
  46. switch(mode) {
  47. case DRM_MODE_DPMS_ON:
  48. temp |= ADPA_DAC_ENABLE;
  49. break;
  50. case DRM_MODE_DPMS_STANDBY:
  51. temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  52. break;
  53. case DRM_MODE_DPMS_SUSPEND:
  54. temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  55. break;
  56. case DRM_MODE_DPMS_OFF:
  57. temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  58. break;
  59. }
  60. I915_WRITE(reg, temp);
  61. }
  62. static int intel_crt_mode_valid(struct drm_connector *connector,
  63. struct drm_display_mode *mode)
  64. {
  65. struct drm_device *dev = connector->dev;
  66. int max_clock = 0;
  67. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  68. return MODE_NO_DBLESCAN;
  69. if (mode->clock < 25000)
  70. return MODE_CLOCK_LOW;
  71. if (!IS_I9XX(dev))
  72. max_clock = 350000;
  73. else
  74. max_clock = 400000;
  75. if (mode->clock > max_clock)
  76. return MODE_CLOCK_HIGH;
  77. return MODE_OK;
  78. }
  79. static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
  80. struct drm_display_mode *mode,
  81. struct drm_display_mode *adjusted_mode)
  82. {
  83. return true;
  84. }
  85. static void intel_crt_mode_set(struct drm_encoder *encoder,
  86. struct drm_display_mode *mode,
  87. struct drm_display_mode *adjusted_mode)
  88. {
  89. struct drm_device *dev = encoder->dev;
  90. struct drm_crtc *crtc = encoder->crtc;
  91. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  92. struct drm_i915_private *dev_priv = dev->dev_private;
  93. int dpll_md_reg;
  94. u32 adpa, dpll_md;
  95. u32 adpa_reg;
  96. if (intel_crtc->pipe == 0)
  97. dpll_md_reg = DPLL_A_MD;
  98. else
  99. dpll_md_reg = DPLL_B_MD;
  100. if (IS_IRONLAKE(dev))
  101. adpa_reg = PCH_ADPA;
  102. else
  103. adpa_reg = ADPA;
  104. /*
  105. * Disable separate mode multiplier used when cloning SDVO to CRT
  106. * XXX this needs to be adjusted when we really are cloning
  107. */
  108. if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
  109. dpll_md = I915_READ(dpll_md_reg);
  110. I915_WRITE(dpll_md_reg,
  111. dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
  112. }
  113. adpa = 0;
  114. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  115. adpa |= ADPA_HSYNC_ACTIVE_HIGH;
  116. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  117. adpa |= ADPA_VSYNC_ACTIVE_HIGH;
  118. if (intel_crtc->pipe == 0) {
  119. adpa |= ADPA_PIPE_A_SELECT;
  120. if (!IS_IRONLAKE(dev))
  121. I915_WRITE(BCLRPAT_A, 0);
  122. } else {
  123. adpa |= ADPA_PIPE_B_SELECT;
  124. if (!IS_IRONLAKE(dev))
  125. I915_WRITE(BCLRPAT_B, 0);
  126. }
  127. I915_WRITE(adpa_reg, adpa);
  128. }
  129. static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
  130. {
  131. struct drm_device *dev = connector->dev;
  132. struct drm_i915_private *dev_priv = dev->dev_private;
  133. u32 adpa;
  134. bool ret;
  135. adpa = I915_READ(PCH_ADPA);
  136. adpa &= ~ADPA_CRT_HOTPLUG_MASK;
  137. adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 |
  138. ADPA_CRT_HOTPLUG_WARMUP_10MS |
  139. ADPA_CRT_HOTPLUG_SAMPLE_4S |
  140. ADPA_CRT_HOTPLUG_VOLTAGE_50 | /* default */
  141. ADPA_CRT_HOTPLUG_VOLREF_325MV |
  142. ADPA_CRT_HOTPLUG_ENABLE |
  143. ADPA_CRT_HOTPLUG_FORCE_TRIGGER);
  144. DRM_DEBUG_KMS("pch crt adpa 0x%x", adpa);
  145. I915_WRITE(PCH_ADPA, adpa);
  146. while ((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) != 0)
  147. ;
  148. /* Check the status to see if both blue and green are on now */
  149. adpa = I915_READ(PCH_ADPA);
  150. adpa &= ADPA_CRT_HOTPLUG_MONITOR_MASK;
  151. if ((adpa == ADPA_CRT_HOTPLUG_MONITOR_COLOR) ||
  152. (adpa == ADPA_CRT_HOTPLUG_MONITOR_MONO))
  153. ret = true;
  154. else
  155. ret = false;
  156. return ret;
  157. }
  158. /**
  159. * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  160. *
  161. * Not for i915G/i915GM
  162. *
  163. * \return true if CRT is connected.
  164. * \return false if CRT is disconnected.
  165. */
  166. static bool intel_crt_detect_hotplug(struct drm_connector *connector)
  167. {
  168. struct drm_device *dev = connector->dev;
  169. struct drm_i915_private *dev_priv = dev->dev_private;
  170. u32 hotplug_en;
  171. int i, tries = 0;
  172. if (IS_IRONLAKE(dev))
  173. return intel_ironlake_crt_detect_hotplug(connector);
  174. /*
  175. * On 4 series desktop, CRT detect sequence need to be done twice
  176. * to get a reliable result.
  177. */
  178. if (IS_G4X(dev) && !IS_GM45(dev))
  179. tries = 2;
  180. else
  181. tries = 1;
  182. hotplug_en = I915_READ(PORT_HOTPLUG_EN);
  183. hotplug_en &= CRT_FORCE_HOTPLUG_MASK;
  184. hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
  185. if (IS_G4X(dev))
  186. hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
  187. hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
  188. for (i = 0; i < tries ; i++) {
  189. unsigned long timeout;
  190. /* turn on the FORCE_DETECT */
  191. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  192. timeout = jiffies + msecs_to_jiffies(1000);
  193. /* wait for FORCE_DETECT to go off */
  194. do {
  195. if (!(I915_READ(PORT_HOTPLUG_EN) &
  196. CRT_HOTPLUG_FORCE_DETECT))
  197. break;
  198. msleep(1);
  199. } while (time_after(timeout, jiffies));
  200. }
  201. if ((I915_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) !=
  202. CRT_HOTPLUG_MONITOR_NONE)
  203. return true;
  204. return false;
  205. }
  206. static bool intel_crt_detect_ddc(struct drm_connector *connector)
  207. {
  208. struct intel_output *intel_output = to_intel_output(connector);
  209. /* CRT should always be at 0, but check anyway */
  210. if (intel_output->type != INTEL_OUTPUT_ANALOG)
  211. return false;
  212. return intel_ddc_probe(intel_output);
  213. }
  214. static enum drm_connector_status
  215. intel_crt_load_detect(struct drm_crtc *crtc, struct intel_output *intel_output)
  216. {
  217. struct drm_encoder *encoder = &intel_output->enc;
  218. struct drm_device *dev = encoder->dev;
  219. struct drm_i915_private *dev_priv = dev->dev_private;
  220. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  221. uint32_t pipe = intel_crtc->pipe;
  222. uint32_t save_bclrpat;
  223. uint32_t save_vtotal;
  224. uint32_t vtotal, vactive;
  225. uint32_t vsample;
  226. uint32_t vblank, vblank_start, vblank_end;
  227. uint32_t dsl;
  228. uint32_t bclrpat_reg;
  229. uint32_t vtotal_reg;
  230. uint32_t vblank_reg;
  231. uint32_t vsync_reg;
  232. uint32_t pipeconf_reg;
  233. uint32_t pipe_dsl_reg;
  234. uint8_t st00;
  235. enum drm_connector_status status;
  236. if (pipe == 0) {
  237. bclrpat_reg = BCLRPAT_A;
  238. vtotal_reg = VTOTAL_A;
  239. vblank_reg = VBLANK_A;
  240. vsync_reg = VSYNC_A;
  241. pipeconf_reg = PIPEACONF;
  242. pipe_dsl_reg = PIPEADSL;
  243. } else {
  244. bclrpat_reg = BCLRPAT_B;
  245. vtotal_reg = VTOTAL_B;
  246. vblank_reg = VBLANK_B;
  247. vsync_reg = VSYNC_B;
  248. pipeconf_reg = PIPEBCONF;
  249. pipe_dsl_reg = PIPEBDSL;
  250. }
  251. save_bclrpat = I915_READ(bclrpat_reg);
  252. save_vtotal = I915_READ(vtotal_reg);
  253. vblank = I915_READ(vblank_reg);
  254. vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
  255. vactive = (save_vtotal & 0x7ff) + 1;
  256. vblank_start = (vblank & 0xfff) + 1;
  257. vblank_end = ((vblank >> 16) & 0xfff) + 1;
  258. /* Set the border color to purple. */
  259. I915_WRITE(bclrpat_reg, 0x500050);
  260. if (IS_I9XX(dev)) {
  261. uint32_t pipeconf = I915_READ(pipeconf_reg);
  262. I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
  263. /* Wait for next Vblank to substitue
  264. * border color for Color info */
  265. intel_wait_for_vblank(dev);
  266. st00 = I915_READ8(VGA_MSR_WRITE);
  267. status = ((st00 & (1 << 4)) != 0) ?
  268. connector_status_connected :
  269. connector_status_disconnected;
  270. I915_WRITE(pipeconf_reg, pipeconf);
  271. } else {
  272. bool restore_vblank = false;
  273. int count, detect;
  274. /*
  275. * If there isn't any border, add some.
  276. * Yes, this will flicker
  277. */
  278. if (vblank_start <= vactive && vblank_end >= vtotal) {
  279. uint32_t vsync = I915_READ(vsync_reg);
  280. uint32_t vsync_start = (vsync & 0xffff) + 1;
  281. vblank_start = vsync_start;
  282. I915_WRITE(vblank_reg,
  283. (vblank_start - 1) |
  284. ((vblank_end - 1) << 16));
  285. restore_vblank = true;
  286. }
  287. /* sample in the vertical border, selecting the larger one */
  288. if (vblank_start - vactive >= vtotal - vblank_end)
  289. vsample = (vblank_start + vactive) >> 1;
  290. else
  291. vsample = (vtotal + vblank_end) >> 1;
  292. /*
  293. * Wait for the border to be displayed
  294. */
  295. while (I915_READ(pipe_dsl_reg) >= vactive)
  296. ;
  297. while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
  298. ;
  299. /*
  300. * Watch ST00 for an entire scanline
  301. */
  302. detect = 0;
  303. count = 0;
  304. do {
  305. count++;
  306. /* Read the ST00 VGA status register */
  307. st00 = I915_READ8(VGA_MSR_WRITE);
  308. if (st00 & (1 << 4))
  309. detect++;
  310. } while ((I915_READ(pipe_dsl_reg) == dsl));
  311. /* restore vblank if necessary */
  312. if (restore_vblank)
  313. I915_WRITE(vblank_reg, vblank);
  314. /*
  315. * If more than 3/4 of the scanline detected a monitor,
  316. * then it is assumed to be present. This works even on i830,
  317. * where there isn't any way to force the border color across
  318. * the screen
  319. */
  320. status = detect * 4 > count * 3 ?
  321. connector_status_connected :
  322. connector_status_disconnected;
  323. }
  324. /* Restore previous settings */
  325. I915_WRITE(bclrpat_reg, save_bclrpat);
  326. return status;
  327. }
  328. static enum drm_connector_status intel_crt_detect(struct drm_connector *connector)
  329. {
  330. struct drm_device *dev = connector->dev;
  331. struct intel_output *intel_output = to_intel_output(connector);
  332. struct drm_encoder *encoder = &intel_output->enc;
  333. struct drm_crtc *crtc;
  334. int dpms_mode;
  335. enum drm_connector_status status;
  336. if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
  337. if (intel_crt_detect_hotplug(connector))
  338. return connector_status_connected;
  339. else
  340. return connector_status_disconnected;
  341. }
  342. if (intel_crt_detect_ddc(connector))
  343. return connector_status_connected;
  344. /* for pre-945g platforms use load detect */
  345. if (encoder->crtc && encoder->crtc->enabled) {
  346. status = intel_crt_load_detect(encoder->crtc, intel_output);
  347. } else {
  348. crtc = intel_get_load_detect_pipe(intel_output,
  349. NULL, &dpms_mode);
  350. if (crtc) {
  351. status = intel_crt_load_detect(crtc, intel_output);
  352. intel_release_load_detect_pipe(intel_output, dpms_mode);
  353. } else
  354. status = connector_status_unknown;
  355. }
  356. return status;
  357. }
  358. static void intel_crt_destroy(struct drm_connector *connector)
  359. {
  360. struct intel_output *intel_output = to_intel_output(connector);
  361. intel_i2c_destroy(intel_output->ddc_bus);
  362. drm_sysfs_connector_remove(connector);
  363. drm_connector_cleanup(connector);
  364. kfree(connector);
  365. }
  366. static int intel_crt_get_modes(struct drm_connector *connector)
  367. {
  368. int ret;
  369. struct intel_output *intel_output = to_intel_output(connector);
  370. struct i2c_adapter *ddcbus;
  371. struct drm_device *dev = connector->dev;
  372. ret = intel_ddc_get_modes(intel_output);
  373. if (ret || !IS_G4X(dev))
  374. goto end;
  375. ddcbus = intel_output->ddc_bus;
  376. /* Try to probe digital port for output in DVI-I -> VGA mode. */
  377. intel_output->ddc_bus =
  378. intel_i2c_create(connector->dev, GPIOD, "CRTDDC_D");
  379. if (!intel_output->ddc_bus) {
  380. intel_output->ddc_bus = ddcbus;
  381. dev_printk(KERN_ERR, &connector->dev->pdev->dev,
  382. "DDC bus registration failed for CRTDDC_D.\n");
  383. goto end;
  384. }
  385. /* Try to get modes by GPIOD port */
  386. ret = intel_ddc_get_modes(intel_output);
  387. intel_i2c_destroy(ddcbus);
  388. end:
  389. return ret;
  390. }
  391. static int intel_crt_set_property(struct drm_connector *connector,
  392. struct drm_property *property,
  393. uint64_t value)
  394. {
  395. return 0;
  396. }
  397. /*
  398. * Routines for controlling stuff on the analog port
  399. */
  400. static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
  401. .dpms = intel_crt_dpms,
  402. .mode_fixup = intel_crt_mode_fixup,
  403. .prepare = intel_encoder_prepare,
  404. .commit = intel_encoder_commit,
  405. .mode_set = intel_crt_mode_set,
  406. };
  407. static const struct drm_connector_funcs intel_crt_connector_funcs = {
  408. .dpms = drm_helper_connector_dpms,
  409. .detect = intel_crt_detect,
  410. .fill_modes = drm_helper_probe_single_connector_modes,
  411. .destroy = intel_crt_destroy,
  412. .set_property = intel_crt_set_property,
  413. };
  414. static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
  415. .mode_valid = intel_crt_mode_valid,
  416. .get_modes = intel_crt_get_modes,
  417. .best_encoder = intel_best_encoder,
  418. };
  419. static void intel_crt_enc_destroy(struct drm_encoder *encoder)
  420. {
  421. drm_encoder_cleanup(encoder);
  422. }
  423. static const struct drm_encoder_funcs intel_crt_enc_funcs = {
  424. .destroy = intel_crt_enc_destroy,
  425. };
  426. void intel_crt_init(struct drm_device *dev)
  427. {
  428. struct drm_connector *connector;
  429. struct intel_output *intel_output;
  430. struct drm_i915_private *dev_priv = dev->dev_private;
  431. u32 i2c_reg;
  432. intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL);
  433. if (!intel_output)
  434. return;
  435. connector = &intel_output->base;
  436. drm_connector_init(dev, &intel_output->base,
  437. &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  438. drm_encoder_init(dev, &intel_output->enc, &intel_crt_enc_funcs,
  439. DRM_MODE_ENCODER_DAC);
  440. drm_mode_connector_attach_encoder(&intel_output->base,
  441. &intel_output->enc);
  442. /* Set up the DDC bus. */
  443. if (IS_IRONLAKE(dev))
  444. i2c_reg = PCH_GPIOA;
  445. else {
  446. i2c_reg = GPIOA;
  447. /* Use VBT information for CRT DDC if available */
  448. if (dev_priv->crt_ddc_bus != 0)
  449. i2c_reg = dev_priv->crt_ddc_bus;
  450. }
  451. intel_output->ddc_bus = intel_i2c_create(dev, i2c_reg, "CRTDDC_A");
  452. if (!intel_output->ddc_bus) {
  453. dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
  454. "failed.\n");
  455. return;
  456. }
  457. intel_output->type = INTEL_OUTPUT_ANALOG;
  458. intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  459. (1 << INTEL_ANALOG_CLONE_BIT) |
  460. (1 << INTEL_SDVO_LVDS_CLONE_BIT);
  461. intel_output->crtc_mask = (1 << 0) | (1 << 1);
  462. connector->interlace_allowed = 0;
  463. connector->doublescan_allowed = 0;
  464. drm_encoder_helper_add(&intel_output->enc, &intel_crt_helper_funcs);
  465. drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
  466. drm_sysfs_connector_add(connector);
  467. dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
  468. }