i915_drv.c 15 KB

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  1. /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
  2. */
  3. /*
  4. *
  5. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the
  10. * "Software"), to deal in the Software without restriction, including
  11. * without limitation the rights to use, copy, modify, merge, publish,
  12. * distribute, sub license, and/or sell copies of the Software, and to
  13. * permit persons to whom the Software is furnished to do so, subject to
  14. * the following conditions:
  15. *
  16. * The above copyright notice and this permission notice (including the
  17. * next paragraph) shall be included in all copies or substantial portions
  18. * of the Software.
  19. *
  20. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27. *
  28. */
  29. #include <linux/device.h>
  30. #include "drmP.h"
  31. #include "drm.h"
  32. #include "i915_drm.h"
  33. #include "i915_drv.h"
  34. #include <linux/console.h>
  35. #include "drm_crtc_helper.h"
  36. static int i915_modeset = -1;
  37. module_param_named(modeset, i915_modeset, int, 0400);
  38. unsigned int i915_fbpercrtc = 0;
  39. module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  40. unsigned int i915_powersave = 1;
  41. module_param_named(powersave, i915_powersave, int, 0400);
  42. static struct drm_driver driver;
  43. #define INTEL_VGA_DEVICE(id, info) { \
  44. .class = PCI_CLASS_DISPLAY_VGA << 8, \
  45. .class_mask = 0xffff00, \
  46. .vendor = 0x8086, \
  47. .device = id, \
  48. .subvendor = PCI_ANY_ID, \
  49. .subdevice = PCI_ANY_ID, \
  50. .driver_data = (unsigned long) info }
  51. const static struct intel_device_info intel_i830_info = {
  52. .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
  53. };
  54. const static struct intel_device_info intel_845g_info = {
  55. .is_i8xx = 1,
  56. };
  57. const static struct intel_device_info intel_i85x_info = {
  58. .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
  59. };
  60. const static struct intel_device_info intel_i865g_info = {
  61. .is_i8xx = 1,
  62. };
  63. const static struct intel_device_info intel_i915g_info = {
  64. .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,
  65. };
  66. const static struct intel_device_info intel_i915gm_info = {
  67. .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
  68. .cursor_needs_physical = 1,
  69. };
  70. const static struct intel_device_info intel_i945g_info = {
  71. .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
  72. };
  73. const static struct intel_device_info intel_i945gm_info = {
  74. .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
  75. .has_hotplug = 1, .cursor_needs_physical = 1,
  76. };
  77. const static struct intel_device_info intel_i965g_info = {
  78. .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
  79. };
  80. const static struct intel_device_info intel_i965gm_info = {
  81. .is_i965g = 1, .is_mobile = 1, .is_i965gm = 1, .is_i9xx = 1,
  82. .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,
  83. .has_hotplug = 1,
  84. };
  85. const static struct intel_device_info intel_g33_info = {
  86. .is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1,
  87. .has_hotplug = 1,
  88. };
  89. const static struct intel_device_info intel_g45_info = {
  90. .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,
  91. .has_pipe_cxsr = 1,
  92. .has_hotplug = 1,
  93. };
  94. const static struct intel_device_info intel_gm45_info = {
  95. .is_i965g = 1, .is_mobile = 1, .is_g4x = 1, .is_i9xx = 1,
  96. .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
  97. .has_pipe_cxsr = 1,
  98. .has_hotplug = 1,
  99. };
  100. const static struct intel_device_info intel_pineview_info = {
  101. .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
  102. .has_pipe_cxsr = 1,
  103. .has_hotplug = 1,
  104. };
  105. const static struct intel_device_info intel_ironlake_d_info = {
  106. .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
  107. .has_pipe_cxsr = 1,
  108. .has_hotplug = 1,
  109. };
  110. const static struct intel_device_info intel_ironlake_m_info = {
  111. .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
  112. .need_gfx_hws = 1, .has_rc6 = 1,
  113. .has_hotplug = 1,
  114. };
  115. const static struct pci_device_id pciidlist[] = {
  116. INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
  117. INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
  118. INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
  119. INTEL_VGA_DEVICE(0x35e8, &intel_i85x_info),
  120. INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
  121. INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
  122. INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
  123. INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),
  124. INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),
  125. INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),
  126. INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),
  127. INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),
  128. INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),
  129. INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),
  130. INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),
  131. INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),
  132. INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),
  133. INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),
  134. INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),
  135. INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),
  136. INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),
  137. INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),
  138. INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),
  139. INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),
  140. INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),
  141. INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),
  142. INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
  143. INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
  144. INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
  145. INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
  146. {0, 0, 0}
  147. };
  148. #if defined(CONFIG_DRM_I915_KMS)
  149. MODULE_DEVICE_TABLE(pci, pciidlist);
  150. #endif
  151. static int i915_suspend(struct drm_device *dev, pm_message_t state)
  152. {
  153. struct drm_i915_private *dev_priv = dev->dev_private;
  154. if (!dev || !dev_priv) {
  155. DRM_ERROR("dev: %p, dev_priv: %p\n", dev, dev_priv);
  156. DRM_ERROR("DRM not initialized, aborting suspend.\n");
  157. return -ENODEV;
  158. }
  159. if (state.event == PM_EVENT_PRETHAW)
  160. return 0;
  161. pci_save_state(dev->pdev);
  162. /* If KMS is active, we do the leavevt stuff here */
  163. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  164. if (i915_gem_idle(dev))
  165. dev_err(&dev->pdev->dev,
  166. "GEM idle failed, resume may fail\n");
  167. drm_irq_uninstall(dev);
  168. }
  169. i915_save_state(dev);
  170. intel_opregion_free(dev, 1);
  171. if (state.event == PM_EVENT_SUSPEND) {
  172. /* Shut down the device */
  173. pci_disable_device(dev->pdev);
  174. pci_set_power_state(dev->pdev, PCI_D3hot);
  175. }
  176. /* Modeset on resume, not lid events */
  177. dev_priv->modeset_on_lid = 0;
  178. return 0;
  179. }
  180. static int i915_resume(struct drm_device *dev)
  181. {
  182. struct drm_i915_private *dev_priv = dev->dev_private;
  183. int ret = 0;
  184. if (pci_enable_device(dev->pdev))
  185. return -1;
  186. pci_set_master(dev->pdev);
  187. i915_restore_state(dev);
  188. intel_opregion_init(dev, 1);
  189. /* KMS EnterVT equivalent */
  190. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  191. mutex_lock(&dev->struct_mutex);
  192. dev_priv->mm.suspended = 0;
  193. ret = i915_gem_init_ringbuffer(dev);
  194. if (ret != 0)
  195. ret = -1;
  196. mutex_unlock(&dev->struct_mutex);
  197. drm_irq_install(dev);
  198. }
  199. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  200. /* Resume the modeset for every activated CRTC */
  201. drm_helper_resume_force_mode(dev);
  202. }
  203. dev_priv->modeset_on_lid = 0;
  204. return ret;
  205. }
  206. /**
  207. * i965_reset - reset chip after a hang
  208. * @dev: drm device to reset
  209. * @flags: reset domains
  210. *
  211. * Reset the chip. Useful if a hang is detected. Returns zero on successful
  212. * reset or otherwise an error code.
  213. *
  214. * Procedure is fairly simple:
  215. * - reset the chip using the reset reg
  216. * - re-init context state
  217. * - re-init hardware status page
  218. * - re-init ring buffer
  219. * - re-init interrupt state
  220. * - re-init display
  221. */
  222. int i965_reset(struct drm_device *dev, u8 flags)
  223. {
  224. drm_i915_private_t *dev_priv = dev->dev_private;
  225. unsigned long timeout;
  226. u8 gdrst;
  227. /*
  228. * We really should only reset the display subsystem if we actually
  229. * need to
  230. */
  231. bool need_display = true;
  232. mutex_lock(&dev->struct_mutex);
  233. /*
  234. * Clear request list
  235. */
  236. i915_gem_retire_requests(dev);
  237. if (need_display)
  238. i915_save_display(dev);
  239. if (IS_I965G(dev) || IS_G4X(dev)) {
  240. /*
  241. * Set the domains we want to reset, then the reset bit (bit 0).
  242. * Clear the reset bit after a while and wait for hardware status
  243. * bit (bit 1) to be set
  244. */
  245. pci_read_config_byte(dev->pdev, GDRST, &gdrst);
  246. pci_write_config_byte(dev->pdev, GDRST, gdrst | flags | ((flags == GDRST_FULL) ? 0x1 : 0x0));
  247. udelay(50);
  248. pci_write_config_byte(dev->pdev, GDRST, gdrst & 0xfe);
  249. /* ...we don't want to loop forever though, 500ms should be plenty */
  250. timeout = jiffies + msecs_to_jiffies(500);
  251. do {
  252. udelay(100);
  253. pci_read_config_byte(dev->pdev, GDRST, &gdrst);
  254. } while ((gdrst & 0x1) && time_after(timeout, jiffies));
  255. if (gdrst & 0x1) {
  256. WARN(true, "i915: Failed to reset chip\n");
  257. mutex_unlock(&dev->struct_mutex);
  258. return -EIO;
  259. }
  260. } else {
  261. DRM_ERROR("Error occurred. Don't know how to reset this chip.\n");
  262. return -ENODEV;
  263. }
  264. /* Ok, now get things going again... */
  265. /*
  266. * Everything depends on having the GTT running, so we need to start
  267. * there. Fortunately we don't need to do this unless we reset the
  268. * chip at a PCI level.
  269. *
  270. * Next we need to restore the context, but we don't use those
  271. * yet either...
  272. *
  273. * Ring buffer needs to be re-initialized in the KMS case, or if X
  274. * was running at the time of the reset (i.e. we weren't VT
  275. * switched away).
  276. */
  277. if (drm_core_check_feature(dev, DRIVER_MODESET) ||
  278. !dev_priv->mm.suspended) {
  279. drm_i915_ring_buffer_t *ring = &dev_priv->ring;
  280. struct drm_gem_object *obj = ring->ring_obj;
  281. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  282. dev_priv->mm.suspended = 0;
  283. /* Stop the ring if it's running. */
  284. I915_WRITE(PRB0_CTL, 0);
  285. I915_WRITE(PRB0_TAIL, 0);
  286. I915_WRITE(PRB0_HEAD, 0);
  287. /* Initialize the ring. */
  288. I915_WRITE(PRB0_START, obj_priv->gtt_offset);
  289. I915_WRITE(PRB0_CTL,
  290. ((obj->size - 4096) & RING_NR_PAGES) |
  291. RING_NO_REPORT |
  292. RING_VALID);
  293. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  294. i915_kernel_lost_context(dev);
  295. else {
  296. ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  297. ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
  298. ring->space = ring->head - (ring->tail + 8);
  299. if (ring->space < 0)
  300. ring->space += ring->Size;
  301. }
  302. mutex_unlock(&dev->struct_mutex);
  303. drm_irq_uninstall(dev);
  304. drm_irq_install(dev);
  305. mutex_lock(&dev->struct_mutex);
  306. }
  307. /*
  308. * Display needs restore too...
  309. */
  310. if (need_display)
  311. i915_restore_display(dev);
  312. mutex_unlock(&dev->struct_mutex);
  313. return 0;
  314. }
  315. static int __devinit
  316. i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  317. {
  318. return drm_get_dev(pdev, ent, &driver);
  319. }
  320. static void
  321. i915_pci_remove(struct pci_dev *pdev)
  322. {
  323. struct drm_device *dev = pci_get_drvdata(pdev);
  324. drm_put_dev(dev);
  325. }
  326. static int
  327. i915_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  328. {
  329. struct drm_device *dev = pci_get_drvdata(pdev);
  330. return i915_suspend(dev, state);
  331. }
  332. static int
  333. i915_pci_resume(struct pci_dev *pdev)
  334. {
  335. struct drm_device *dev = pci_get_drvdata(pdev);
  336. return i915_resume(dev);
  337. }
  338. static int
  339. i915_pm_suspend(struct device *dev)
  340. {
  341. return i915_pci_suspend(to_pci_dev(dev), PMSG_SUSPEND);
  342. }
  343. static int
  344. i915_pm_resume(struct device *dev)
  345. {
  346. return i915_pci_resume(to_pci_dev(dev));
  347. }
  348. static int
  349. i915_pm_freeze(struct device *dev)
  350. {
  351. return i915_pci_suspend(to_pci_dev(dev), PMSG_FREEZE);
  352. }
  353. static int
  354. i915_pm_thaw(struct device *dev)
  355. {
  356. /* thaw during hibernate, do nothing! */
  357. return 0;
  358. }
  359. static int
  360. i915_pm_poweroff(struct device *dev)
  361. {
  362. return i915_pci_suspend(to_pci_dev(dev), PMSG_HIBERNATE);
  363. }
  364. static int
  365. i915_pm_restore(struct device *dev)
  366. {
  367. return i915_pci_resume(to_pci_dev(dev));
  368. }
  369. const struct dev_pm_ops i915_pm_ops = {
  370. .suspend = i915_pm_suspend,
  371. .resume = i915_pm_resume,
  372. .freeze = i915_pm_freeze,
  373. .thaw = i915_pm_thaw,
  374. .poweroff = i915_pm_poweroff,
  375. .restore = i915_pm_restore,
  376. };
  377. static struct vm_operations_struct i915_gem_vm_ops = {
  378. .fault = i915_gem_fault,
  379. .open = drm_gem_vm_open,
  380. .close = drm_gem_vm_close,
  381. };
  382. static struct drm_driver driver = {
  383. /* don't use mtrr's here, the Xserver or user space app should
  384. * deal with them for intel hardware.
  385. */
  386. .driver_features =
  387. DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
  388. DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
  389. .load = i915_driver_load,
  390. .unload = i915_driver_unload,
  391. .open = i915_driver_open,
  392. .lastclose = i915_driver_lastclose,
  393. .preclose = i915_driver_preclose,
  394. .postclose = i915_driver_postclose,
  395. .suspend = i915_suspend,
  396. .resume = i915_resume,
  397. .device_is_agp = i915_driver_device_is_agp,
  398. .enable_vblank = i915_enable_vblank,
  399. .disable_vblank = i915_disable_vblank,
  400. .irq_preinstall = i915_driver_irq_preinstall,
  401. .irq_postinstall = i915_driver_irq_postinstall,
  402. .irq_uninstall = i915_driver_irq_uninstall,
  403. .irq_handler = i915_driver_irq_handler,
  404. .reclaim_buffers = drm_core_reclaim_buffers,
  405. .get_map_ofs = drm_core_get_map_ofs,
  406. .get_reg_ofs = drm_core_get_reg_ofs,
  407. .master_create = i915_master_create,
  408. .master_destroy = i915_master_destroy,
  409. #if defined(CONFIG_DEBUG_FS)
  410. .debugfs_init = i915_debugfs_init,
  411. .debugfs_cleanup = i915_debugfs_cleanup,
  412. #endif
  413. .gem_init_object = i915_gem_init_object,
  414. .gem_free_object = i915_gem_free_object,
  415. .gem_vm_ops = &i915_gem_vm_ops,
  416. .ioctls = i915_ioctls,
  417. .fops = {
  418. .owner = THIS_MODULE,
  419. .open = drm_open,
  420. .release = drm_release,
  421. .unlocked_ioctl = drm_ioctl,
  422. .mmap = drm_gem_mmap,
  423. .poll = drm_poll,
  424. .fasync = drm_fasync,
  425. .read = drm_read,
  426. #ifdef CONFIG_COMPAT
  427. .compat_ioctl = i915_compat_ioctl,
  428. #endif
  429. },
  430. .pci_driver = {
  431. .name = DRIVER_NAME,
  432. .id_table = pciidlist,
  433. .probe = i915_pci_probe,
  434. .remove = i915_pci_remove,
  435. .driver.pm = &i915_pm_ops,
  436. },
  437. .name = DRIVER_NAME,
  438. .desc = DRIVER_DESC,
  439. .date = DRIVER_DATE,
  440. .major = DRIVER_MAJOR,
  441. .minor = DRIVER_MINOR,
  442. .patchlevel = DRIVER_PATCHLEVEL,
  443. };
  444. static int __init i915_init(void)
  445. {
  446. driver.num_ioctls = i915_max_ioctl;
  447. i915_gem_shrinker_init();
  448. /*
  449. * If CONFIG_DRM_I915_KMS is set, default to KMS unless
  450. * explicitly disabled with the module pararmeter.
  451. *
  452. * Otherwise, just follow the parameter (defaulting to off).
  453. *
  454. * Allow optional vga_text_mode_force boot option to override
  455. * the default behavior.
  456. */
  457. #if defined(CONFIG_DRM_I915_KMS)
  458. if (i915_modeset != 0)
  459. driver.driver_features |= DRIVER_MODESET;
  460. #endif
  461. if (i915_modeset == 1)
  462. driver.driver_features |= DRIVER_MODESET;
  463. #ifdef CONFIG_VGA_CONSOLE
  464. if (vgacon_text_force() && i915_modeset == -1)
  465. driver.driver_features &= ~DRIVER_MODESET;
  466. #endif
  467. return drm_init(&driver);
  468. }
  469. static void __exit i915_exit(void)
  470. {
  471. i915_gem_shrinker_exit();
  472. drm_exit(&driver);
  473. }
  474. module_init(i915_init);
  475. module_exit(i915_exit);
  476. MODULE_AUTHOR(DRIVER_AUTHOR);
  477. MODULE_DESCRIPTION(DRIVER_DESC);
  478. MODULE_LICENSE("GPL and additional rights");