timbgpio.c 8.0 KB

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  1. /*
  2. * timbgpio.c timberdale FPGA GPIO driver
  3. * Copyright (c) 2009 Intel Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. */
  18. /* Supports:
  19. * Timberdale FPGA GPIO
  20. */
  21. #include <linux/module.h>
  22. #include <linux/gpio.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/io.h>
  25. #include <linux/timb_gpio.h>
  26. #include <linux/interrupt.h>
  27. #define DRIVER_NAME "timb-gpio"
  28. #define TGPIOVAL 0x00
  29. #define TGPIODIR 0x04
  30. #define TGPIO_IER 0x08
  31. #define TGPIO_ISR 0x0c
  32. #define TGPIO_IPR 0x10
  33. #define TGPIO_ICR 0x14
  34. #define TGPIO_FLR 0x18
  35. #define TGPIO_LVR 0x1c
  36. struct timbgpio {
  37. void __iomem *membase;
  38. spinlock_t lock; /* mutual exclusion */
  39. struct gpio_chip gpio;
  40. int irq_base;
  41. };
  42. static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
  43. unsigned offset, bool enabled)
  44. {
  45. struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
  46. u32 reg;
  47. spin_lock(&tgpio->lock);
  48. reg = ioread32(tgpio->membase + offset);
  49. if (enabled)
  50. reg |= (1 << index);
  51. else
  52. reg &= ~(1 << index);
  53. iowrite32(reg, tgpio->membase + offset);
  54. spin_unlock(&tgpio->lock);
  55. return 0;
  56. }
  57. static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
  58. {
  59. return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
  60. }
  61. static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
  62. {
  63. struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
  64. u32 value;
  65. value = ioread32(tgpio->membase + TGPIOVAL);
  66. return (value & (1 << nr)) ? 1 : 0;
  67. }
  68. static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
  69. unsigned nr, int val)
  70. {
  71. return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
  72. }
  73. static void timbgpio_gpio_set(struct gpio_chip *gpio,
  74. unsigned nr, int val)
  75. {
  76. timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
  77. }
  78. static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
  79. {
  80. struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
  81. if (tgpio->irq_base <= 0)
  82. return -EINVAL;
  83. return tgpio->irq_base + offset;
  84. }
  85. /*
  86. * GPIO IRQ
  87. */
  88. static void timbgpio_irq_disable(unsigned irq)
  89. {
  90. struct timbgpio *tgpio = get_irq_chip_data(irq);
  91. int offset = irq - tgpio->irq_base;
  92. timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 0);
  93. }
  94. static void timbgpio_irq_enable(unsigned irq)
  95. {
  96. struct timbgpio *tgpio = get_irq_chip_data(irq);
  97. int offset = irq - tgpio->irq_base;
  98. timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 1);
  99. }
  100. static int timbgpio_irq_type(unsigned irq, unsigned trigger)
  101. {
  102. struct timbgpio *tgpio = get_irq_chip_data(irq);
  103. int offset = irq - tgpio->irq_base;
  104. unsigned long flags;
  105. u32 lvr, flr;
  106. if (offset < 0 || offset > tgpio->gpio.ngpio)
  107. return -EINVAL;
  108. spin_lock_irqsave(&tgpio->lock, flags);
  109. lvr = ioread32(tgpio->membase + TGPIO_LVR);
  110. flr = ioread32(tgpio->membase + TGPIO_FLR);
  111. if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
  112. flr &= ~(1 << offset);
  113. if (trigger & IRQ_TYPE_LEVEL_HIGH)
  114. lvr |= 1 << offset;
  115. else
  116. lvr &= ~(1 << offset);
  117. }
  118. if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
  119. return -EINVAL;
  120. else {
  121. flr |= 1 << offset;
  122. /* opposite compared to the datasheet, but it mirrors the
  123. * reality
  124. */
  125. if (trigger & IRQ_TYPE_EDGE_FALLING)
  126. lvr |= 1 << offset;
  127. else
  128. lvr &= ~(1 << offset);
  129. }
  130. iowrite32(lvr, tgpio->membase + TGPIO_LVR);
  131. iowrite32(flr, tgpio->membase + TGPIO_FLR);
  132. iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
  133. spin_unlock_irqrestore(&tgpio->lock, flags);
  134. return 0;
  135. }
  136. static void timbgpio_irq(unsigned int irq, struct irq_desc *desc)
  137. {
  138. struct timbgpio *tgpio = get_irq_data(irq);
  139. unsigned long ipr;
  140. int offset;
  141. desc->chip->ack(irq);
  142. ipr = ioread32(tgpio->membase + TGPIO_IPR);
  143. iowrite32(ipr, tgpio->membase + TGPIO_ICR);
  144. for_each_bit(offset, &ipr, tgpio->gpio.ngpio)
  145. generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
  146. }
  147. static struct irq_chip timbgpio_irqchip = {
  148. .name = "GPIO",
  149. .enable = timbgpio_irq_enable,
  150. .disable = timbgpio_irq_disable,
  151. .set_type = timbgpio_irq_type,
  152. };
  153. static int __devinit timbgpio_probe(struct platform_device *pdev)
  154. {
  155. int err, i;
  156. struct gpio_chip *gc;
  157. struct timbgpio *tgpio;
  158. struct resource *iomem;
  159. struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
  160. int irq = platform_get_irq(pdev, 0);
  161. if (!pdata || pdata->nr_pins > 32) {
  162. err = -EINVAL;
  163. goto err_mem;
  164. }
  165. iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  166. if (!iomem) {
  167. err = -EINVAL;
  168. goto err_mem;
  169. }
  170. tgpio = kzalloc(sizeof(*tgpio), GFP_KERNEL);
  171. if (!tgpio) {
  172. err = -EINVAL;
  173. goto err_mem;
  174. }
  175. tgpio->irq_base = pdata->irq_base;
  176. spin_lock_init(&tgpio->lock);
  177. if (!request_mem_region(iomem->start, resource_size(iomem),
  178. DRIVER_NAME)) {
  179. err = -EBUSY;
  180. goto err_request;
  181. }
  182. tgpio->membase = ioremap(iomem->start, resource_size(iomem));
  183. if (!tgpio->membase) {
  184. err = -ENOMEM;
  185. goto err_ioremap;
  186. }
  187. gc = &tgpio->gpio;
  188. gc->label = dev_name(&pdev->dev);
  189. gc->owner = THIS_MODULE;
  190. gc->dev = &pdev->dev;
  191. gc->direction_input = timbgpio_gpio_direction_input;
  192. gc->get = timbgpio_gpio_get;
  193. gc->direction_output = timbgpio_gpio_direction_output;
  194. gc->set = timbgpio_gpio_set;
  195. gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
  196. gc->dbg_show = NULL;
  197. gc->base = pdata->gpio_base;
  198. gc->ngpio = pdata->nr_pins;
  199. gc->can_sleep = 0;
  200. err = gpiochip_add(gc);
  201. if (err)
  202. goto err_chipadd;
  203. platform_set_drvdata(pdev, tgpio);
  204. /* make sure to disable interrupts */
  205. iowrite32(0x0, tgpio->membase + TGPIO_IER);
  206. if (irq < 0 || tgpio->irq_base <= 0)
  207. return 0;
  208. for (i = 0; i < pdata->nr_pins; i++) {
  209. set_irq_chip_and_handler_name(tgpio->irq_base + i,
  210. &timbgpio_irqchip, handle_simple_irq, "mux");
  211. set_irq_chip_data(tgpio->irq_base + i, tgpio);
  212. #ifdef CONFIG_ARM
  213. set_irq_flags(tgpio->irq_base + i, IRQF_VALID | IRQF_PROBE);
  214. #endif
  215. }
  216. set_irq_data(irq, tgpio);
  217. set_irq_chained_handler(irq, timbgpio_irq);
  218. return 0;
  219. err_chipadd:
  220. iounmap(tgpio->membase);
  221. err_ioremap:
  222. release_mem_region(iomem->start, resource_size(iomem));
  223. err_request:
  224. kfree(tgpio);
  225. err_mem:
  226. printk(KERN_ERR DRIVER_NAME": Failed to register GPIOs: %d\n", err);
  227. return err;
  228. }
  229. static int __devexit timbgpio_remove(struct platform_device *pdev)
  230. {
  231. int err;
  232. struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
  233. struct timbgpio *tgpio = platform_get_drvdata(pdev);
  234. struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  235. int irq = platform_get_irq(pdev, 0);
  236. if (irq >= 0 && tgpio->irq_base > 0) {
  237. int i;
  238. for (i = 0; i < pdata->nr_pins; i++) {
  239. set_irq_chip(tgpio->irq_base + i, NULL);
  240. set_irq_chip_data(tgpio->irq_base + i, NULL);
  241. }
  242. set_irq_handler(irq, NULL);
  243. set_irq_data(irq, NULL);
  244. }
  245. err = gpiochip_remove(&tgpio->gpio);
  246. if (err)
  247. printk(KERN_ERR DRIVER_NAME": failed to remove gpio_chip\n");
  248. iounmap(tgpio->membase);
  249. release_mem_region(iomem->start, resource_size(iomem));
  250. kfree(tgpio);
  251. platform_set_drvdata(pdev, NULL);
  252. return 0;
  253. }
  254. static struct platform_driver timbgpio_platform_driver = {
  255. .driver = {
  256. .name = DRIVER_NAME,
  257. .owner = THIS_MODULE,
  258. },
  259. .probe = timbgpio_probe,
  260. .remove = timbgpio_remove,
  261. };
  262. /*--------------------------------------------------------------------------*/
  263. static int __init timbgpio_init(void)
  264. {
  265. return platform_driver_register(&timbgpio_platform_driver);
  266. }
  267. static void __exit timbgpio_exit(void)
  268. {
  269. platform_driver_unregister(&timbgpio_platform_driver);
  270. }
  271. module_init(timbgpio_init);
  272. module_exit(timbgpio_exit);
  273. MODULE_DESCRIPTION("Timberdale GPIO driver");
  274. MODULE_LICENSE("GPL v2");
  275. MODULE_AUTHOR("Mocean Laboratories");
  276. MODULE_ALIAS("platform:"DRIVER_NAME);