Kconfig 8.0 KB

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  1. #
  2. # EDAC Kconfig
  3. # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
  4. # Licensed and distributed under the GPL
  5. #
  6. menuconfig EDAC
  7. bool "EDAC (Error Detection And Correction) reporting"
  8. depends on HAS_IOMEM
  9. depends on X86 || PPC
  10. help
  11. EDAC is designed to report errors in the core system.
  12. These are low-level errors that are reported in the CPU or
  13. supporting chipset or other subsystems:
  14. memory errors, cache errors, PCI errors, thermal throttling, etc..
  15. If unsure, select 'Y'.
  16. If this code is reporting problems on your system, please
  17. see the EDAC project web pages for more information at:
  18. <http://bluesmoke.sourceforge.net/>
  19. and:
  20. <http://buttersideup.com/edacwiki>
  21. There is also a mailing list for the EDAC project, which can
  22. be found via the sourceforge page.
  23. if EDAC
  24. comment "Reporting subsystems"
  25. config EDAC_DEBUG
  26. bool "Debugging"
  27. help
  28. This turns on debugging information for the entire EDAC
  29. sub-system. You can insert module with "debug_level=x", current
  30. there're four debug levels (x=0,1,2,3 from low to high).
  31. Usually you should select 'N'.
  32. config EDAC_DEBUG_VERBOSE
  33. bool "More verbose debugging"
  34. depends on EDAC_DEBUG
  35. help
  36. This option makes debugging information more verbose.
  37. Source file name and line number where debugging message
  38. printed will be added to debugging message.
  39. config EDAC_DECODE_MCE
  40. tristate "Decode MCEs in human-readable form (only on AMD for now)"
  41. depends on CPU_SUP_AMD && X86_MCE
  42. default y
  43. ---help---
  44. Enable this option if you want to decode Machine Check Exceptions
  45. occuring on your machine in human-readable form.
  46. You should definitely say Y here in case you want to decode MCEs
  47. which occur really early upon boot, before the module infrastructure
  48. has been initialized.
  49. config EDAC_MM_EDAC
  50. tristate "Main Memory EDAC (Error Detection And Correction) reporting"
  51. help
  52. Some systems are able to detect and correct errors in main
  53. memory. EDAC can report statistics on memory error
  54. detection and correction (EDAC - or commonly referred to ECC
  55. errors). EDAC will also try to decode where these errors
  56. occurred so that a particular failing memory module can be
  57. replaced. If unsure, select 'Y'.
  58. config EDAC_AMD64
  59. tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h"
  60. depends on EDAC_MM_EDAC && K8_NB && X86_64 && PCI && EDAC_DECODE_MCE
  61. help
  62. Support for error detection and correction on the AMD 64
  63. Families of Memory Controllers (K8, F10h and F11h)
  64. config EDAC_AMD64_ERROR_INJECTION
  65. bool "Sysfs Error Injection facilities"
  66. depends on EDAC_AMD64
  67. help
  68. Recent Opterons (Family 10h and later) provide for Memory Error
  69. Injection into the ECC detection circuits. The amd64_edac module
  70. allows the operator/user to inject Uncorrectable and Correctable
  71. errors into DRAM.
  72. When enabled, in each of the respective memory controller directories
  73. (/sys/devices/system/edac/mc/mcX), there are 3 input files:
  74. - inject_section (0..3, 16-byte section of 64-byte cacheline),
  75. - inject_word (0..8, 16-bit word of 16-byte section),
  76. - inject_ecc_vector (hex ecc vector: select bits of inject word)
  77. In addition, there are two control files, inject_read and inject_write,
  78. which trigger the DRAM ECC Read and Write respectively.
  79. config EDAC_AMD76X
  80. tristate "AMD 76x (760, 762, 768)"
  81. depends on EDAC_MM_EDAC && PCI && X86_32
  82. help
  83. Support for error detection and correction on the AMD 76x
  84. series of chipsets used with the Athlon processor.
  85. config EDAC_E7XXX
  86. tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
  87. depends on EDAC_MM_EDAC && PCI && X86_32
  88. help
  89. Support for error detection and correction on the Intel
  90. E7205, E7500, E7501 and E7505 server chipsets.
  91. config EDAC_E752X
  92. tristate "Intel e752x (e7520, e7525, e7320) and 3100"
  93. depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
  94. help
  95. Support for error detection and correction on the Intel
  96. E7520, E7525, E7320 server chipsets.
  97. config EDAC_I82443BXGX
  98. tristate "Intel 82443BX/GX (440BX/GX)"
  99. depends on EDAC_MM_EDAC && PCI && X86_32
  100. depends on BROKEN
  101. help
  102. Support for error detection and correction on the Intel
  103. 82443BX/GX memory controllers (440BX/GX chipsets).
  104. config EDAC_I82875P
  105. tristate "Intel 82875p (D82875P, E7210)"
  106. depends on EDAC_MM_EDAC && PCI && X86_32
  107. help
  108. Support for error detection and correction on the Intel
  109. DP82785P and E7210 server chipsets.
  110. config EDAC_I82975X
  111. tristate "Intel 82975x (D82975x)"
  112. depends on EDAC_MM_EDAC && PCI && X86
  113. help
  114. Support for error detection and correction on the Intel
  115. DP82975x server chipsets.
  116. config EDAC_I3000
  117. tristate "Intel 3000/3010"
  118. depends on EDAC_MM_EDAC && PCI && X86
  119. help
  120. Support for error detection and correction on the Intel
  121. 3000 and 3010 server chipsets.
  122. config EDAC_I3200
  123. tristate "Intel 3200"
  124. depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
  125. help
  126. Support for error detection and correction on the Intel
  127. 3200 and 3210 server chipsets.
  128. config EDAC_X38
  129. tristate "Intel X38"
  130. depends on EDAC_MM_EDAC && PCI && X86
  131. help
  132. Support for error detection and correction on the Intel
  133. X38 server chipsets.
  134. config EDAC_I5400
  135. tristate "Intel 5400 (Seaburg) chipsets"
  136. depends on EDAC_MM_EDAC && PCI && X86
  137. help
  138. Support for error detection and correction the Intel
  139. i5400 MCH chipset (Seaburg).
  140. config EDAC_I82860
  141. tristate "Intel 82860"
  142. depends on EDAC_MM_EDAC && PCI && X86_32
  143. help
  144. Support for error detection and correction on the Intel
  145. 82860 chipset.
  146. config EDAC_R82600
  147. tristate "Radisys 82600 embedded chipset"
  148. depends on EDAC_MM_EDAC && PCI && X86_32
  149. help
  150. Support for error detection and correction on the Radisys
  151. 82600 embedded chipset.
  152. config EDAC_I5000
  153. tristate "Intel Greencreek/Blackford chipset"
  154. depends on EDAC_MM_EDAC && X86 && PCI
  155. help
  156. Support for error detection and correction the Intel
  157. Greekcreek/Blackford chipsets.
  158. config EDAC_I5100
  159. tristate "Intel San Clemente MCH"
  160. depends on EDAC_MM_EDAC && X86 && PCI
  161. help
  162. Support for error detection and correction the Intel
  163. San Clemente MCH.
  164. config EDAC_MPC85XX
  165. tristate "Freescale MPC83xx / MPC85xx"
  166. depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || MPC85xx)
  167. help
  168. Support for error detection and correction on the Freescale
  169. MPC8349, MPC8560, MPC8540, MPC8548
  170. config EDAC_MV64X60
  171. tristate "Marvell MV64x60"
  172. depends on EDAC_MM_EDAC && MV64X60
  173. help
  174. Support for error detection and correction on the Marvell
  175. MV64360 and MV64460 chipsets.
  176. config EDAC_PASEMI
  177. tristate "PA Semi PWRficient"
  178. depends on EDAC_MM_EDAC && PCI
  179. depends on PPC_PASEMI
  180. help
  181. Support for error detection and correction on PA Semi
  182. PWRficient.
  183. config EDAC_CELL
  184. tristate "Cell Broadband Engine memory controller"
  185. depends on EDAC_MM_EDAC && PPC_CELL_COMMON
  186. help
  187. Support for error detection and correction on the
  188. Cell Broadband Engine internal memory controller
  189. on platform without a hypervisor
  190. config EDAC_PPC4XX
  191. tristate "PPC4xx IBM DDR2 Memory Controller"
  192. depends on EDAC_MM_EDAC && 4xx
  193. help
  194. This enables support for EDAC on the ECC memory used
  195. with the IBM DDR2 memory controller found in various
  196. PowerPC 4xx embedded processors such as the 405EX[r],
  197. 440SP, 440SPe, 460EX, 460GT and 460SX.
  198. config EDAC_AMD8131
  199. tristate "AMD8131 HyperTransport PCI-X Tunnel"
  200. depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
  201. help
  202. Support for error detection and correction on the
  203. AMD8131 HyperTransport PCI-X Tunnel chip.
  204. Note, add more Kconfig dependency if it's adopted
  205. on some machine other than Maple.
  206. config EDAC_AMD8111
  207. tristate "AMD8111 HyperTransport I/O Hub"
  208. depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
  209. help
  210. Support for error detection and correction on the
  211. AMD8111 HyperTransport I/O Hub chip.
  212. Note, add more Kconfig dependency if it's adopted
  213. on some machine other than Maple.
  214. config EDAC_CPC925
  215. tristate "IBM CPC925 Memory Controller (PPC970FX)"
  216. depends on EDAC_MM_EDAC && PPC64
  217. help
  218. Support for error detection and correction on the
  219. IBM CPC925 Bridge and Memory Controller, which is
  220. a companion chip to the PowerPC 970 family of
  221. processors.
  222. endif # EDAC