Kconfig 4.3 KB

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  1. #
  2. # DMA engine configuration
  3. #
  4. menuconfig DMADEVICES
  5. bool "DMA Engine support"
  6. depends on HAS_DMA
  7. help
  8. DMA engines can do asynchronous data transfers without
  9. involving the host CPU. Currently, this framework can be
  10. used to offload memory copies in the network stack and
  11. RAID operations in the MD driver. This menu only presents
  12. DMA Device drivers supported by the configured arch, it may
  13. be empty in some cases.
  14. if DMADEVICES
  15. comment "DMA Devices"
  16. config ASYNC_TX_DISABLE_CHANNEL_SWITCH
  17. bool
  18. config INTEL_IOATDMA
  19. tristate "Intel I/OAT DMA support"
  20. depends on PCI && X86
  21. select DMA_ENGINE
  22. select DCA
  23. select ASYNC_TX_DISABLE_CHANNEL_SWITCH
  24. select ASYNC_TX_DISABLE_PQ_VAL_DMA
  25. select ASYNC_TX_DISABLE_XOR_VAL_DMA
  26. help
  27. Enable support for the Intel(R) I/OAT DMA engine present
  28. in recent Intel Xeon chipsets.
  29. Say Y here if you have such a chipset.
  30. If unsure, say N.
  31. config INTEL_IOP_ADMA
  32. tristate "Intel IOP ADMA support"
  33. depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
  34. select DMA_ENGINE
  35. help
  36. Enable support for the Intel(R) IOP Series RAID engines.
  37. config DW_DMAC
  38. tristate "Synopsys DesignWare AHB DMA support"
  39. depends on AVR32
  40. select DMA_ENGINE
  41. default y if CPU_AT32AP7000
  42. help
  43. Support the Synopsys DesignWare AHB DMA controller. This
  44. can be integrated in chips such as the Atmel AT32ap7000.
  45. config AT_HDMAC
  46. tristate "Atmel AHB DMA support"
  47. depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
  48. select DMA_ENGINE
  49. help
  50. Support the Atmel AHB DMA controller. This can be integrated in
  51. chips such as the Atmel AT91SAM9RL.
  52. config FSL_DMA
  53. tristate "Freescale Elo and Elo Plus DMA support"
  54. depends on FSL_SOC
  55. select DMA_ENGINE
  56. ---help---
  57. Enable support for the Freescale Elo and Elo Plus DMA controllers.
  58. The Elo is the DMA controller on some 82xx and 83xx parts, and the
  59. Elo Plus is the DMA controller on 85xx and 86xx parts.
  60. config MV_XOR
  61. bool "Marvell XOR engine support"
  62. depends on PLAT_ORION
  63. select DMA_ENGINE
  64. ---help---
  65. Enable support for the Marvell XOR engine.
  66. config MX3_IPU
  67. bool "MX3x Image Processing Unit support"
  68. depends on ARCH_MX3
  69. select DMA_ENGINE
  70. default y
  71. help
  72. If you plan to use the Image Processing unit in the i.MX3x, say
  73. Y here. If unsure, select Y.
  74. config MX3_IPU_IRQS
  75. int "Number of dynamically mapped interrupts for IPU"
  76. depends on MX3_IPU
  77. range 2 137
  78. default 4
  79. help
  80. Out of 137 interrupt sources on i.MX31 IPU only very few are used.
  81. To avoid bloating the irq_desc[] array we allocate a sufficient
  82. number of IRQ slots and map them dynamically to specific sources.
  83. config TXX9_DMAC
  84. tristate "Toshiba TXx9 SoC DMA support"
  85. depends on MACH_TX49XX || MACH_TX39XX
  86. select DMA_ENGINE
  87. help
  88. Support the TXx9 SoC internal DMA controller. This can be
  89. integrated in chips such as the Toshiba TX4927/38/39.
  90. config SH_DMAE
  91. tristate "Renesas SuperH DMAC support"
  92. depends on SUPERH && SH_DMA
  93. depends on !SH_DMA_API
  94. select DMA_ENGINE
  95. help
  96. Enable support for the Renesas SuperH DMA controllers.
  97. config COH901318
  98. bool "ST-Ericsson COH901318 DMA support"
  99. select DMA_ENGINE
  100. depends on ARCH_U300
  101. help
  102. Enable support for ST-Ericsson COH 901 318 DMA.
  103. config AMCC_PPC440SPE_ADMA
  104. tristate "AMCC PPC440SPe ADMA support"
  105. depends on 440SPe || 440SP
  106. select DMA_ENGINE
  107. select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
  108. help
  109. Enable support for the AMCC PPC440SPe RAID engines.
  110. config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
  111. bool
  112. config DMA_ENGINE
  113. bool
  114. comment "DMA Clients"
  115. depends on DMA_ENGINE
  116. config NET_DMA
  117. bool "Network: TCP receive copy offload"
  118. depends on DMA_ENGINE && NET
  119. default (INTEL_IOATDMA || FSL_DMA)
  120. help
  121. This enables the use of DMA engines in the network stack to
  122. offload receive copy-to-user operations, freeing CPU cycles.
  123. Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
  124. say N.
  125. config ASYNC_TX_DMA
  126. bool "Async_tx: Offload support for the async_tx api"
  127. depends on DMA_ENGINE
  128. help
  129. This allows the async_tx api to take advantage of offload engines for
  130. memcpy, memset, xor, and raid6 p+q operations. If your platform has
  131. a dma engine that can perform raid operations and you have enabled
  132. MD_RAID456 say Y.
  133. If unsure, say N.
  134. config DMATEST
  135. tristate "DMA Test client"
  136. depends on DMA_ENGINE
  137. help
  138. Simple DMA test client. Say N unless you're debugging a
  139. DMA Device driver.
  140. endif