synclink_cs.c 111 KB

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  1. /*
  2. * linux/drivers/char/pcmcia/synclink_cs.c
  3. *
  4. * $Id: synclink_cs.c,v 4.34 2005/09/08 13:20:54 paulkf Exp $
  5. *
  6. * Device driver for Microgate SyncLink PC Card
  7. * multiprotocol serial adapter.
  8. *
  9. * written by Paul Fulghum for Microgate Corporation
  10. * paulkf@microgate.com
  11. *
  12. * Microgate and SyncLink are trademarks of Microgate Corporation
  13. *
  14. * This code is released under the GNU General Public License (GPL)
  15. *
  16. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  17. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18. * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  19. * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  20. * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  22. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  24. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  26. * OF THE POSSIBILITY OF SUCH DAMAGE.
  27. */
  28. #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29. #if defined(__i386__)
  30. # define BREAKPOINT() asm(" int $3");
  31. #else
  32. # define BREAKPOINT() { }
  33. #endif
  34. #define MAX_DEVICE_COUNT 4
  35. #include <linux/module.h>
  36. #include <linux/errno.h>
  37. #include <linux/signal.h>
  38. #include <linux/sched.h>
  39. #include <linux/timer.h>
  40. #include <linux/time.h>
  41. #include <linux/interrupt.h>
  42. #include <linux/tty.h>
  43. #include <linux/tty_flip.h>
  44. #include <linux/serial.h>
  45. #include <linux/major.h>
  46. #include <linux/string.h>
  47. #include <linux/fcntl.h>
  48. #include <linux/ptrace.h>
  49. #include <linux/ioport.h>
  50. #include <linux/mm.h>
  51. #include <linux/seq_file.h>
  52. #include <linux/slab.h>
  53. #include <linux/netdevice.h>
  54. #include <linux/vmalloc.h>
  55. #include <linux/init.h>
  56. #include <linux/delay.h>
  57. #include <linux/ioctl.h>
  58. #include <linux/synclink.h>
  59. #include <asm/system.h>
  60. #include <asm/io.h>
  61. #include <asm/irq.h>
  62. #include <asm/dma.h>
  63. #include <linux/bitops.h>
  64. #include <asm/types.h>
  65. #include <linux/termios.h>
  66. #include <linux/workqueue.h>
  67. #include <linux/hdlc.h>
  68. #include <pcmcia/cs_types.h>
  69. #include <pcmcia/cs.h>
  70. #include <pcmcia/cistpl.h>
  71. #include <pcmcia/cisreg.h>
  72. #include <pcmcia/ds.h>
  73. #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_CS_MODULE))
  74. #define SYNCLINK_GENERIC_HDLC 1
  75. #else
  76. #define SYNCLINK_GENERIC_HDLC 0
  77. #endif
  78. #define GET_USER(error,value,addr) error = get_user(value,addr)
  79. #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  80. #define PUT_USER(error,value,addr) error = put_user(value,addr)
  81. #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  82. #include <asm/uaccess.h>
  83. static MGSL_PARAMS default_params = {
  84. MGSL_MODE_HDLC, /* unsigned long mode */
  85. 0, /* unsigned char loopback; */
  86. HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
  87. HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
  88. 0, /* unsigned long clock_speed; */
  89. 0xff, /* unsigned char addr_filter; */
  90. HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
  91. HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
  92. HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
  93. 9600, /* unsigned long data_rate; */
  94. 8, /* unsigned char data_bits; */
  95. 1, /* unsigned char stop_bits; */
  96. ASYNC_PARITY_NONE /* unsigned char parity; */
  97. };
  98. typedef struct
  99. {
  100. int count;
  101. unsigned char status;
  102. char data[1];
  103. } RXBUF;
  104. /* The queue of BH actions to be performed */
  105. #define BH_RECEIVE 1
  106. #define BH_TRANSMIT 2
  107. #define BH_STATUS 4
  108. #define IO_PIN_SHUTDOWN_LIMIT 100
  109. #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
  110. struct _input_signal_events {
  111. int ri_up;
  112. int ri_down;
  113. int dsr_up;
  114. int dsr_down;
  115. int dcd_up;
  116. int dcd_down;
  117. int cts_up;
  118. int cts_down;
  119. };
  120. /*
  121. * Device instance data structure
  122. */
  123. typedef struct _mgslpc_info {
  124. struct tty_port port;
  125. void *if_ptr; /* General purpose pointer (used by SPPP) */
  126. int magic;
  127. int line;
  128. struct mgsl_icount icount;
  129. int timeout;
  130. int x_char; /* xon/xoff character */
  131. unsigned char read_status_mask;
  132. unsigned char ignore_status_mask;
  133. unsigned char *tx_buf;
  134. int tx_put;
  135. int tx_get;
  136. int tx_count;
  137. /* circular list of fixed length rx buffers */
  138. unsigned char *rx_buf; /* memory allocated for all rx buffers */
  139. int rx_buf_total_size; /* size of memory allocated for rx buffers */
  140. int rx_put; /* index of next empty rx buffer */
  141. int rx_get; /* index of next full rx buffer */
  142. int rx_buf_size; /* size in bytes of single rx buffer */
  143. int rx_buf_count; /* total number of rx buffers */
  144. int rx_frame_count; /* number of full rx buffers */
  145. wait_queue_head_t status_event_wait_q;
  146. wait_queue_head_t event_wait_q;
  147. struct timer_list tx_timer; /* HDLC transmit timeout timer */
  148. struct _mgslpc_info *next_device; /* device list link */
  149. unsigned short imra_value;
  150. unsigned short imrb_value;
  151. unsigned char pim_value;
  152. spinlock_t lock;
  153. struct work_struct task; /* task structure for scheduling bh */
  154. u32 max_frame_size;
  155. u32 pending_bh;
  156. bool bh_running;
  157. bool bh_requested;
  158. int dcd_chkcount; /* check counts to prevent */
  159. int cts_chkcount; /* too many IRQs if a signal */
  160. int dsr_chkcount; /* is floating */
  161. int ri_chkcount;
  162. bool rx_enabled;
  163. bool rx_overflow;
  164. bool tx_enabled;
  165. bool tx_active;
  166. bool tx_aborting;
  167. u32 idle_mode;
  168. int if_mode; /* serial interface selection (RS-232, v.35 etc) */
  169. char device_name[25]; /* device instance name */
  170. unsigned int io_base; /* base I/O address of adapter */
  171. unsigned int irq_level;
  172. MGSL_PARAMS params; /* communications parameters */
  173. unsigned char serial_signals; /* current serial signal states */
  174. bool irq_occurred; /* for diagnostics use */
  175. char testing_irq;
  176. unsigned int init_error; /* startup error (DIAGS) */
  177. char flag_buf[MAX_ASYNC_BUFFER_SIZE];
  178. bool drop_rts_on_tx_done;
  179. struct _input_signal_events input_signal_events;
  180. /* PCMCIA support */
  181. struct pcmcia_device *p_dev;
  182. dev_node_t node;
  183. int stop;
  184. /* SPPP/Cisco HDLC device parts */
  185. int netcount;
  186. spinlock_t netlock;
  187. #if SYNCLINK_GENERIC_HDLC
  188. struct net_device *netdev;
  189. #endif
  190. } MGSLPC_INFO;
  191. #define MGSLPC_MAGIC 0x5402
  192. /*
  193. * The size of the serial xmit buffer is 1 page, or 4096 bytes
  194. */
  195. #define TXBUFSIZE 4096
  196. #define CHA 0x00 /* channel A offset */
  197. #define CHB 0x40 /* channel B offset */
  198. /*
  199. * FIXME: PPC has PVR defined in asm/reg.h. For now we just undef it.
  200. */
  201. #undef PVR
  202. #define RXFIFO 0
  203. #define TXFIFO 0
  204. #define STAR 0x20
  205. #define CMDR 0x20
  206. #define RSTA 0x21
  207. #define PRE 0x21
  208. #define MODE 0x22
  209. #define TIMR 0x23
  210. #define XAD1 0x24
  211. #define XAD2 0x25
  212. #define RAH1 0x26
  213. #define RAH2 0x27
  214. #define DAFO 0x27
  215. #define RAL1 0x28
  216. #define RFC 0x28
  217. #define RHCR 0x29
  218. #define RAL2 0x29
  219. #define RBCL 0x2a
  220. #define XBCL 0x2a
  221. #define RBCH 0x2b
  222. #define XBCH 0x2b
  223. #define CCR0 0x2c
  224. #define CCR1 0x2d
  225. #define CCR2 0x2e
  226. #define CCR3 0x2f
  227. #define VSTR 0x34
  228. #define BGR 0x34
  229. #define RLCR 0x35
  230. #define AML 0x36
  231. #define AMH 0x37
  232. #define GIS 0x38
  233. #define IVA 0x38
  234. #define IPC 0x39
  235. #define ISR 0x3a
  236. #define IMR 0x3a
  237. #define PVR 0x3c
  238. #define PIS 0x3d
  239. #define PIM 0x3d
  240. #define PCR 0x3e
  241. #define CCR4 0x3f
  242. // IMR/ISR
  243. #define IRQ_BREAK_ON BIT15 // rx break detected
  244. #define IRQ_DATAOVERRUN BIT14 // receive data overflow
  245. #define IRQ_ALLSENT BIT13 // all sent
  246. #define IRQ_UNDERRUN BIT12 // transmit data underrun
  247. #define IRQ_TIMER BIT11 // timer interrupt
  248. #define IRQ_CTS BIT10 // CTS status change
  249. #define IRQ_TXREPEAT BIT9 // tx message repeat
  250. #define IRQ_TXFIFO BIT8 // transmit pool ready
  251. #define IRQ_RXEOM BIT7 // receive message end
  252. #define IRQ_EXITHUNT BIT6 // receive frame start
  253. #define IRQ_RXTIME BIT6 // rx char timeout
  254. #define IRQ_DCD BIT2 // carrier detect status change
  255. #define IRQ_OVERRUN BIT1 // receive frame overflow
  256. #define IRQ_RXFIFO BIT0 // receive pool full
  257. // STAR
  258. #define XFW BIT6 // transmit FIFO write enable
  259. #define CEC BIT2 // command executing
  260. #define CTS BIT1 // CTS state
  261. #define PVR_DTR BIT0
  262. #define PVR_DSR BIT1
  263. #define PVR_RI BIT2
  264. #define PVR_AUTOCTS BIT3
  265. #define PVR_RS232 0x20 /* 0010b */
  266. #define PVR_V35 0xe0 /* 1110b */
  267. #define PVR_RS422 0x40 /* 0100b */
  268. /* Register access functions */
  269. #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
  270. #define read_reg(info, reg) inb((info)->io_base + (reg))
  271. #define read_reg16(info, reg) inw((info)->io_base + (reg))
  272. #define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
  273. #define set_reg_bits(info, reg, mask) \
  274. write_reg(info, (reg), \
  275. (unsigned char) (read_reg(info, (reg)) | (mask)))
  276. #define clear_reg_bits(info, reg, mask) \
  277. write_reg(info, (reg), \
  278. (unsigned char) (read_reg(info, (reg)) & ~(mask)))
  279. /*
  280. * interrupt enable/disable routines
  281. */
  282. static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
  283. {
  284. if (channel == CHA) {
  285. info->imra_value |= mask;
  286. write_reg16(info, CHA + IMR, info->imra_value);
  287. } else {
  288. info->imrb_value |= mask;
  289. write_reg16(info, CHB + IMR, info->imrb_value);
  290. }
  291. }
  292. static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
  293. {
  294. if (channel == CHA) {
  295. info->imra_value &= ~mask;
  296. write_reg16(info, CHA + IMR, info->imra_value);
  297. } else {
  298. info->imrb_value &= ~mask;
  299. write_reg16(info, CHB + IMR, info->imrb_value);
  300. }
  301. }
  302. #define port_irq_disable(info, mask) \
  303. { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
  304. #define port_irq_enable(info, mask) \
  305. { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
  306. static void rx_start(MGSLPC_INFO *info);
  307. static void rx_stop(MGSLPC_INFO *info);
  308. static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty);
  309. static void tx_stop(MGSLPC_INFO *info);
  310. static void tx_set_idle(MGSLPC_INFO *info);
  311. static void get_signals(MGSLPC_INFO *info);
  312. static void set_signals(MGSLPC_INFO *info);
  313. static void reset_device(MGSLPC_INFO *info);
  314. static void hdlc_mode(MGSLPC_INFO *info);
  315. static void async_mode(MGSLPC_INFO *info);
  316. static void tx_timeout(unsigned long context);
  317. static int carrier_raised(struct tty_port *port);
  318. static void dtr_rts(struct tty_port *port, int onoff);
  319. #if SYNCLINK_GENERIC_HDLC
  320. #define dev_to_port(D) (dev_to_hdlc(D)->priv)
  321. static void hdlcdev_tx_done(MGSLPC_INFO *info);
  322. static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size);
  323. static int hdlcdev_init(MGSLPC_INFO *info);
  324. static void hdlcdev_exit(MGSLPC_INFO *info);
  325. #endif
  326. static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit);
  327. static bool register_test(MGSLPC_INFO *info);
  328. static bool irq_test(MGSLPC_INFO *info);
  329. static int adapter_test(MGSLPC_INFO *info);
  330. static int claim_resources(MGSLPC_INFO *info);
  331. static void release_resources(MGSLPC_INFO *info);
  332. static void mgslpc_add_device(MGSLPC_INFO *info);
  333. static void mgslpc_remove_device(MGSLPC_INFO *info);
  334. static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty);
  335. static void rx_reset_buffers(MGSLPC_INFO *info);
  336. static int rx_alloc_buffers(MGSLPC_INFO *info);
  337. static void rx_free_buffers(MGSLPC_INFO *info);
  338. static irqreturn_t mgslpc_isr(int irq, void *dev_id);
  339. /*
  340. * Bottom half interrupt handlers
  341. */
  342. static void bh_handler(struct work_struct *work);
  343. static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty);
  344. static void bh_status(MGSLPC_INFO *info);
  345. /*
  346. * ioctl handlers
  347. */
  348. static int tiocmget(struct tty_struct *tty, struct file *file);
  349. static int tiocmset(struct tty_struct *tty, struct file *file,
  350. unsigned int set, unsigned int clear);
  351. static int get_stats(MGSLPC_INFO *info, struct mgsl_icount __user *user_icount);
  352. static int get_params(MGSLPC_INFO *info, MGSL_PARAMS __user *user_params);
  353. static int set_params(MGSLPC_INFO *info, MGSL_PARAMS __user *new_params, struct tty_struct *tty);
  354. static int get_txidle(MGSLPC_INFO *info, int __user *idle_mode);
  355. static int set_txidle(MGSLPC_INFO *info, int idle_mode);
  356. static int set_txenable(MGSLPC_INFO *info, int enable, struct tty_struct *tty);
  357. static int tx_abort(MGSLPC_INFO *info);
  358. static int set_rxenable(MGSLPC_INFO *info, int enable);
  359. static int wait_events(MGSLPC_INFO *info, int __user *mask);
  360. static MGSLPC_INFO *mgslpc_device_list = NULL;
  361. static int mgslpc_device_count = 0;
  362. /*
  363. * Set this param to non-zero to load eax with the
  364. * .text section address and breakpoint on module load.
  365. * This is useful for use with gdb and add-symbol-file command.
  366. */
  367. static int break_on_load=0;
  368. /*
  369. * Driver major number, defaults to zero to get auto
  370. * assigned major number. May be forced as module parameter.
  371. */
  372. static int ttymajor=0;
  373. static int debug_level = 0;
  374. static int maxframe[MAX_DEVICE_COUNT] = {0,};
  375. module_param(break_on_load, bool, 0);
  376. module_param(ttymajor, int, 0);
  377. module_param(debug_level, int, 0);
  378. module_param_array(maxframe, int, NULL, 0);
  379. MODULE_LICENSE("GPL");
  380. static char *driver_name = "SyncLink PC Card driver";
  381. static char *driver_version = "$Revision: 4.34 $";
  382. static struct tty_driver *serial_driver;
  383. /* number of characters left in xmit buffer before we ask for more */
  384. #define WAKEUP_CHARS 256
  385. static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty);
  386. static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout);
  387. /* PCMCIA prototypes */
  388. static int mgslpc_config(struct pcmcia_device *link);
  389. static void mgslpc_release(u_long arg);
  390. static void mgslpc_detach(struct pcmcia_device *p_dev);
  391. /*
  392. * 1st function defined in .text section. Calling this function in
  393. * init_module() followed by a breakpoint allows a remote debugger
  394. * (gdb) to get the .text address for the add-symbol-file command.
  395. * This allows remote debugging of dynamically loadable modules.
  396. */
  397. static void* mgslpc_get_text_ptr(void)
  398. {
  399. return mgslpc_get_text_ptr;
  400. }
  401. /**
  402. * line discipline callback wrappers
  403. *
  404. * The wrappers maintain line discipline references
  405. * while calling into the line discipline.
  406. *
  407. * ldisc_receive_buf - pass receive data to line discipline
  408. */
  409. static void ldisc_receive_buf(struct tty_struct *tty,
  410. const __u8 *data, char *flags, int count)
  411. {
  412. struct tty_ldisc *ld;
  413. if (!tty)
  414. return;
  415. ld = tty_ldisc_ref(tty);
  416. if (ld) {
  417. if (ld->ops->receive_buf)
  418. ld->ops->receive_buf(tty, data, flags, count);
  419. tty_ldisc_deref(ld);
  420. }
  421. }
  422. static const struct tty_port_operations mgslpc_port_ops = {
  423. .carrier_raised = carrier_raised,
  424. .dtr_rts = dtr_rts
  425. };
  426. static int mgslpc_probe(struct pcmcia_device *link)
  427. {
  428. MGSLPC_INFO *info;
  429. int ret;
  430. if (debug_level >= DEBUG_LEVEL_INFO)
  431. printk("mgslpc_attach\n");
  432. info = kzalloc(sizeof(MGSLPC_INFO), GFP_KERNEL);
  433. if (!info) {
  434. printk("Error can't allocate device instance data\n");
  435. return -ENOMEM;
  436. }
  437. info->magic = MGSLPC_MAGIC;
  438. tty_port_init(&info->port);
  439. info->port.ops = &mgslpc_port_ops;
  440. INIT_WORK(&info->task, bh_handler);
  441. info->max_frame_size = 4096;
  442. info->port.close_delay = 5*HZ/10;
  443. info->port.closing_wait = 30*HZ;
  444. init_waitqueue_head(&info->status_event_wait_q);
  445. init_waitqueue_head(&info->event_wait_q);
  446. spin_lock_init(&info->lock);
  447. spin_lock_init(&info->netlock);
  448. memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
  449. info->idle_mode = HDLC_TXIDLE_FLAGS;
  450. info->imra_value = 0xffff;
  451. info->imrb_value = 0xffff;
  452. info->pim_value = 0xff;
  453. info->p_dev = link;
  454. link->priv = info;
  455. /* Initialize the struct pcmcia_device structure */
  456. /* Interrupt setup */
  457. link->irq.Attributes = IRQ_TYPE_DYNAMIC_SHARING;
  458. link->irq.Handler = NULL;
  459. link->conf.Attributes = 0;
  460. link->conf.IntType = INT_MEMORY_AND_IO;
  461. ret = mgslpc_config(link);
  462. if (ret)
  463. return ret;
  464. mgslpc_add_device(info);
  465. return 0;
  466. }
  467. /* Card has been inserted.
  468. */
  469. static int mgslpc_ioprobe(struct pcmcia_device *p_dev,
  470. cistpl_cftable_entry_t *cfg,
  471. cistpl_cftable_entry_t *dflt,
  472. unsigned int vcc,
  473. void *priv_data)
  474. {
  475. if (cfg->io.nwin > 0) {
  476. p_dev->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
  477. if (!(cfg->io.flags & CISTPL_IO_8BIT))
  478. p_dev->io.Attributes1 = IO_DATA_PATH_WIDTH_16;
  479. if (!(cfg->io.flags & CISTPL_IO_16BIT))
  480. p_dev->io.Attributes1 = IO_DATA_PATH_WIDTH_8;
  481. p_dev->io.IOAddrLines = cfg->io.flags & CISTPL_IO_LINES_MASK;
  482. p_dev->io.BasePort1 = cfg->io.win[0].base;
  483. p_dev->io.NumPorts1 = cfg->io.win[0].len;
  484. return pcmcia_request_io(p_dev, &p_dev->io);
  485. }
  486. return -ENODEV;
  487. }
  488. static int mgslpc_config(struct pcmcia_device *link)
  489. {
  490. MGSLPC_INFO *info = link->priv;
  491. int ret;
  492. if (debug_level >= DEBUG_LEVEL_INFO)
  493. printk("mgslpc_config(0x%p)\n", link);
  494. ret = pcmcia_loop_config(link, mgslpc_ioprobe, NULL);
  495. if (ret != 0)
  496. goto failed;
  497. link->conf.Attributes = CONF_ENABLE_IRQ;
  498. link->conf.IntType = INT_MEMORY_AND_IO;
  499. link->conf.ConfigIndex = 8;
  500. link->conf.Present = PRESENT_OPTION;
  501. link->irq.Handler = mgslpc_isr;
  502. ret = pcmcia_request_irq(link, &link->irq);
  503. if (ret)
  504. goto failed;
  505. ret = pcmcia_request_configuration(link, &link->conf);
  506. if (ret)
  507. goto failed;
  508. info->io_base = link->io.BasePort1;
  509. info->irq_level = link->irq.AssignedIRQ;
  510. /* add to linked list of devices */
  511. sprintf(info->node.dev_name, "mgslpc0");
  512. info->node.major = info->node.minor = 0;
  513. link->dev_node = &info->node;
  514. printk(KERN_INFO "%s: index 0x%02x:",
  515. info->node.dev_name, link->conf.ConfigIndex);
  516. if (link->conf.Attributes & CONF_ENABLE_IRQ)
  517. printk(", irq %d", link->irq.AssignedIRQ);
  518. if (link->io.NumPorts1)
  519. printk(", io 0x%04x-0x%04x", link->io.BasePort1,
  520. link->io.BasePort1+link->io.NumPorts1-1);
  521. printk("\n");
  522. return 0;
  523. failed:
  524. mgslpc_release((u_long)link);
  525. return -ENODEV;
  526. }
  527. /* Card has been removed.
  528. * Unregister device and release PCMCIA configuration.
  529. * If device is open, postpone until it is closed.
  530. */
  531. static void mgslpc_release(u_long arg)
  532. {
  533. struct pcmcia_device *link = (struct pcmcia_device *)arg;
  534. if (debug_level >= DEBUG_LEVEL_INFO)
  535. printk("mgslpc_release(0x%p)\n", link);
  536. pcmcia_disable_device(link);
  537. }
  538. static void mgslpc_detach(struct pcmcia_device *link)
  539. {
  540. if (debug_level >= DEBUG_LEVEL_INFO)
  541. printk("mgslpc_detach(0x%p)\n", link);
  542. ((MGSLPC_INFO *)link->priv)->stop = 1;
  543. mgslpc_release((u_long)link);
  544. mgslpc_remove_device((MGSLPC_INFO *)link->priv);
  545. }
  546. static int mgslpc_suspend(struct pcmcia_device *link)
  547. {
  548. MGSLPC_INFO *info = link->priv;
  549. info->stop = 1;
  550. return 0;
  551. }
  552. static int mgslpc_resume(struct pcmcia_device *link)
  553. {
  554. MGSLPC_INFO *info = link->priv;
  555. info->stop = 0;
  556. return 0;
  557. }
  558. static inline bool mgslpc_paranoia_check(MGSLPC_INFO *info,
  559. char *name, const char *routine)
  560. {
  561. #ifdef MGSLPC_PARANOIA_CHECK
  562. static const char *badmagic =
  563. "Warning: bad magic number for mgsl struct (%s) in %s\n";
  564. static const char *badinfo =
  565. "Warning: null mgslpc_info for (%s) in %s\n";
  566. if (!info) {
  567. printk(badinfo, name, routine);
  568. return true;
  569. }
  570. if (info->magic != MGSLPC_MAGIC) {
  571. printk(badmagic, name, routine);
  572. return true;
  573. }
  574. #else
  575. if (!info)
  576. return true;
  577. #endif
  578. return false;
  579. }
  580. #define CMD_RXFIFO BIT7 // release current rx FIFO
  581. #define CMD_RXRESET BIT6 // receiver reset
  582. #define CMD_RXFIFO_READ BIT5
  583. #define CMD_START_TIMER BIT4
  584. #define CMD_TXFIFO BIT3 // release current tx FIFO
  585. #define CMD_TXEOM BIT1 // transmit end message
  586. #define CMD_TXRESET BIT0 // transmit reset
  587. static bool wait_command_complete(MGSLPC_INFO *info, unsigned char channel)
  588. {
  589. int i = 0;
  590. /* wait for command completion */
  591. while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) {
  592. udelay(1);
  593. if (i++ == 1000)
  594. return false;
  595. }
  596. return true;
  597. }
  598. static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd)
  599. {
  600. wait_command_complete(info, channel);
  601. write_reg(info, (unsigned char) (channel + CMDR), cmd);
  602. }
  603. static void tx_pause(struct tty_struct *tty)
  604. {
  605. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  606. unsigned long flags;
  607. if (mgslpc_paranoia_check(info, tty->name, "tx_pause"))
  608. return;
  609. if (debug_level >= DEBUG_LEVEL_INFO)
  610. printk("tx_pause(%s)\n",info->device_name);
  611. spin_lock_irqsave(&info->lock,flags);
  612. if (info->tx_enabled)
  613. tx_stop(info);
  614. spin_unlock_irqrestore(&info->lock,flags);
  615. }
  616. static void tx_release(struct tty_struct *tty)
  617. {
  618. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  619. unsigned long flags;
  620. if (mgslpc_paranoia_check(info, tty->name, "tx_release"))
  621. return;
  622. if (debug_level >= DEBUG_LEVEL_INFO)
  623. printk("tx_release(%s)\n",info->device_name);
  624. spin_lock_irqsave(&info->lock,flags);
  625. if (!info->tx_enabled)
  626. tx_start(info, tty);
  627. spin_unlock_irqrestore(&info->lock,flags);
  628. }
  629. /* Return next bottom half action to perform.
  630. * or 0 if nothing to do.
  631. */
  632. static int bh_action(MGSLPC_INFO *info)
  633. {
  634. unsigned long flags;
  635. int rc = 0;
  636. spin_lock_irqsave(&info->lock,flags);
  637. if (info->pending_bh & BH_RECEIVE) {
  638. info->pending_bh &= ~BH_RECEIVE;
  639. rc = BH_RECEIVE;
  640. } else if (info->pending_bh & BH_TRANSMIT) {
  641. info->pending_bh &= ~BH_TRANSMIT;
  642. rc = BH_TRANSMIT;
  643. } else if (info->pending_bh & BH_STATUS) {
  644. info->pending_bh &= ~BH_STATUS;
  645. rc = BH_STATUS;
  646. }
  647. if (!rc) {
  648. /* Mark BH routine as complete */
  649. info->bh_running = false;
  650. info->bh_requested = false;
  651. }
  652. spin_unlock_irqrestore(&info->lock,flags);
  653. return rc;
  654. }
  655. static void bh_handler(struct work_struct *work)
  656. {
  657. MGSLPC_INFO *info = container_of(work, MGSLPC_INFO, task);
  658. struct tty_struct *tty;
  659. int action;
  660. if (!info)
  661. return;
  662. if (debug_level >= DEBUG_LEVEL_BH)
  663. printk( "%s(%d):bh_handler(%s) entry\n",
  664. __FILE__,__LINE__,info->device_name);
  665. info->bh_running = true;
  666. tty = tty_port_tty_get(&info->port);
  667. while((action = bh_action(info)) != 0) {
  668. /* Process work item */
  669. if ( debug_level >= DEBUG_LEVEL_BH )
  670. printk( "%s(%d):bh_handler() work item action=%d\n",
  671. __FILE__,__LINE__,action);
  672. switch (action) {
  673. case BH_RECEIVE:
  674. while(rx_get_frame(info, tty));
  675. break;
  676. case BH_TRANSMIT:
  677. bh_transmit(info, tty);
  678. break;
  679. case BH_STATUS:
  680. bh_status(info);
  681. break;
  682. default:
  683. /* unknown work item ID */
  684. printk("Unknown work item ID=%08X!\n", action);
  685. break;
  686. }
  687. }
  688. tty_kref_put(tty);
  689. if (debug_level >= DEBUG_LEVEL_BH)
  690. printk( "%s(%d):bh_handler(%s) exit\n",
  691. __FILE__,__LINE__,info->device_name);
  692. }
  693. static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty)
  694. {
  695. if (debug_level >= DEBUG_LEVEL_BH)
  696. printk("bh_transmit() entry on %s\n", info->device_name);
  697. if (tty)
  698. tty_wakeup(tty);
  699. }
  700. static void bh_status(MGSLPC_INFO *info)
  701. {
  702. info->ri_chkcount = 0;
  703. info->dsr_chkcount = 0;
  704. info->dcd_chkcount = 0;
  705. info->cts_chkcount = 0;
  706. }
  707. /* eom: non-zero = end of frame */
  708. static void rx_ready_hdlc(MGSLPC_INFO *info, int eom)
  709. {
  710. unsigned char data[2];
  711. unsigned char fifo_count, read_count, i;
  712. RXBUF *buf = (RXBUF*)(info->rx_buf + (info->rx_put * info->rx_buf_size));
  713. if (debug_level >= DEBUG_LEVEL_ISR)
  714. printk("%s(%d):rx_ready_hdlc(eom=%d)\n",__FILE__,__LINE__,eom);
  715. if (!info->rx_enabled)
  716. return;
  717. if (info->rx_frame_count >= info->rx_buf_count) {
  718. /* no more free buffers */
  719. issue_command(info, CHA, CMD_RXRESET);
  720. info->pending_bh |= BH_RECEIVE;
  721. info->rx_overflow = true;
  722. info->icount.buf_overrun++;
  723. return;
  724. }
  725. if (eom) {
  726. /* end of frame, get FIFO count from RBCL register */
  727. if (!(fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f)))
  728. fifo_count = 32;
  729. } else
  730. fifo_count = 32;
  731. do {
  732. if (fifo_count == 1) {
  733. read_count = 1;
  734. data[0] = read_reg(info, CHA + RXFIFO);
  735. } else {
  736. read_count = 2;
  737. *((unsigned short *) data) = read_reg16(info, CHA + RXFIFO);
  738. }
  739. fifo_count -= read_count;
  740. if (!fifo_count && eom)
  741. buf->status = data[--read_count];
  742. for (i = 0; i < read_count; i++) {
  743. if (buf->count >= info->max_frame_size) {
  744. /* frame too large, reset receiver and reset current buffer */
  745. issue_command(info, CHA, CMD_RXRESET);
  746. buf->count = 0;
  747. return;
  748. }
  749. *(buf->data + buf->count) = data[i];
  750. buf->count++;
  751. }
  752. } while (fifo_count);
  753. if (eom) {
  754. info->pending_bh |= BH_RECEIVE;
  755. info->rx_frame_count++;
  756. info->rx_put++;
  757. if (info->rx_put >= info->rx_buf_count)
  758. info->rx_put = 0;
  759. }
  760. issue_command(info, CHA, CMD_RXFIFO);
  761. }
  762. static void rx_ready_async(MGSLPC_INFO *info, int tcd, struct tty_struct *tty)
  763. {
  764. unsigned char data, status, flag;
  765. int fifo_count;
  766. int work = 0;
  767. struct mgsl_icount *icount = &info->icount;
  768. if (tcd) {
  769. /* early termination, get FIFO count from RBCL register */
  770. fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
  771. /* Zero fifo count could mean 0 or 32 bytes available.
  772. * If BIT5 of STAR is set then at least 1 byte is available.
  773. */
  774. if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))
  775. fifo_count = 32;
  776. } else
  777. fifo_count = 32;
  778. tty_buffer_request_room(tty, fifo_count);
  779. /* Flush received async data to receive data buffer. */
  780. while (fifo_count) {
  781. data = read_reg(info, CHA + RXFIFO);
  782. status = read_reg(info, CHA + RXFIFO);
  783. fifo_count -= 2;
  784. icount->rx++;
  785. flag = TTY_NORMAL;
  786. // if no frameing/crc error then save data
  787. // BIT7:parity error
  788. // BIT6:framing error
  789. if (status & (BIT7 + BIT6)) {
  790. if (status & BIT7)
  791. icount->parity++;
  792. else
  793. icount->frame++;
  794. /* discard char if tty control flags say so */
  795. if (status & info->ignore_status_mask)
  796. continue;
  797. status &= info->read_status_mask;
  798. if (status & BIT7)
  799. flag = TTY_PARITY;
  800. else if (status & BIT6)
  801. flag = TTY_FRAME;
  802. }
  803. work += tty_insert_flip_char(tty, data, flag);
  804. }
  805. issue_command(info, CHA, CMD_RXFIFO);
  806. if (debug_level >= DEBUG_LEVEL_ISR) {
  807. printk("%s(%d):rx_ready_async",
  808. __FILE__,__LINE__);
  809. printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
  810. __FILE__,__LINE__,icount->rx,icount->brk,
  811. icount->parity,icount->frame,icount->overrun);
  812. }
  813. if (work)
  814. tty_flip_buffer_push(tty);
  815. }
  816. static void tx_done(MGSLPC_INFO *info, struct tty_struct *tty)
  817. {
  818. if (!info->tx_active)
  819. return;
  820. info->tx_active = false;
  821. info->tx_aborting = false;
  822. if (info->params.mode == MGSL_MODE_ASYNC)
  823. return;
  824. info->tx_count = info->tx_put = info->tx_get = 0;
  825. del_timer(&info->tx_timer);
  826. if (info->drop_rts_on_tx_done) {
  827. get_signals(info);
  828. if (info->serial_signals & SerialSignal_RTS) {
  829. info->serial_signals &= ~SerialSignal_RTS;
  830. set_signals(info);
  831. }
  832. info->drop_rts_on_tx_done = false;
  833. }
  834. #if SYNCLINK_GENERIC_HDLC
  835. if (info->netcount)
  836. hdlcdev_tx_done(info);
  837. else
  838. #endif
  839. {
  840. if (tty->stopped || tty->hw_stopped) {
  841. tx_stop(info);
  842. return;
  843. }
  844. info->pending_bh |= BH_TRANSMIT;
  845. }
  846. }
  847. static void tx_ready(MGSLPC_INFO *info, struct tty_struct *tty)
  848. {
  849. unsigned char fifo_count = 32;
  850. int c;
  851. if (debug_level >= DEBUG_LEVEL_ISR)
  852. printk("%s(%d):tx_ready(%s)\n", __FILE__,__LINE__,info->device_name);
  853. if (info->params.mode == MGSL_MODE_HDLC) {
  854. if (!info->tx_active)
  855. return;
  856. } else {
  857. if (tty->stopped || tty->hw_stopped) {
  858. tx_stop(info);
  859. return;
  860. }
  861. if (!info->tx_count)
  862. info->tx_active = false;
  863. }
  864. if (!info->tx_count)
  865. return;
  866. while (info->tx_count && fifo_count) {
  867. c = min(2, min_t(int, fifo_count, min(info->tx_count, TXBUFSIZE - info->tx_get)));
  868. if (c == 1) {
  869. write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));
  870. } else {
  871. write_reg16(info, CHA + TXFIFO,
  872. *((unsigned short*)(info->tx_buf + info->tx_get)));
  873. }
  874. info->tx_count -= c;
  875. info->tx_get = (info->tx_get + c) & (TXBUFSIZE - 1);
  876. fifo_count -= c;
  877. }
  878. if (info->params.mode == MGSL_MODE_ASYNC) {
  879. if (info->tx_count < WAKEUP_CHARS)
  880. info->pending_bh |= BH_TRANSMIT;
  881. issue_command(info, CHA, CMD_TXFIFO);
  882. } else {
  883. if (info->tx_count)
  884. issue_command(info, CHA, CMD_TXFIFO);
  885. else
  886. issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM);
  887. }
  888. }
  889. static void cts_change(MGSLPC_INFO *info, struct tty_struct *tty)
  890. {
  891. get_signals(info);
  892. if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  893. irq_disable(info, CHB, IRQ_CTS);
  894. info->icount.cts++;
  895. if (info->serial_signals & SerialSignal_CTS)
  896. info->input_signal_events.cts_up++;
  897. else
  898. info->input_signal_events.cts_down++;
  899. wake_up_interruptible(&info->status_event_wait_q);
  900. wake_up_interruptible(&info->event_wait_q);
  901. if (info->port.flags & ASYNC_CTS_FLOW) {
  902. if (tty->hw_stopped) {
  903. if (info->serial_signals & SerialSignal_CTS) {
  904. if (debug_level >= DEBUG_LEVEL_ISR)
  905. printk("CTS tx start...");
  906. if (tty)
  907. tty->hw_stopped = 0;
  908. tx_start(info, tty);
  909. info->pending_bh |= BH_TRANSMIT;
  910. return;
  911. }
  912. } else {
  913. if (!(info->serial_signals & SerialSignal_CTS)) {
  914. if (debug_level >= DEBUG_LEVEL_ISR)
  915. printk("CTS tx stop...");
  916. if (tty)
  917. tty->hw_stopped = 1;
  918. tx_stop(info);
  919. }
  920. }
  921. }
  922. info->pending_bh |= BH_STATUS;
  923. }
  924. static void dcd_change(MGSLPC_INFO *info, struct tty_struct *tty)
  925. {
  926. get_signals(info);
  927. if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  928. irq_disable(info, CHB, IRQ_DCD);
  929. info->icount.dcd++;
  930. if (info->serial_signals & SerialSignal_DCD) {
  931. info->input_signal_events.dcd_up++;
  932. }
  933. else
  934. info->input_signal_events.dcd_down++;
  935. #if SYNCLINK_GENERIC_HDLC
  936. if (info->netcount) {
  937. if (info->serial_signals & SerialSignal_DCD)
  938. netif_carrier_on(info->netdev);
  939. else
  940. netif_carrier_off(info->netdev);
  941. }
  942. #endif
  943. wake_up_interruptible(&info->status_event_wait_q);
  944. wake_up_interruptible(&info->event_wait_q);
  945. if (info->port.flags & ASYNC_CHECK_CD) {
  946. if (debug_level >= DEBUG_LEVEL_ISR)
  947. printk("%s CD now %s...", info->device_name,
  948. (info->serial_signals & SerialSignal_DCD) ? "on" : "off");
  949. if (info->serial_signals & SerialSignal_DCD)
  950. wake_up_interruptible(&info->port.open_wait);
  951. else {
  952. if (debug_level >= DEBUG_LEVEL_ISR)
  953. printk("doing serial hangup...");
  954. if (tty)
  955. tty_hangup(tty);
  956. }
  957. }
  958. info->pending_bh |= BH_STATUS;
  959. }
  960. static void dsr_change(MGSLPC_INFO *info)
  961. {
  962. get_signals(info);
  963. if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  964. port_irq_disable(info, PVR_DSR);
  965. info->icount.dsr++;
  966. if (info->serial_signals & SerialSignal_DSR)
  967. info->input_signal_events.dsr_up++;
  968. else
  969. info->input_signal_events.dsr_down++;
  970. wake_up_interruptible(&info->status_event_wait_q);
  971. wake_up_interruptible(&info->event_wait_q);
  972. info->pending_bh |= BH_STATUS;
  973. }
  974. static void ri_change(MGSLPC_INFO *info)
  975. {
  976. get_signals(info);
  977. if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  978. port_irq_disable(info, PVR_RI);
  979. info->icount.rng++;
  980. if (info->serial_signals & SerialSignal_RI)
  981. info->input_signal_events.ri_up++;
  982. else
  983. info->input_signal_events.ri_down++;
  984. wake_up_interruptible(&info->status_event_wait_q);
  985. wake_up_interruptible(&info->event_wait_q);
  986. info->pending_bh |= BH_STATUS;
  987. }
  988. /* Interrupt service routine entry point.
  989. *
  990. * Arguments:
  991. *
  992. * irq interrupt number that caused interrupt
  993. * dev_id device ID supplied during interrupt registration
  994. */
  995. static irqreturn_t mgslpc_isr(int dummy, void *dev_id)
  996. {
  997. MGSLPC_INFO *info = dev_id;
  998. struct tty_struct *tty;
  999. unsigned short isr;
  1000. unsigned char gis, pis;
  1001. int count=0;
  1002. if (debug_level >= DEBUG_LEVEL_ISR)
  1003. printk("mgslpc_isr(%d) entry.\n", info->irq_level);
  1004. if (!(info->p_dev->_locked))
  1005. return IRQ_HANDLED;
  1006. tty = tty_port_tty_get(&info->port);
  1007. spin_lock(&info->lock);
  1008. while ((gis = read_reg(info, CHA + GIS))) {
  1009. if (debug_level >= DEBUG_LEVEL_ISR)
  1010. printk("mgslpc_isr %s gis=%04X\n", info->device_name,gis);
  1011. if ((gis & 0x70) || count > 1000) {
  1012. printk("synclink_cs:hardware failed or ejected\n");
  1013. break;
  1014. }
  1015. count++;
  1016. if (gis & (BIT1 + BIT0)) {
  1017. isr = read_reg16(info, CHB + ISR);
  1018. if (isr & IRQ_DCD)
  1019. dcd_change(info, tty);
  1020. if (isr & IRQ_CTS)
  1021. cts_change(info, tty);
  1022. }
  1023. if (gis & (BIT3 + BIT2))
  1024. {
  1025. isr = read_reg16(info, CHA + ISR);
  1026. if (isr & IRQ_TIMER) {
  1027. info->irq_occurred = true;
  1028. irq_disable(info, CHA, IRQ_TIMER);
  1029. }
  1030. /* receive IRQs */
  1031. if (isr & IRQ_EXITHUNT) {
  1032. info->icount.exithunt++;
  1033. wake_up_interruptible(&info->event_wait_q);
  1034. }
  1035. if (isr & IRQ_BREAK_ON) {
  1036. info->icount.brk++;
  1037. if (info->port.flags & ASYNC_SAK)
  1038. do_SAK(tty);
  1039. }
  1040. if (isr & IRQ_RXTIME) {
  1041. issue_command(info, CHA, CMD_RXFIFO_READ);
  1042. }
  1043. if (isr & (IRQ_RXEOM + IRQ_RXFIFO)) {
  1044. if (info->params.mode == MGSL_MODE_HDLC)
  1045. rx_ready_hdlc(info, isr & IRQ_RXEOM);
  1046. else
  1047. rx_ready_async(info, isr & IRQ_RXEOM, tty);
  1048. }
  1049. /* transmit IRQs */
  1050. if (isr & IRQ_UNDERRUN) {
  1051. if (info->tx_aborting)
  1052. info->icount.txabort++;
  1053. else
  1054. info->icount.txunder++;
  1055. tx_done(info, tty);
  1056. }
  1057. else if (isr & IRQ_ALLSENT) {
  1058. info->icount.txok++;
  1059. tx_done(info, tty);
  1060. }
  1061. else if (isr & IRQ_TXFIFO)
  1062. tx_ready(info, tty);
  1063. }
  1064. if (gis & BIT7) {
  1065. pis = read_reg(info, CHA + PIS);
  1066. if (pis & BIT1)
  1067. dsr_change(info);
  1068. if (pis & BIT2)
  1069. ri_change(info);
  1070. }
  1071. }
  1072. /* Request bottom half processing if there's something
  1073. * for it to do and the bh is not already running
  1074. */
  1075. if (info->pending_bh && !info->bh_running && !info->bh_requested) {
  1076. if ( debug_level >= DEBUG_LEVEL_ISR )
  1077. printk("%s(%d):%s queueing bh task.\n",
  1078. __FILE__,__LINE__,info->device_name);
  1079. schedule_work(&info->task);
  1080. info->bh_requested = true;
  1081. }
  1082. spin_unlock(&info->lock);
  1083. tty_kref_put(tty);
  1084. if (debug_level >= DEBUG_LEVEL_ISR)
  1085. printk("%s(%d):mgslpc_isr(%d)exit.\n",
  1086. __FILE__, __LINE__, info->irq_level);
  1087. return IRQ_HANDLED;
  1088. }
  1089. /* Initialize and start device.
  1090. */
  1091. static int startup(MGSLPC_INFO * info, struct tty_struct *tty)
  1092. {
  1093. int retval = 0;
  1094. if (debug_level >= DEBUG_LEVEL_INFO)
  1095. printk("%s(%d):startup(%s)\n",__FILE__,__LINE__,info->device_name);
  1096. if (info->port.flags & ASYNC_INITIALIZED)
  1097. return 0;
  1098. if (!info->tx_buf) {
  1099. /* allocate a page of memory for a transmit buffer */
  1100. info->tx_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
  1101. if (!info->tx_buf) {
  1102. printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
  1103. __FILE__,__LINE__,info->device_name);
  1104. return -ENOMEM;
  1105. }
  1106. }
  1107. info->pending_bh = 0;
  1108. memset(&info->icount, 0, sizeof(info->icount));
  1109. setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
  1110. /* Allocate and claim adapter resources */
  1111. retval = claim_resources(info);
  1112. /* perform existance check and diagnostics */
  1113. if ( !retval )
  1114. retval = adapter_test(info);
  1115. if ( retval ) {
  1116. if (capable(CAP_SYS_ADMIN) && tty)
  1117. set_bit(TTY_IO_ERROR, &tty->flags);
  1118. release_resources(info);
  1119. return retval;
  1120. }
  1121. /* program hardware for current parameters */
  1122. mgslpc_change_params(info, tty);
  1123. if (tty)
  1124. clear_bit(TTY_IO_ERROR, &tty->flags);
  1125. info->port.flags |= ASYNC_INITIALIZED;
  1126. return 0;
  1127. }
  1128. /* Called by mgslpc_close() and mgslpc_hangup() to shutdown hardware
  1129. */
  1130. static void shutdown(MGSLPC_INFO * info, struct tty_struct *tty)
  1131. {
  1132. unsigned long flags;
  1133. if (!(info->port.flags & ASYNC_INITIALIZED))
  1134. return;
  1135. if (debug_level >= DEBUG_LEVEL_INFO)
  1136. printk("%s(%d):mgslpc_shutdown(%s)\n",
  1137. __FILE__,__LINE__, info->device_name );
  1138. /* clear status wait queue because status changes */
  1139. /* can't happen after shutting down the hardware */
  1140. wake_up_interruptible(&info->status_event_wait_q);
  1141. wake_up_interruptible(&info->event_wait_q);
  1142. del_timer_sync(&info->tx_timer);
  1143. if (info->tx_buf) {
  1144. free_page((unsigned long) info->tx_buf);
  1145. info->tx_buf = NULL;
  1146. }
  1147. spin_lock_irqsave(&info->lock,flags);
  1148. rx_stop(info);
  1149. tx_stop(info);
  1150. /* TODO:disable interrupts instead of reset to preserve signal states */
  1151. reset_device(info);
  1152. if (!tty || tty->termios->c_cflag & HUPCL) {
  1153. info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
  1154. set_signals(info);
  1155. }
  1156. spin_unlock_irqrestore(&info->lock,flags);
  1157. release_resources(info);
  1158. if (tty)
  1159. set_bit(TTY_IO_ERROR, &tty->flags);
  1160. info->port.flags &= ~ASYNC_INITIALIZED;
  1161. }
  1162. static void mgslpc_program_hw(MGSLPC_INFO *info, struct tty_struct *tty)
  1163. {
  1164. unsigned long flags;
  1165. spin_lock_irqsave(&info->lock,flags);
  1166. rx_stop(info);
  1167. tx_stop(info);
  1168. info->tx_count = info->tx_put = info->tx_get = 0;
  1169. if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
  1170. hdlc_mode(info);
  1171. else
  1172. async_mode(info);
  1173. set_signals(info);
  1174. info->dcd_chkcount = 0;
  1175. info->cts_chkcount = 0;
  1176. info->ri_chkcount = 0;
  1177. info->dsr_chkcount = 0;
  1178. irq_enable(info, CHB, IRQ_DCD | IRQ_CTS);
  1179. port_irq_enable(info, (unsigned char) PVR_DSR | PVR_RI);
  1180. get_signals(info);
  1181. if (info->netcount || (tty && (tty->termios->c_cflag & CREAD)))
  1182. rx_start(info);
  1183. spin_unlock_irqrestore(&info->lock,flags);
  1184. }
  1185. /* Reconfigure adapter based on new parameters
  1186. */
  1187. static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty)
  1188. {
  1189. unsigned cflag;
  1190. int bits_per_char;
  1191. if (!tty || !tty->termios)
  1192. return;
  1193. if (debug_level >= DEBUG_LEVEL_INFO)
  1194. printk("%s(%d):mgslpc_change_params(%s)\n",
  1195. __FILE__,__LINE__, info->device_name );
  1196. cflag = tty->termios->c_cflag;
  1197. /* if B0 rate (hangup) specified then negate DTR and RTS */
  1198. /* otherwise assert DTR and RTS */
  1199. if (cflag & CBAUD)
  1200. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  1201. else
  1202. info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  1203. /* byte size and parity */
  1204. switch (cflag & CSIZE) {
  1205. case CS5: info->params.data_bits = 5; break;
  1206. case CS6: info->params.data_bits = 6; break;
  1207. case CS7: info->params.data_bits = 7; break;
  1208. case CS8: info->params.data_bits = 8; break;
  1209. default: info->params.data_bits = 7; break;
  1210. }
  1211. if (cflag & CSTOPB)
  1212. info->params.stop_bits = 2;
  1213. else
  1214. info->params.stop_bits = 1;
  1215. info->params.parity = ASYNC_PARITY_NONE;
  1216. if (cflag & PARENB) {
  1217. if (cflag & PARODD)
  1218. info->params.parity = ASYNC_PARITY_ODD;
  1219. else
  1220. info->params.parity = ASYNC_PARITY_EVEN;
  1221. #ifdef CMSPAR
  1222. if (cflag & CMSPAR)
  1223. info->params.parity = ASYNC_PARITY_SPACE;
  1224. #endif
  1225. }
  1226. /* calculate number of jiffies to transmit a full
  1227. * FIFO (32 bytes) at specified data rate
  1228. */
  1229. bits_per_char = info->params.data_bits +
  1230. info->params.stop_bits + 1;
  1231. /* if port data rate is set to 460800 or less then
  1232. * allow tty settings to override, otherwise keep the
  1233. * current data rate.
  1234. */
  1235. if (info->params.data_rate <= 460800) {
  1236. info->params.data_rate = tty_get_baud_rate(tty);
  1237. }
  1238. if ( info->params.data_rate ) {
  1239. info->timeout = (32*HZ*bits_per_char) /
  1240. info->params.data_rate;
  1241. }
  1242. info->timeout += HZ/50; /* Add .02 seconds of slop */
  1243. if (cflag & CRTSCTS)
  1244. info->port.flags |= ASYNC_CTS_FLOW;
  1245. else
  1246. info->port.flags &= ~ASYNC_CTS_FLOW;
  1247. if (cflag & CLOCAL)
  1248. info->port.flags &= ~ASYNC_CHECK_CD;
  1249. else
  1250. info->port.flags |= ASYNC_CHECK_CD;
  1251. /* process tty input control flags */
  1252. info->read_status_mask = 0;
  1253. if (I_INPCK(tty))
  1254. info->read_status_mask |= BIT7 | BIT6;
  1255. if (I_IGNPAR(tty))
  1256. info->ignore_status_mask |= BIT7 | BIT6;
  1257. mgslpc_program_hw(info, tty);
  1258. }
  1259. /* Add a character to the transmit buffer
  1260. */
  1261. static int mgslpc_put_char(struct tty_struct *tty, unsigned char ch)
  1262. {
  1263. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1264. unsigned long flags;
  1265. if (debug_level >= DEBUG_LEVEL_INFO) {
  1266. printk( "%s(%d):mgslpc_put_char(%d) on %s\n",
  1267. __FILE__,__LINE__,ch,info->device_name);
  1268. }
  1269. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_put_char"))
  1270. return 0;
  1271. if (!info->tx_buf)
  1272. return 0;
  1273. spin_lock_irqsave(&info->lock,flags);
  1274. if (info->params.mode == MGSL_MODE_ASYNC || !info->tx_active) {
  1275. if (info->tx_count < TXBUFSIZE - 1) {
  1276. info->tx_buf[info->tx_put++] = ch;
  1277. info->tx_put &= TXBUFSIZE-1;
  1278. info->tx_count++;
  1279. }
  1280. }
  1281. spin_unlock_irqrestore(&info->lock,flags);
  1282. return 1;
  1283. }
  1284. /* Enable transmitter so remaining characters in the
  1285. * transmit buffer are sent.
  1286. */
  1287. static void mgslpc_flush_chars(struct tty_struct *tty)
  1288. {
  1289. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1290. unsigned long flags;
  1291. if (debug_level >= DEBUG_LEVEL_INFO)
  1292. printk( "%s(%d):mgslpc_flush_chars() entry on %s tx_count=%d\n",
  1293. __FILE__,__LINE__,info->device_name,info->tx_count);
  1294. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars"))
  1295. return;
  1296. if (info->tx_count <= 0 || tty->stopped ||
  1297. tty->hw_stopped || !info->tx_buf)
  1298. return;
  1299. if (debug_level >= DEBUG_LEVEL_INFO)
  1300. printk( "%s(%d):mgslpc_flush_chars() entry on %s starting transmitter\n",
  1301. __FILE__,__LINE__,info->device_name);
  1302. spin_lock_irqsave(&info->lock,flags);
  1303. if (!info->tx_active)
  1304. tx_start(info, tty);
  1305. spin_unlock_irqrestore(&info->lock,flags);
  1306. }
  1307. /* Send a block of data
  1308. *
  1309. * Arguments:
  1310. *
  1311. * tty pointer to tty information structure
  1312. * buf pointer to buffer containing send data
  1313. * count size of send data in bytes
  1314. *
  1315. * Returns: number of characters written
  1316. */
  1317. static int mgslpc_write(struct tty_struct * tty,
  1318. const unsigned char *buf, int count)
  1319. {
  1320. int c, ret = 0;
  1321. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1322. unsigned long flags;
  1323. if (debug_level >= DEBUG_LEVEL_INFO)
  1324. printk( "%s(%d):mgslpc_write(%s) count=%d\n",
  1325. __FILE__,__LINE__,info->device_name,count);
  1326. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write") ||
  1327. !info->tx_buf)
  1328. goto cleanup;
  1329. if (info->params.mode == MGSL_MODE_HDLC) {
  1330. if (count > TXBUFSIZE) {
  1331. ret = -EIO;
  1332. goto cleanup;
  1333. }
  1334. if (info->tx_active)
  1335. goto cleanup;
  1336. else if (info->tx_count)
  1337. goto start;
  1338. }
  1339. for (;;) {
  1340. c = min(count,
  1341. min(TXBUFSIZE - info->tx_count - 1,
  1342. TXBUFSIZE - info->tx_put));
  1343. if (c <= 0)
  1344. break;
  1345. memcpy(info->tx_buf + info->tx_put, buf, c);
  1346. spin_lock_irqsave(&info->lock,flags);
  1347. info->tx_put = (info->tx_put + c) & (TXBUFSIZE-1);
  1348. info->tx_count += c;
  1349. spin_unlock_irqrestore(&info->lock,flags);
  1350. buf += c;
  1351. count -= c;
  1352. ret += c;
  1353. }
  1354. start:
  1355. if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
  1356. spin_lock_irqsave(&info->lock,flags);
  1357. if (!info->tx_active)
  1358. tx_start(info, tty);
  1359. spin_unlock_irqrestore(&info->lock,flags);
  1360. }
  1361. cleanup:
  1362. if (debug_level >= DEBUG_LEVEL_INFO)
  1363. printk( "%s(%d):mgslpc_write(%s) returning=%d\n",
  1364. __FILE__,__LINE__,info->device_name,ret);
  1365. return ret;
  1366. }
  1367. /* Return the count of free bytes in transmit buffer
  1368. */
  1369. static int mgslpc_write_room(struct tty_struct *tty)
  1370. {
  1371. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1372. int ret;
  1373. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write_room"))
  1374. return 0;
  1375. if (info->params.mode == MGSL_MODE_HDLC) {
  1376. /* HDLC (frame oriented) mode */
  1377. if (info->tx_active)
  1378. return 0;
  1379. else
  1380. return HDLC_MAX_FRAME_SIZE;
  1381. } else {
  1382. ret = TXBUFSIZE - info->tx_count - 1;
  1383. if (ret < 0)
  1384. ret = 0;
  1385. }
  1386. if (debug_level >= DEBUG_LEVEL_INFO)
  1387. printk("%s(%d):mgslpc_write_room(%s)=%d\n",
  1388. __FILE__,__LINE__, info->device_name, ret);
  1389. return ret;
  1390. }
  1391. /* Return the count of bytes in transmit buffer
  1392. */
  1393. static int mgslpc_chars_in_buffer(struct tty_struct *tty)
  1394. {
  1395. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1396. int rc;
  1397. if (debug_level >= DEBUG_LEVEL_INFO)
  1398. printk("%s(%d):mgslpc_chars_in_buffer(%s)\n",
  1399. __FILE__,__LINE__, info->device_name );
  1400. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_chars_in_buffer"))
  1401. return 0;
  1402. if (info->params.mode == MGSL_MODE_HDLC)
  1403. rc = info->tx_active ? info->max_frame_size : 0;
  1404. else
  1405. rc = info->tx_count;
  1406. if (debug_level >= DEBUG_LEVEL_INFO)
  1407. printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n",
  1408. __FILE__,__LINE__, info->device_name, rc);
  1409. return rc;
  1410. }
  1411. /* Discard all data in the send buffer
  1412. */
  1413. static void mgslpc_flush_buffer(struct tty_struct *tty)
  1414. {
  1415. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1416. unsigned long flags;
  1417. if (debug_level >= DEBUG_LEVEL_INFO)
  1418. printk("%s(%d):mgslpc_flush_buffer(%s) entry\n",
  1419. __FILE__,__LINE__, info->device_name );
  1420. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_buffer"))
  1421. return;
  1422. spin_lock_irqsave(&info->lock,flags);
  1423. info->tx_count = info->tx_put = info->tx_get = 0;
  1424. del_timer(&info->tx_timer);
  1425. spin_unlock_irqrestore(&info->lock,flags);
  1426. wake_up_interruptible(&tty->write_wait);
  1427. tty_wakeup(tty);
  1428. }
  1429. /* Send a high-priority XON/XOFF character
  1430. */
  1431. static void mgslpc_send_xchar(struct tty_struct *tty, char ch)
  1432. {
  1433. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1434. unsigned long flags;
  1435. if (debug_level >= DEBUG_LEVEL_INFO)
  1436. printk("%s(%d):mgslpc_send_xchar(%s,%d)\n",
  1437. __FILE__,__LINE__, info->device_name, ch );
  1438. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_send_xchar"))
  1439. return;
  1440. info->x_char = ch;
  1441. if (ch) {
  1442. spin_lock_irqsave(&info->lock,flags);
  1443. if (!info->tx_enabled)
  1444. tx_start(info, tty);
  1445. spin_unlock_irqrestore(&info->lock,flags);
  1446. }
  1447. }
  1448. /* Signal remote device to throttle send data (our receive data)
  1449. */
  1450. static void mgslpc_throttle(struct tty_struct * tty)
  1451. {
  1452. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1453. unsigned long flags;
  1454. if (debug_level >= DEBUG_LEVEL_INFO)
  1455. printk("%s(%d):mgslpc_throttle(%s) entry\n",
  1456. __FILE__,__LINE__, info->device_name );
  1457. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_throttle"))
  1458. return;
  1459. if (I_IXOFF(tty))
  1460. mgslpc_send_xchar(tty, STOP_CHAR(tty));
  1461. if (tty->termios->c_cflag & CRTSCTS) {
  1462. spin_lock_irqsave(&info->lock,flags);
  1463. info->serial_signals &= ~SerialSignal_RTS;
  1464. set_signals(info);
  1465. spin_unlock_irqrestore(&info->lock,flags);
  1466. }
  1467. }
  1468. /* Signal remote device to stop throttling send data (our receive data)
  1469. */
  1470. static void mgslpc_unthrottle(struct tty_struct * tty)
  1471. {
  1472. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1473. unsigned long flags;
  1474. if (debug_level >= DEBUG_LEVEL_INFO)
  1475. printk("%s(%d):mgslpc_unthrottle(%s) entry\n",
  1476. __FILE__,__LINE__, info->device_name );
  1477. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_unthrottle"))
  1478. return;
  1479. if (I_IXOFF(tty)) {
  1480. if (info->x_char)
  1481. info->x_char = 0;
  1482. else
  1483. mgslpc_send_xchar(tty, START_CHAR(tty));
  1484. }
  1485. if (tty->termios->c_cflag & CRTSCTS) {
  1486. spin_lock_irqsave(&info->lock,flags);
  1487. info->serial_signals |= SerialSignal_RTS;
  1488. set_signals(info);
  1489. spin_unlock_irqrestore(&info->lock,flags);
  1490. }
  1491. }
  1492. /* get the current serial statistics
  1493. */
  1494. static int get_stats(MGSLPC_INFO * info, struct mgsl_icount __user *user_icount)
  1495. {
  1496. int err;
  1497. if (debug_level >= DEBUG_LEVEL_INFO)
  1498. printk("get_params(%s)\n", info->device_name);
  1499. if (!user_icount) {
  1500. memset(&info->icount, 0, sizeof(info->icount));
  1501. } else {
  1502. COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
  1503. if (err)
  1504. return -EFAULT;
  1505. }
  1506. return 0;
  1507. }
  1508. /* get the current serial parameters
  1509. */
  1510. static int get_params(MGSLPC_INFO * info, MGSL_PARAMS __user *user_params)
  1511. {
  1512. int err;
  1513. if (debug_level >= DEBUG_LEVEL_INFO)
  1514. printk("get_params(%s)\n", info->device_name);
  1515. COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
  1516. if (err)
  1517. return -EFAULT;
  1518. return 0;
  1519. }
  1520. /* set the serial parameters
  1521. *
  1522. * Arguments:
  1523. *
  1524. * info pointer to device instance data
  1525. * new_params user buffer containing new serial params
  1526. *
  1527. * Returns: 0 if success, otherwise error code
  1528. */
  1529. static int set_params(MGSLPC_INFO * info, MGSL_PARAMS __user *new_params, struct tty_struct *tty)
  1530. {
  1531. unsigned long flags;
  1532. MGSL_PARAMS tmp_params;
  1533. int err;
  1534. if (debug_level >= DEBUG_LEVEL_INFO)
  1535. printk("%s(%d):set_params %s\n", __FILE__,__LINE__,
  1536. info->device_name );
  1537. COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
  1538. if (err) {
  1539. if ( debug_level >= DEBUG_LEVEL_INFO )
  1540. printk( "%s(%d):set_params(%s) user buffer copy failed\n",
  1541. __FILE__,__LINE__,info->device_name);
  1542. return -EFAULT;
  1543. }
  1544. spin_lock_irqsave(&info->lock,flags);
  1545. memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
  1546. spin_unlock_irqrestore(&info->lock,flags);
  1547. mgslpc_change_params(info, tty);
  1548. return 0;
  1549. }
  1550. static int get_txidle(MGSLPC_INFO * info, int __user *idle_mode)
  1551. {
  1552. int err;
  1553. if (debug_level >= DEBUG_LEVEL_INFO)
  1554. printk("get_txidle(%s)=%d\n", info->device_name, info->idle_mode);
  1555. COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
  1556. if (err)
  1557. return -EFAULT;
  1558. return 0;
  1559. }
  1560. static int set_txidle(MGSLPC_INFO * info, int idle_mode)
  1561. {
  1562. unsigned long flags;
  1563. if (debug_level >= DEBUG_LEVEL_INFO)
  1564. printk("set_txidle(%s,%d)\n", info->device_name, idle_mode);
  1565. spin_lock_irqsave(&info->lock,flags);
  1566. info->idle_mode = idle_mode;
  1567. tx_set_idle(info);
  1568. spin_unlock_irqrestore(&info->lock,flags);
  1569. return 0;
  1570. }
  1571. static int get_interface(MGSLPC_INFO * info, int __user *if_mode)
  1572. {
  1573. int err;
  1574. if (debug_level >= DEBUG_LEVEL_INFO)
  1575. printk("get_interface(%s)=%d\n", info->device_name, info->if_mode);
  1576. COPY_TO_USER(err,if_mode, &info->if_mode, sizeof(int));
  1577. if (err)
  1578. return -EFAULT;
  1579. return 0;
  1580. }
  1581. static int set_interface(MGSLPC_INFO * info, int if_mode)
  1582. {
  1583. unsigned long flags;
  1584. unsigned char val;
  1585. if (debug_level >= DEBUG_LEVEL_INFO)
  1586. printk("set_interface(%s,%d)\n", info->device_name, if_mode);
  1587. spin_lock_irqsave(&info->lock,flags);
  1588. info->if_mode = if_mode;
  1589. val = read_reg(info, PVR) & 0x0f;
  1590. switch (info->if_mode)
  1591. {
  1592. case MGSL_INTERFACE_RS232: val |= PVR_RS232; break;
  1593. case MGSL_INTERFACE_V35: val |= PVR_V35; break;
  1594. case MGSL_INTERFACE_RS422: val |= PVR_RS422; break;
  1595. }
  1596. write_reg(info, PVR, val);
  1597. spin_unlock_irqrestore(&info->lock,flags);
  1598. return 0;
  1599. }
  1600. static int set_txenable(MGSLPC_INFO * info, int enable, struct tty_struct *tty)
  1601. {
  1602. unsigned long flags;
  1603. if (debug_level >= DEBUG_LEVEL_INFO)
  1604. printk("set_txenable(%s,%d)\n", info->device_name, enable);
  1605. spin_lock_irqsave(&info->lock,flags);
  1606. if (enable) {
  1607. if (!info->tx_enabled)
  1608. tx_start(info, tty);
  1609. } else {
  1610. if (info->tx_enabled)
  1611. tx_stop(info);
  1612. }
  1613. spin_unlock_irqrestore(&info->lock,flags);
  1614. return 0;
  1615. }
  1616. static int tx_abort(MGSLPC_INFO * info)
  1617. {
  1618. unsigned long flags;
  1619. if (debug_level >= DEBUG_LEVEL_INFO)
  1620. printk("tx_abort(%s)\n", info->device_name);
  1621. spin_lock_irqsave(&info->lock,flags);
  1622. if (info->tx_active && info->tx_count &&
  1623. info->params.mode == MGSL_MODE_HDLC) {
  1624. /* clear data count so FIFO is not filled on next IRQ.
  1625. * This results in underrun and abort transmission.
  1626. */
  1627. info->tx_count = info->tx_put = info->tx_get = 0;
  1628. info->tx_aborting = true;
  1629. }
  1630. spin_unlock_irqrestore(&info->lock,flags);
  1631. return 0;
  1632. }
  1633. static int set_rxenable(MGSLPC_INFO * info, int enable)
  1634. {
  1635. unsigned long flags;
  1636. if (debug_level >= DEBUG_LEVEL_INFO)
  1637. printk("set_rxenable(%s,%d)\n", info->device_name, enable);
  1638. spin_lock_irqsave(&info->lock,flags);
  1639. if (enable) {
  1640. if (!info->rx_enabled)
  1641. rx_start(info);
  1642. } else {
  1643. if (info->rx_enabled)
  1644. rx_stop(info);
  1645. }
  1646. spin_unlock_irqrestore(&info->lock,flags);
  1647. return 0;
  1648. }
  1649. /* wait for specified event to occur
  1650. *
  1651. * Arguments: info pointer to device instance data
  1652. * mask pointer to bitmask of events to wait for
  1653. * Return Value: 0 if successful and bit mask updated with
  1654. * of events triggerred,
  1655. * otherwise error code
  1656. */
  1657. static int wait_events(MGSLPC_INFO * info, int __user *mask_ptr)
  1658. {
  1659. unsigned long flags;
  1660. int s;
  1661. int rc=0;
  1662. struct mgsl_icount cprev, cnow;
  1663. int events;
  1664. int mask;
  1665. struct _input_signal_events oldsigs, newsigs;
  1666. DECLARE_WAITQUEUE(wait, current);
  1667. COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
  1668. if (rc)
  1669. return -EFAULT;
  1670. if (debug_level >= DEBUG_LEVEL_INFO)
  1671. printk("wait_events(%s,%d)\n", info->device_name, mask);
  1672. spin_lock_irqsave(&info->lock,flags);
  1673. /* return immediately if state matches requested events */
  1674. get_signals(info);
  1675. s = info->serial_signals;
  1676. events = mask &
  1677. ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
  1678. ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
  1679. ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
  1680. ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
  1681. if (events) {
  1682. spin_unlock_irqrestore(&info->lock,flags);
  1683. goto exit;
  1684. }
  1685. /* save current irq counts */
  1686. cprev = info->icount;
  1687. oldsigs = info->input_signal_events;
  1688. if ((info->params.mode == MGSL_MODE_HDLC) &&
  1689. (mask & MgslEvent_ExitHuntMode))
  1690. irq_enable(info, CHA, IRQ_EXITHUNT);
  1691. set_current_state(TASK_INTERRUPTIBLE);
  1692. add_wait_queue(&info->event_wait_q, &wait);
  1693. spin_unlock_irqrestore(&info->lock,flags);
  1694. for(;;) {
  1695. schedule();
  1696. if (signal_pending(current)) {
  1697. rc = -ERESTARTSYS;
  1698. break;
  1699. }
  1700. /* get current irq counts */
  1701. spin_lock_irqsave(&info->lock,flags);
  1702. cnow = info->icount;
  1703. newsigs = info->input_signal_events;
  1704. set_current_state(TASK_INTERRUPTIBLE);
  1705. spin_unlock_irqrestore(&info->lock,flags);
  1706. /* if no change, wait aborted for some reason */
  1707. if (newsigs.dsr_up == oldsigs.dsr_up &&
  1708. newsigs.dsr_down == oldsigs.dsr_down &&
  1709. newsigs.dcd_up == oldsigs.dcd_up &&
  1710. newsigs.dcd_down == oldsigs.dcd_down &&
  1711. newsigs.cts_up == oldsigs.cts_up &&
  1712. newsigs.cts_down == oldsigs.cts_down &&
  1713. newsigs.ri_up == oldsigs.ri_up &&
  1714. newsigs.ri_down == oldsigs.ri_down &&
  1715. cnow.exithunt == cprev.exithunt &&
  1716. cnow.rxidle == cprev.rxidle) {
  1717. rc = -EIO;
  1718. break;
  1719. }
  1720. events = mask &
  1721. ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
  1722. (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
  1723. (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
  1724. (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
  1725. (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
  1726. (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
  1727. (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
  1728. (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
  1729. (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
  1730. (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
  1731. if (events)
  1732. break;
  1733. cprev = cnow;
  1734. oldsigs = newsigs;
  1735. }
  1736. remove_wait_queue(&info->event_wait_q, &wait);
  1737. set_current_state(TASK_RUNNING);
  1738. if (mask & MgslEvent_ExitHuntMode) {
  1739. spin_lock_irqsave(&info->lock,flags);
  1740. if (!waitqueue_active(&info->event_wait_q))
  1741. irq_disable(info, CHA, IRQ_EXITHUNT);
  1742. spin_unlock_irqrestore(&info->lock,flags);
  1743. }
  1744. exit:
  1745. if (rc == 0)
  1746. PUT_USER(rc, events, mask_ptr);
  1747. return rc;
  1748. }
  1749. static int modem_input_wait(MGSLPC_INFO *info,int arg)
  1750. {
  1751. unsigned long flags;
  1752. int rc;
  1753. struct mgsl_icount cprev, cnow;
  1754. DECLARE_WAITQUEUE(wait, current);
  1755. /* save current irq counts */
  1756. spin_lock_irqsave(&info->lock,flags);
  1757. cprev = info->icount;
  1758. add_wait_queue(&info->status_event_wait_q, &wait);
  1759. set_current_state(TASK_INTERRUPTIBLE);
  1760. spin_unlock_irqrestore(&info->lock,flags);
  1761. for(;;) {
  1762. schedule();
  1763. if (signal_pending(current)) {
  1764. rc = -ERESTARTSYS;
  1765. break;
  1766. }
  1767. /* get new irq counts */
  1768. spin_lock_irqsave(&info->lock,flags);
  1769. cnow = info->icount;
  1770. set_current_state(TASK_INTERRUPTIBLE);
  1771. spin_unlock_irqrestore(&info->lock,flags);
  1772. /* if no change, wait aborted for some reason */
  1773. if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
  1774. cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
  1775. rc = -EIO;
  1776. break;
  1777. }
  1778. /* check for change in caller specified modem input */
  1779. if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
  1780. (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
  1781. (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
  1782. (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
  1783. rc = 0;
  1784. break;
  1785. }
  1786. cprev = cnow;
  1787. }
  1788. remove_wait_queue(&info->status_event_wait_q, &wait);
  1789. set_current_state(TASK_RUNNING);
  1790. return rc;
  1791. }
  1792. /* return the state of the serial control and status signals
  1793. */
  1794. static int tiocmget(struct tty_struct *tty, struct file *file)
  1795. {
  1796. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1797. unsigned int result;
  1798. unsigned long flags;
  1799. spin_lock_irqsave(&info->lock,flags);
  1800. get_signals(info);
  1801. spin_unlock_irqrestore(&info->lock,flags);
  1802. result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
  1803. ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
  1804. ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
  1805. ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
  1806. ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
  1807. ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
  1808. if (debug_level >= DEBUG_LEVEL_INFO)
  1809. printk("%s(%d):%s tiocmget() value=%08X\n",
  1810. __FILE__,__LINE__, info->device_name, result );
  1811. return result;
  1812. }
  1813. /* set modem control signals (DTR/RTS)
  1814. */
  1815. static int tiocmset(struct tty_struct *tty, struct file *file,
  1816. unsigned int set, unsigned int clear)
  1817. {
  1818. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1819. unsigned long flags;
  1820. if (debug_level >= DEBUG_LEVEL_INFO)
  1821. printk("%s(%d):%s tiocmset(%x,%x)\n",
  1822. __FILE__,__LINE__,info->device_name, set, clear);
  1823. if (set & TIOCM_RTS)
  1824. info->serial_signals |= SerialSignal_RTS;
  1825. if (set & TIOCM_DTR)
  1826. info->serial_signals |= SerialSignal_DTR;
  1827. if (clear & TIOCM_RTS)
  1828. info->serial_signals &= ~SerialSignal_RTS;
  1829. if (clear & TIOCM_DTR)
  1830. info->serial_signals &= ~SerialSignal_DTR;
  1831. spin_lock_irqsave(&info->lock,flags);
  1832. set_signals(info);
  1833. spin_unlock_irqrestore(&info->lock,flags);
  1834. return 0;
  1835. }
  1836. /* Set or clear transmit break condition
  1837. *
  1838. * Arguments: tty pointer to tty instance data
  1839. * break_state -1=set break condition, 0=clear
  1840. */
  1841. static int mgslpc_break(struct tty_struct *tty, int break_state)
  1842. {
  1843. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1844. unsigned long flags;
  1845. if (debug_level >= DEBUG_LEVEL_INFO)
  1846. printk("%s(%d):mgslpc_break(%s,%d)\n",
  1847. __FILE__,__LINE__, info->device_name, break_state);
  1848. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_break"))
  1849. return -EINVAL;
  1850. spin_lock_irqsave(&info->lock,flags);
  1851. if (break_state == -1)
  1852. set_reg_bits(info, CHA+DAFO, BIT6);
  1853. else
  1854. clear_reg_bits(info, CHA+DAFO, BIT6);
  1855. spin_unlock_irqrestore(&info->lock,flags);
  1856. return 0;
  1857. }
  1858. /* Service an IOCTL request
  1859. *
  1860. * Arguments:
  1861. *
  1862. * tty pointer to tty instance data
  1863. * file pointer to associated file object for device
  1864. * cmd IOCTL command code
  1865. * arg command argument/context
  1866. *
  1867. * Return Value: 0 if success, otherwise error code
  1868. */
  1869. static int mgslpc_ioctl(struct tty_struct *tty, struct file * file,
  1870. unsigned int cmd, unsigned long arg)
  1871. {
  1872. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1873. int error;
  1874. struct mgsl_icount cnow; /* kernel counter temps */
  1875. struct serial_icounter_struct __user *p_cuser; /* user space */
  1876. void __user *argp = (void __user *)arg;
  1877. unsigned long flags;
  1878. if (debug_level >= DEBUG_LEVEL_INFO)
  1879. printk("%s(%d):mgslpc_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
  1880. info->device_name, cmd );
  1881. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_ioctl"))
  1882. return -ENODEV;
  1883. if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
  1884. (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
  1885. if (tty->flags & (1 << TTY_IO_ERROR))
  1886. return -EIO;
  1887. }
  1888. switch (cmd) {
  1889. case MGSL_IOCGPARAMS:
  1890. return get_params(info, argp);
  1891. case MGSL_IOCSPARAMS:
  1892. return set_params(info, argp, tty);
  1893. case MGSL_IOCGTXIDLE:
  1894. return get_txidle(info, argp);
  1895. case MGSL_IOCSTXIDLE:
  1896. return set_txidle(info, (int)arg);
  1897. case MGSL_IOCGIF:
  1898. return get_interface(info, argp);
  1899. case MGSL_IOCSIF:
  1900. return set_interface(info,(int)arg);
  1901. case MGSL_IOCTXENABLE:
  1902. return set_txenable(info,(int)arg, tty);
  1903. case MGSL_IOCRXENABLE:
  1904. return set_rxenable(info,(int)arg);
  1905. case MGSL_IOCTXABORT:
  1906. return tx_abort(info);
  1907. case MGSL_IOCGSTATS:
  1908. return get_stats(info, argp);
  1909. case MGSL_IOCWAITEVENT:
  1910. return wait_events(info, argp);
  1911. case TIOCMIWAIT:
  1912. return modem_input_wait(info,(int)arg);
  1913. case TIOCGICOUNT:
  1914. spin_lock_irqsave(&info->lock,flags);
  1915. cnow = info->icount;
  1916. spin_unlock_irqrestore(&info->lock,flags);
  1917. p_cuser = argp;
  1918. PUT_USER(error,cnow.cts, &p_cuser->cts);
  1919. if (error) return error;
  1920. PUT_USER(error,cnow.dsr, &p_cuser->dsr);
  1921. if (error) return error;
  1922. PUT_USER(error,cnow.rng, &p_cuser->rng);
  1923. if (error) return error;
  1924. PUT_USER(error,cnow.dcd, &p_cuser->dcd);
  1925. if (error) return error;
  1926. PUT_USER(error,cnow.rx, &p_cuser->rx);
  1927. if (error) return error;
  1928. PUT_USER(error,cnow.tx, &p_cuser->tx);
  1929. if (error) return error;
  1930. PUT_USER(error,cnow.frame, &p_cuser->frame);
  1931. if (error) return error;
  1932. PUT_USER(error,cnow.overrun, &p_cuser->overrun);
  1933. if (error) return error;
  1934. PUT_USER(error,cnow.parity, &p_cuser->parity);
  1935. if (error) return error;
  1936. PUT_USER(error,cnow.brk, &p_cuser->brk);
  1937. if (error) return error;
  1938. PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
  1939. if (error) return error;
  1940. return 0;
  1941. default:
  1942. return -ENOIOCTLCMD;
  1943. }
  1944. return 0;
  1945. }
  1946. /* Set new termios settings
  1947. *
  1948. * Arguments:
  1949. *
  1950. * tty pointer to tty structure
  1951. * termios pointer to buffer to hold returned old termios
  1952. */
  1953. static void mgslpc_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
  1954. {
  1955. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1956. unsigned long flags;
  1957. if (debug_level >= DEBUG_LEVEL_INFO)
  1958. printk("%s(%d):mgslpc_set_termios %s\n", __FILE__,__LINE__,
  1959. tty->driver->name );
  1960. /* just return if nothing has changed */
  1961. if ((tty->termios->c_cflag == old_termios->c_cflag)
  1962. && (RELEVANT_IFLAG(tty->termios->c_iflag)
  1963. == RELEVANT_IFLAG(old_termios->c_iflag)))
  1964. return;
  1965. mgslpc_change_params(info, tty);
  1966. /* Handle transition to B0 status */
  1967. if (old_termios->c_cflag & CBAUD &&
  1968. !(tty->termios->c_cflag & CBAUD)) {
  1969. info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  1970. spin_lock_irqsave(&info->lock,flags);
  1971. set_signals(info);
  1972. spin_unlock_irqrestore(&info->lock,flags);
  1973. }
  1974. /* Handle transition away from B0 status */
  1975. if (!(old_termios->c_cflag & CBAUD) &&
  1976. tty->termios->c_cflag & CBAUD) {
  1977. info->serial_signals |= SerialSignal_DTR;
  1978. if (!(tty->termios->c_cflag & CRTSCTS) ||
  1979. !test_bit(TTY_THROTTLED, &tty->flags)) {
  1980. info->serial_signals |= SerialSignal_RTS;
  1981. }
  1982. spin_lock_irqsave(&info->lock,flags);
  1983. set_signals(info);
  1984. spin_unlock_irqrestore(&info->lock,flags);
  1985. }
  1986. /* Handle turning off CRTSCTS */
  1987. if (old_termios->c_cflag & CRTSCTS &&
  1988. !(tty->termios->c_cflag & CRTSCTS)) {
  1989. tty->hw_stopped = 0;
  1990. tx_release(tty);
  1991. }
  1992. }
  1993. static void mgslpc_close(struct tty_struct *tty, struct file * filp)
  1994. {
  1995. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1996. struct tty_port *port = &info->port;
  1997. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_close"))
  1998. return;
  1999. if (debug_level >= DEBUG_LEVEL_INFO)
  2000. printk("%s(%d):mgslpc_close(%s) entry, count=%d\n",
  2001. __FILE__,__LINE__, info->device_name, port->count);
  2002. WARN_ON(!port->count);
  2003. if (tty_port_close_start(port, tty, filp) == 0)
  2004. goto cleanup;
  2005. if (port->flags & ASYNC_INITIALIZED)
  2006. mgslpc_wait_until_sent(tty, info->timeout);
  2007. mgslpc_flush_buffer(tty);
  2008. tty_ldisc_flush(tty);
  2009. shutdown(info, tty);
  2010. tty_port_close_end(port, tty);
  2011. tty_port_tty_set(port, NULL);
  2012. cleanup:
  2013. if (debug_level >= DEBUG_LEVEL_INFO)
  2014. printk("%s(%d):mgslpc_close(%s) exit, count=%d\n", __FILE__,__LINE__,
  2015. tty->driver->name, port->count);
  2016. }
  2017. /* Wait until the transmitter is empty.
  2018. */
  2019. static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout)
  2020. {
  2021. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  2022. unsigned long orig_jiffies, char_time;
  2023. if (!info )
  2024. return;
  2025. if (debug_level >= DEBUG_LEVEL_INFO)
  2026. printk("%s(%d):mgslpc_wait_until_sent(%s) entry\n",
  2027. __FILE__,__LINE__, info->device_name );
  2028. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_wait_until_sent"))
  2029. return;
  2030. if (!(info->port.flags & ASYNC_INITIALIZED))
  2031. goto exit;
  2032. orig_jiffies = jiffies;
  2033. /* Set check interval to 1/5 of estimated time to
  2034. * send a character, and make it at least 1. The check
  2035. * interval should also be less than the timeout.
  2036. * Note: use tight timings here to satisfy the NIST-PCTS.
  2037. */
  2038. if ( info->params.data_rate ) {
  2039. char_time = info->timeout/(32 * 5);
  2040. if (!char_time)
  2041. char_time++;
  2042. } else
  2043. char_time = 1;
  2044. if (timeout)
  2045. char_time = min_t(unsigned long, char_time, timeout);
  2046. if (info->params.mode == MGSL_MODE_HDLC) {
  2047. while (info->tx_active) {
  2048. msleep_interruptible(jiffies_to_msecs(char_time));
  2049. if (signal_pending(current))
  2050. break;
  2051. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2052. break;
  2053. }
  2054. } else {
  2055. while ((info->tx_count || info->tx_active) &&
  2056. info->tx_enabled) {
  2057. msleep_interruptible(jiffies_to_msecs(char_time));
  2058. if (signal_pending(current))
  2059. break;
  2060. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2061. break;
  2062. }
  2063. }
  2064. exit:
  2065. if (debug_level >= DEBUG_LEVEL_INFO)
  2066. printk("%s(%d):mgslpc_wait_until_sent(%s) exit\n",
  2067. __FILE__,__LINE__, info->device_name );
  2068. }
  2069. /* Called by tty_hangup() when a hangup is signaled.
  2070. * This is the same as closing all open files for the port.
  2071. */
  2072. static void mgslpc_hangup(struct tty_struct *tty)
  2073. {
  2074. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  2075. if (debug_level >= DEBUG_LEVEL_INFO)
  2076. printk("%s(%d):mgslpc_hangup(%s)\n",
  2077. __FILE__,__LINE__, info->device_name );
  2078. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_hangup"))
  2079. return;
  2080. mgslpc_flush_buffer(tty);
  2081. shutdown(info, tty);
  2082. tty_port_hangup(&info->port);
  2083. }
  2084. static int carrier_raised(struct tty_port *port)
  2085. {
  2086. MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
  2087. unsigned long flags;
  2088. spin_lock_irqsave(&info->lock,flags);
  2089. get_signals(info);
  2090. spin_unlock_irqrestore(&info->lock,flags);
  2091. if (info->serial_signals & SerialSignal_DCD)
  2092. return 1;
  2093. return 0;
  2094. }
  2095. static void dtr_rts(struct tty_port *port, int onoff)
  2096. {
  2097. MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
  2098. unsigned long flags;
  2099. spin_lock_irqsave(&info->lock,flags);
  2100. if (onoff)
  2101. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  2102. else
  2103. info->serial_signals &= ~SerialSignal_RTS + SerialSignal_DTR;
  2104. set_signals(info);
  2105. spin_unlock_irqrestore(&info->lock,flags);
  2106. }
  2107. static int mgslpc_open(struct tty_struct *tty, struct file * filp)
  2108. {
  2109. MGSLPC_INFO *info;
  2110. struct tty_port *port;
  2111. int retval, line;
  2112. unsigned long flags;
  2113. /* verify range of specified line number */
  2114. line = tty->index;
  2115. if ((line < 0) || (line >= mgslpc_device_count)) {
  2116. printk("%s(%d):mgslpc_open with invalid line #%d.\n",
  2117. __FILE__,__LINE__,line);
  2118. return -ENODEV;
  2119. }
  2120. /* find the info structure for the specified line */
  2121. info = mgslpc_device_list;
  2122. while(info && info->line != line)
  2123. info = info->next_device;
  2124. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_open"))
  2125. return -ENODEV;
  2126. port = &info->port;
  2127. tty->driver_data = info;
  2128. tty_port_tty_set(port, tty);
  2129. if (debug_level >= DEBUG_LEVEL_INFO)
  2130. printk("%s(%d):mgslpc_open(%s), old ref count = %d\n",
  2131. __FILE__,__LINE__,tty->driver->name, port->count);
  2132. /* If port is closing, signal caller to try again */
  2133. if (tty_hung_up_p(filp) || port->flags & ASYNC_CLOSING){
  2134. if (port->flags & ASYNC_CLOSING)
  2135. interruptible_sleep_on(&port->close_wait);
  2136. retval = ((port->flags & ASYNC_HUP_NOTIFY) ?
  2137. -EAGAIN : -ERESTARTSYS);
  2138. goto cleanup;
  2139. }
  2140. tty->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
  2141. spin_lock_irqsave(&info->netlock, flags);
  2142. if (info->netcount) {
  2143. retval = -EBUSY;
  2144. spin_unlock_irqrestore(&info->netlock, flags);
  2145. goto cleanup;
  2146. }
  2147. spin_lock(&port->lock);
  2148. port->count++;
  2149. spin_unlock(&port->lock);
  2150. spin_unlock_irqrestore(&info->netlock, flags);
  2151. if (port->count == 1) {
  2152. /* 1st open on this device, init hardware */
  2153. retval = startup(info, tty);
  2154. if (retval < 0)
  2155. goto cleanup;
  2156. }
  2157. retval = tty_port_block_til_ready(&info->port, tty, filp);
  2158. if (retval) {
  2159. if (debug_level >= DEBUG_LEVEL_INFO)
  2160. printk("%s(%d):block_til_ready(%s) returned %d\n",
  2161. __FILE__,__LINE__, info->device_name, retval);
  2162. goto cleanup;
  2163. }
  2164. if (debug_level >= DEBUG_LEVEL_INFO)
  2165. printk("%s(%d):mgslpc_open(%s) success\n",
  2166. __FILE__,__LINE__, info->device_name);
  2167. retval = 0;
  2168. cleanup:
  2169. return retval;
  2170. }
  2171. /*
  2172. * /proc fs routines....
  2173. */
  2174. static inline void line_info(struct seq_file *m, MGSLPC_INFO *info)
  2175. {
  2176. char stat_buf[30];
  2177. unsigned long flags;
  2178. seq_printf(m, "%s:io:%04X irq:%d",
  2179. info->device_name, info->io_base, info->irq_level);
  2180. /* output current serial signal states */
  2181. spin_lock_irqsave(&info->lock,flags);
  2182. get_signals(info);
  2183. spin_unlock_irqrestore(&info->lock,flags);
  2184. stat_buf[0] = 0;
  2185. stat_buf[1] = 0;
  2186. if (info->serial_signals & SerialSignal_RTS)
  2187. strcat(stat_buf, "|RTS");
  2188. if (info->serial_signals & SerialSignal_CTS)
  2189. strcat(stat_buf, "|CTS");
  2190. if (info->serial_signals & SerialSignal_DTR)
  2191. strcat(stat_buf, "|DTR");
  2192. if (info->serial_signals & SerialSignal_DSR)
  2193. strcat(stat_buf, "|DSR");
  2194. if (info->serial_signals & SerialSignal_DCD)
  2195. strcat(stat_buf, "|CD");
  2196. if (info->serial_signals & SerialSignal_RI)
  2197. strcat(stat_buf, "|RI");
  2198. if (info->params.mode == MGSL_MODE_HDLC) {
  2199. seq_printf(m, " HDLC txok:%d rxok:%d",
  2200. info->icount.txok, info->icount.rxok);
  2201. if (info->icount.txunder)
  2202. seq_printf(m, " txunder:%d", info->icount.txunder);
  2203. if (info->icount.txabort)
  2204. seq_printf(m, " txabort:%d", info->icount.txabort);
  2205. if (info->icount.rxshort)
  2206. seq_printf(m, " rxshort:%d", info->icount.rxshort);
  2207. if (info->icount.rxlong)
  2208. seq_printf(m, " rxlong:%d", info->icount.rxlong);
  2209. if (info->icount.rxover)
  2210. seq_printf(m, " rxover:%d", info->icount.rxover);
  2211. if (info->icount.rxcrc)
  2212. seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
  2213. } else {
  2214. seq_printf(m, " ASYNC tx:%d rx:%d",
  2215. info->icount.tx, info->icount.rx);
  2216. if (info->icount.frame)
  2217. seq_printf(m, " fe:%d", info->icount.frame);
  2218. if (info->icount.parity)
  2219. seq_printf(m, " pe:%d", info->icount.parity);
  2220. if (info->icount.brk)
  2221. seq_printf(m, " brk:%d", info->icount.brk);
  2222. if (info->icount.overrun)
  2223. seq_printf(m, " oe:%d", info->icount.overrun);
  2224. }
  2225. /* Append serial signal status to end */
  2226. seq_printf(m, " %s\n", stat_buf+1);
  2227. seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
  2228. info->tx_active,info->bh_requested,info->bh_running,
  2229. info->pending_bh);
  2230. }
  2231. /* Called to print information about devices
  2232. */
  2233. static int mgslpc_proc_show(struct seq_file *m, void *v)
  2234. {
  2235. MGSLPC_INFO *info;
  2236. seq_printf(m, "synclink driver:%s\n", driver_version);
  2237. info = mgslpc_device_list;
  2238. while( info ) {
  2239. line_info(m, info);
  2240. info = info->next_device;
  2241. }
  2242. return 0;
  2243. }
  2244. static int mgslpc_proc_open(struct inode *inode, struct file *file)
  2245. {
  2246. return single_open(file, mgslpc_proc_show, NULL);
  2247. }
  2248. static const struct file_operations mgslpc_proc_fops = {
  2249. .owner = THIS_MODULE,
  2250. .open = mgslpc_proc_open,
  2251. .read = seq_read,
  2252. .llseek = seq_lseek,
  2253. .release = single_release,
  2254. };
  2255. static int rx_alloc_buffers(MGSLPC_INFO *info)
  2256. {
  2257. /* each buffer has header and data */
  2258. info->rx_buf_size = sizeof(RXBUF) + info->max_frame_size;
  2259. /* calculate total allocation size for 8 buffers */
  2260. info->rx_buf_total_size = info->rx_buf_size * 8;
  2261. /* limit total allocated memory */
  2262. if (info->rx_buf_total_size > 0x10000)
  2263. info->rx_buf_total_size = 0x10000;
  2264. /* calculate number of buffers */
  2265. info->rx_buf_count = info->rx_buf_total_size / info->rx_buf_size;
  2266. info->rx_buf = kmalloc(info->rx_buf_total_size, GFP_KERNEL);
  2267. if (info->rx_buf == NULL)
  2268. return -ENOMEM;
  2269. rx_reset_buffers(info);
  2270. return 0;
  2271. }
  2272. static void rx_free_buffers(MGSLPC_INFO *info)
  2273. {
  2274. kfree(info->rx_buf);
  2275. info->rx_buf = NULL;
  2276. }
  2277. static int claim_resources(MGSLPC_INFO *info)
  2278. {
  2279. if (rx_alloc_buffers(info) < 0 ) {
  2280. printk( "Cant allocate rx buffer %s\n", info->device_name);
  2281. release_resources(info);
  2282. return -ENODEV;
  2283. }
  2284. return 0;
  2285. }
  2286. static void release_resources(MGSLPC_INFO *info)
  2287. {
  2288. if (debug_level >= DEBUG_LEVEL_INFO)
  2289. printk("release_resources(%s)\n", info->device_name);
  2290. rx_free_buffers(info);
  2291. }
  2292. /* Add the specified device instance data structure to the
  2293. * global linked list of devices and increment the device count.
  2294. *
  2295. * Arguments: info pointer to device instance data
  2296. */
  2297. static void mgslpc_add_device(MGSLPC_INFO *info)
  2298. {
  2299. info->next_device = NULL;
  2300. info->line = mgslpc_device_count;
  2301. sprintf(info->device_name,"ttySLP%d",info->line);
  2302. if (info->line < MAX_DEVICE_COUNT) {
  2303. if (maxframe[info->line])
  2304. info->max_frame_size = maxframe[info->line];
  2305. }
  2306. mgslpc_device_count++;
  2307. if (!mgslpc_device_list)
  2308. mgslpc_device_list = info;
  2309. else {
  2310. MGSLPC_INFO *current_dev = mgslpc_device_list;
  2311. while( current_dev->next_device )
  2312. current_dev = current_dev->next_device;
  2313. current_dev->next_device = info;
  2314. }
  2315. if (info->max_frame_size < 4096)
  2316. info->max_frame_size = 4096;
  2317. else if (info->max_frame_size > 65535)
  2318. info->max_frame_size = 65535;
  2319. printk( "SyncLink PC Card %s:IO=%04X IRQ=%d\n",
  2320. info->device_name, info->io_base, info->irq_level);
  2321. #if SYNCLINK_GENERIC_HDLC
  2322. hdlcdev_init(info);
  2323. #endif
  2324. }
  2325. static void mgslpc_remove_device(MGSLPC_INFO *remove_info)
  2326. {
  2327. MGSLPC_INFO *info = mgslpc_device_list;
  2328. MGSLPC_INFO *last = NULL;
  2329. while(info) {
  2330. if (info == remove_info) {
  2331. if (last)
  2332. last->next_device = info->next_device;
  2333. else
  2334. mgslpc_device_list = info->next_device;
  2335. #if SYNCLINK_GENERIC_HDLC
  2336. hdlcdev_exit(info);
  2337. #endif
  2338. release_resources(info);
  2339. kfree(info);
  2340. mgslpc_device_count--;
  2341. return;
  2342. }
  2343. last = info;
  2344. info = info->next_device;
  2345. }
  2346. }
  2347. static struct pcmcia_device_id mgslpc_ids[] = {
  2348. PCMCIA_DEVICE_MANF_CARD(0x02c5, 0x0050),
  2349. PCMCIA_DEVICE_NULL
  2350. };
  2351. MODULE_DEVICE_TABLE(pcmcia, mgslpc_ids);
  2352. static struct pcmcia_driver mgslpc_driver = {
  2353. .owner = THIS_MODULE,
  2354. .drv = {
  2355. .name = "synclink_cs",
  2356. },
  2357. .probe = mgslpc_probe,
  2358. .remove = mgslpc_detach,
  2359. .id_table = mgslpc_ids,
  2360. .suspend = mgslpc_suspend,
  2361. .resume = mgslpc_resume,
  2362. };
  2363. static const struct tty_operations mgslpc_ops = {
  2364. .open = mgslpc_open,
  2365. .close = mgslpc_close,
  2366. .write = mgslpc_write,
  2367. .put_char = mgslpc_put_char,
  2368. .flush_chars = mgslpc_flush_chars,
  2369. .write_room = mgslpc_write_room,
  2370. .chars_in_buffer = mgslpc_chars_in_buffer,
  2371. .flush_buffer = mgslpc_flush_buffer,
  2372. .ioctl = mgslpc_ioctl,
  2373. .throttle = mgslpc_throttle,
  2374. .unthrottle = mgslpc_unthrottle,
  2375. .send_xchar = mgslpc_send_xchar,
  2376. .break_ctl = mgslpc_break,
  2377. .wait_until_sent = mgslpc_wait_until_sent,
  2378. .set_termios = mgslpc_set_termios,
  2379. .stop = tx_pause,
  2380. .start = tx_release,
  2381. .hangup = mgslpc_hangup,
  2382. .tiocmget = tiocmget,
  2383. .tiocmset = tiocmset,
  2384. .proc_fops = &mgslpc_proc_fops,
  2385. };
  2386. static void synclink_cs_cleanup(void)
  2387. {
  2388. int rc;
  2389. printk("Unloading %s: version %s\n", driver_name, driver_version);
  2390. while(mgslpc_device_list)
  2391. mgslpc_remove_device(mgslpc_device_list);
  2392. if (serial_driver) {
  2393. if ((rc = tty_unregister_driver(serial_driver)))
  2394. printk("%s(%d) failed to unregister tty driver err=%d\n",
  2395. __FILE__,__LINE__,rc);
  2396. put_tty_driver(serial_driver);
  2397. }
  2398. pcmcia_unregister_driver(&mgslpc_driver);
  2399. }
  2400. static int __init synclink_cs_init(void)
  2401. {
  2402. int rc;
  2403. if (break_on_load) {
  2404. mgslpc_get_text_ptr();
  2405. BREAKPOINT();
  2406. }
  2407. printk("%s %s\n", driver_name, driver_version);
  2408. if ((rc = pcmcia_register_driver(&mgslpc_driver)) < 0)
  2409. return rc;
  2410. serial_driver = alloc_tty_driver(MAX_DEVICE_COUNT);
  2411. if (!serial_driver) {
  2412. rc = -ENOMEM;
  2413. goto error;
  2414. }
  2415. /* Initialize the tty_driver structure */
  2416. serial_driver->owner = THIS_MODULE;
  2417. serial_driver->driver_name = "synclink_cs";
  2418. serial_driver->name = "ttySLP";
  2419. serial_driver->major = ttymajor;
  2420. serial_driver->minor_start = 64;
  2421. serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
  2422. serial_driver->subtype = SERIAL_TYPE_NORMAL;
  2423. serial_driver->init_termios = tty_std_termios;
  2424. serial_driver->init_termios.c_cflag =
  2425. B9600 | CS8 | CREAD | HUPCL | CLOCAL;
  2426. serial_driver->flags = TTY_DRIVER_REAL_RAW;
  2427. tty_set_operations(serial_driver, &mgslpc_ops);
  2428. if ((rc = tty_register_driver(serial_driver)) < 0) {
  2429. printk("%s(%d):Couldn't register serial driver\n",
  2430. __FILE__,__LINE__);
  2431. put_tty_driver(serial_driver);
  2432. serial_driver = NULL;
  2433. goto error;
  2434. }
  2435. printk("%s %s, tty major#%d\n",
  2436. driver_name, driver_version,
  2437. serial_driver->major);
  2438. return 0;
  2439. error:
  2440. synclink_cs_cleanup();
  2441. return rc;
  2442. }
  2443. static void __exit synclink_cs_exit(void)
  2444. {
  2445. synclink_cs_cleanup();
  2446. }
  2447. module_init(synclink_cs_init);
  2448. module_exit(synclink_cs_exit);
  2449. static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate)
  2450. {
  2451. unsigned int M, N;
  2452. unsigned char val;
  2453. /* note:standard BRG mode is broken in V3.2 chip
  2454. * so enhanced mode is always used
  2455. */
  2456. if (rate) {
  2457. N = 3686400 / rate;
  2458. if (!N)
  2459. N = 1;
  2460. N >>= 1;
  2461. for (M = 1; N > 64 && M < 16; M++)
  2462. N >>= 1;
  2463. N--;
  2464. /* BGR[5..0] = N
  2465. * BGR[9..6] = M
  2466. * BGR[7..0] contained in BGR register
  2467. * BGR[9..8] contained in CCR2[7..6]
  2468. * divisor = (N+1)*2^M
  2469. *
  2470. * Note: M *must* not be zero (causes asymetric duty cycle)
  2471. */
  2472. write_reg(info, (unsigned char) (channel + BGR),
  2473. (unsigned char) ((M << 6) + N));
  2474. val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;
  2475. val |= ((M << 4) & 0xc0);
  2476. write_reg(info, (unsigned char) (channel + CCR2), val);
  2477. }
  2478. }
  2479. /* Enabled the AUX clock output at the specified frequency.
  2480. */
  2481. static void enable_auxclk(MGSLPC_INFO *info)
  2482. {
  2483. unsigned char val;
  2484. /* MODE
  2485. *
  2486. * 07..06 MDS[1..0] 10 = transparent HDLC mode
  2487. * 05 ADM Address Mode, 0 = no addr recognition
  2488. * 04 TMD Timer Mode, 0 = external
  2489. * 03 RAC Receiver Active, 0 = inactive
  2490. * 02 RTS 0=RTS active during xmit, 1=RTS always active
  2491. * 01 TRS Timer Resolution, 1=512
  2492. * 00 TLP Test Loop, 0 = no loop
  2493. *
  2494. * 1000 0010
  2495. */
  2496. val = 0x82;
  2497. /* channel B RTS is used to enable AUXCLK driver on SP505 */
  2498. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2499. val |= BIT2;
  2500. write_reg(info, CHB + MODE, val);
  2501. /* CCR0
  2502. *
  2503. * 07 PU Power Up, 1=active, 0=power down
  2504. * 06 MCE Master Clock Enable, 1=enabled
  2505. * 05 Reserved, 0
  2506. * 04..02 SC[2..0] Encoding
  2507. * 01..00 SM[1..0] Serial Mode, 00=HDLC
  2508. *
  2509. * 11000000
  2510. */
  2511. write_reg(info, CHB + CCR0, 0xc0);
  2512. /* CCR1
  2513. *
  2514. * 07 SFLG Shared Flag, 0 = disable shared flags
  2515. * 06 GALP Go Active On Loop, 0 = not used
  2516. * 05 GLP Go On Loop, 0 = not used
  2517. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2518. * 03 ITF Interframe Time Fill, 0=mark, 1=flag
  2519. * 02..00 CM[2..0] Clock Mode
  2520. *
  2521. * 0001 0111
  2522. */
  2523. write_reg(info, CHB + CCR1, 0x17);
  2524. /* CCR2 (Channel B)
  2525. *
  2526. * 07..06 BGR[9..8] Baud rate bits 9..8
  2527. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2528. * 04 SSEL Clock source select, 1=submode b
  2529. * 03 TOE 0=TxCLK is input, 1=TxCLK is output
  2530. * 02 RWX Read/Write Exchange 0=disabled
  2531. * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
  2532. * 00 DIV, data inversion 0=disabled, 1=enabled
  2533. *
  2534. * 0011 1000
  2535. */
  2536. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2537. write_reg(info, CHB + CCR2, 0x38);
  2538. else
  2539. write_reg(info, CHB + CCR2, 0x30);
  2540. /* CCR4
  2541. *
  2542. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2543. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2544. * 05 TST1 Test Pin, 0=normal operation
  2545. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2546. * 03..02 Reserved, must be 0
  2547. * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
  2548. *
  2549. * 0101 0000
  2550. */
  2551. write_reg(info, CHB + CCR4, 0x50);
  2552. /* if auxclk not enabled, set internal BRG so
  2553. * CTS transitions can be detected (requires TxC)
  2554. */
  2555. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2556. mgslpc_set_rate(info, CHB, info->params.clock_speed);
  2557. else
  2558. mgslpc_set_rate(info, CHB, 921600);
  2559. }
  2560. static void loopback_enable(MGSLPC_INFO *info)
  2561. {
  2562. unsigned char val;
  2563. /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */
  2564. val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0);
  2565. write_reg(info, CHA + CCR1, val);
  2566. /* CCR2:04 SSEL Clock source select, 1=submode b */
  2567. val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5);
  2568. write_reg(info, CHA + CCR2, val);
  2569. /* set LinkSpeed if available, otherwise default to 2Mbps */
  2570. if (info->params.clock_speed)
  2571. mgslpc_set_rate(info, CHA, info->params.clock_speed);
  2572. else
  2573. mgslpc_set_rate(info, CHA, 1843200);
  2574. /* MODE:00 TLP Test Loop, 1=loopback enabled */
  2575. val = read_reg(info, CHA + MODE) | BIT0;
  2576. write_reg(info, CHA + MODE, val);
  2577. }
  2578. static void hdlc_mode(MGSLPC_INFO *info)
  2579. {
  2580. unsigned char val;
  2581. unsigned char clkmode, clksubmode;
  2582. /* disable all interrupts */
  2583. irq_disable(info, CHA, 0xffff);
  2584. irq_disable(info, CHB, 0xffff);
  2585. port_irq_disable(info, 0xff);
  2586. /* assume clock mode 0a, rcv=RxC xmt=TxC */
  2587. clkmode = clksubmode = 0;
  2588. if (info->params.flags & HDLC_FLAG_RXC_DPLL
  2589. && info->params.flags & HDLC_FLAG_TXC_DPLL) {
  2590. /* clock mode 7a, rcv = DPLL, xmt = DPLL */
  2591. clkmode = 7;
  2592. } else if (info->params.flags & HDLC_FLAG_RXC_BRG
  2593. && info->params.flags & HDLC_FLAG_TXC_BRG) {
  2594. /* clock mode 7b, rcv = BRG, xmt = BRG */
  2595. clkmode = 7;
  2596. clksubmode = 1;
  2597. } else if (info->params.flags & HDLC_FLAG_RXC_DPLL) {
  2598. if (info->params.flags & HDLC_FLAG_TXC_BRG) {
  2599. /* clock mode 6b, rcv = DPLL, xmt = BRG/16 */
  2600. clkmode = 6;
  2601. clksubmode = 1;
  2602. } else {
  2603. /* clock mode 6a, rcv = DPLL, xmt = TxC */
  2604. clkmode = 6;
  2605. }
  2606. } else if (info->params.flags & HDLC_FLAG_TXC_BRG) {
  2607. /* clock mode 0b, rcv = RxC, xmt = BRG */
  2608. clksubmode = 1;
  2609. }
  2610. /* MODE
  2611. *
  2612. * 07..06 MDS[1..0] 10 = transparent HDLC mode
  2613. * 05 ADM Address Mode, 0 = no addr recognition
  2614. * 04 TMD Timer Mode, 0 = external
  2615. * 03 RAC Receiver Active, 0 = inactive
  2616. * 02 RTS 0=RTS active during xmit, 1=RTS always active
  2617. * 01 TRS Timer Resolution, 1=512
  2618. * 00 TLP Test Loop, 0 = no loop
  2619. *
  2620. * 1000 0010
  2621. */
  2622. val = 0x82;
  2623. if (info->params.loopback)
  2624. val |= BIT0;
  2625. /* preserve RTS state */
  2626. if (info->serial_signals & SerialSignal_RTS)
  2627. val |= BIT2;
  2628. write_reg(info, CHA + MODE, val);
  2629. /* CCR0
  2630. *
  2631. * 07 PU Power Up, 1=active, 0=power down
  2632. * 06 MCE Master Clock Enable, 1=enabled
  2633. * 05 Reserved, 0
  2634. * 04..02 SC[2..0] Encoding
  2635. * 01..00 SM[1..0] Serial Mode, 00=HDLC
  2636. *
  2637. * 11000000
  2638. */
  2639. val = 0xc0;
  2640. switch (info->params.encoding)
  2641. {
  2642. case HDLC_ENCODING_NRZI:
  2643. val |= BIT3;
  2644. break;
  2645. case HDLC_ENCODING_BIPHASE_SPACE:
  2646. val |= BIT4;
  2647. break; // FM0
  2648. case HDLC_ENCODING_BIPHASE_MARK:
  2649. val |= BIT4 + BIT2;
  2650. break; // FM1
  2651. case HDLC_ENCODING_BIPHASE_LEVEL:
  2652. val |= BIT4 + BIT3;
  2653. break; // Manchester
  2654. }
  2655. write_reg(info, CHA + CCR0, val);
  2656. /* CCR1
  2657. *
  2658. * 07 SFLG Shared Flag, 0 = disable shared flags
  2659. * 06 GALP Go Active On Loop, 0 = not used
  2660. * 05 GLP Go On Loop, 0 = not used
  2661. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2662. * 03 ITF Interframe Time Fill, 0=mark, 1=flag
  2663. * 02..00 CM[2..0] Clock Mode
  2664. *
  2665. * 0001 0000
  2666. */
  2667. val = 0x10 + clkmode;
  2668. write_reg(info, CHA + CCR1, val);
  2669. /* CCR2
  2670. *
  2671. * 07..06 BGR[9..8] Baud rate bits 9..8
  2672. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2673. * 04 SSEL Clock source select, 1=submode b
  2674. * 03 TOE 0=TxCLK is input, 0=TxCLK is input
  2675. * 02 RWX Read/Write Exchange 0=disabled
  2676. * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
  2677. * 00 DIV, data inversion 0=disabled, 1=enabled
  2678. *
  2679. * 0000 0000
  2680. */
  2681. val = 0x00;
  2682. if (clkmode == 2 || clkmode == 3 || clkmode == 6
  2683. || clkmode == 7 || (clkmode == 0 && clksubmode == 1))
  2684. val |= BIT5;
  2685. if (clksubmode)
  2686. val |= BIT4;
  2687. if (info->params.crc_type == HDLC_CRC_32_CCITT)
  2688. val |= BIT1;
  2689. if (info->params.encoding == HDLC_ENCODING_NRZB)
  2690. val |= BIT0;
  2691. write_reg(info, CHA + CCR2, val);
  2692. /* CCR3
  2693. *
  2694. * 07..06 PRE[1..0] Preamble count 00=1, 01=2, 10=4, 11=8
  2695. * 05 EPT Enable preamble transmission, 1=enabled
  2696. * 04 RADD Receive address pushed to FIFO, 0=disabled
  2697. * 03 CRL CRC Reset Level, 0=FFFF
  2698. * 02 RCRC Rx CRC 0=On 1=Off
  2699. * 01 TCRC Tx CRC 0=On 1=Off
  2700. * 00 PSD DPLL Phase Shift Disable
  2701. *
  2702. * 0000 0000
  2703. */
  2704. val = 0x00;
  2705. if (info->params.crc_type == HDLC_CRC_NONE)
  2706. val |= BIT2 + BIT1;
  2707. if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
  2708. val |= BIT5;
  2709. switch (info->params.preamble_length)
  2710. {
  2711. case HDLC_PREAMBLE_LENGTH_16BITS:
  2712. val |= BIT6;
  2713. break;
  2714. case HDLC_PREAMBLE_LENGTH_32BITS:
  2715. val |= BIT6;
  2716. break;
  2717. case HDLC_PREAMBLE_LENGTH_64BITS:
  2718. val |= BIT7 + BIT6;
  2719. break;
  2720. }
  2721. write_reg(info, CHA + CCR3, val);
  2722. /* PRE - Preamble pattern */
  2723. val = 0;
  2724. switch (info->params.preamble)
  2725. {
  2726. case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
  2727. case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break;
  2728. case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break;
  2729. case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
  2730. }
  2731. write_reg(info, CHA + PRE, val);
  2732. /* CCR4
  2733. *
  2734. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2735. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2736. * 05 TST1 Test Pin, 0=normal operation
  2737. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2738. * 03..02 Reserved, must be 0
  2739. * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
  2740. *
  2741. * 0101 0000
  2742. */
  2743. val = 0x50;
  2744. write_reg(info, CHA + CCR4, val);
  2745. if (info->params.flags & HDLC_FLAG_RXC_DPLL)
  2746. mgslpc_set_rate(info, CHA, info->params.clock_speed * 16);
  2747. else
  2748. mgslpc_set_rate(info, CHA, info->params.clock_speed);
  2749. /* RLCR Receive length check register
  2750. *
  2751. * 7 1=enable receive length check
  2752. * 6..0 Max frame length = (RL + 1) * 32
  2753. */
  2754. write_reg(info, CHA + RLCR, 0);
  2755. /* XBCH Transmit Byte Count High
  2756. *
  2757. * 07 DMA mode, 0 = interrupt driven
  2758. * 06 NRM, 0=ABM (ignored)
  2759. * 05 CAS Carrier Auto Start
  2760. * 04 XC Transmit Continuously (ignored)
  2761. * 03..00 XBC[10..8] Transmit byte count bits 10..8
  2762. *
  2763. * 0000 0000
  2764. */
  2765. val = 0x00;
  2766. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  2767. val |= BIT5;
  2768. write_reg(info, CHA + XBCH, val);
  2769. enable_auxclk(info);
  2770. if (info->params.loopback || info->testing_irq)
  2771. loopback_enable(info);
  2772. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  2773. {
  2774. irq_enable(info, CHB, IRQ_CTS);
  2775. /* PVR[3] 1=AUTO CTS active */
  2776. set_reg_bits(info, CHA + PVR, BIT3);
  2777. } else
  2778. clear_reg_bits(info, CHA + PVR, BIT3);
  2779. irq_enable(info, CHA,
  2780. IRQ_RXEOM + IRQ_RXFIFO + IRQ_ALLSENT +
  2781. IRQ_UNDERRUN + IRQ_TXFIFO);
  2782. issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
  2783. wait_command_complete(info, CHA);
  2784. read_reg16(info, CHA + ISR); /* clear pending IRQs */
  2785. /* Master clock mode enabled above to allow reset commands
  2786. * to complete even if no data clocks are present.
  2787. *
  2788. * Disable master clock mode for normal communications because
  2789. * V3.2 of the ESCC2 has a bug that prevents the transmit all sent
  2790. * IRQ when in master clock mode.
  2791. *
  2792. * Leave master clock mode enabled for IRQ test because the
  2793. * timer IRQ used by the test can only happen in master clock mode.
  2794. */
  2795. if (!info->testing_irq)
  2796. clear_reg_bits(info, CHA + CCR0, BIT6);
  2797. tx_set_idle(info);
  2798. tx_stop(info);
  2799. rx_stop(info);
  2800. }
  2801. static void rx_stop(MGSLPC_INFO *info)
  2802. {
  2803. if (debug_level >= DEBUG_LEVEL_ISR)
  2804. printk("%s(%d):rx_stop(%s)\n",
  2805. __FILE__,__LINE__, info->device_name );
  2806. /* MODE:03 RAC Receiver Active, 0=inactive */
  2807. clear_reg_bits(info, CHA + MODE, BIT3);
  2808. info->rx_enabled = false;
  2809. info->rx_overflow = false;
  2810. }
  2811. static void rx_start(MGSLPC_INFO *info)
  2812. {
  2813. if (debug_level >= DEBUG_LEVEL_ISR)
  2814. printk("%s(%d):rx_start(%s)\n",
  2815. __FILE__,__LINE__, info->device_name );
  2816. rx_reset_buffers(info);
  2817. info->rx_enabled = false;
  2818. info->rx_overflow = false;
  2819. /* MODE:03 RAC Receiver Active, 1=active */
  2820. set_reg_bits(info, CHA + MODE, BIT3);
  2821. info->rx_enabled = true;
  2822. }
  2823. static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty)
  2824. {
  2825. if (debug_level >= DEBUG_LEVEL_ISR)
  2826. printk("%s(%d):tx_start(%s)\n",
  2827. __FILE__,__LINE__, info->device_name );
  2828. if (info->tx_count) {
  2829. /* If auto RTS enabled and RTS is inactive, then assert */
  2830. /* RTS and set a flag indicating that the driver should */
  2831. /* negate RTS when the transmission completes. */
  2832. info->drop_rts_on_tx_done = false;
  2833. if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
  2834. get_signals(info);
  2835. if (!(info->serial_signals & SerialSignal_RTS)) {
  2836. info->serial_signals |= SerialSignal_RTS;
  2837. set_signals(info);
  2838. info->drop_rts_on_tx_done = true;
  2839. }
  2840. }
  2841. if (info->params.mode == MGSL_MODE_ASYNC) {
  2842. if (!info->tx_active) {
  2843. info->tx_active = true;
  2844. tx_ready(info, tty);
  2845. }
  2846. } else {
  2847. info->tx_active = true;
  2848. tx_ready(info, tty);
  2849. mod_timer(&info->tx_timer, jiffies +
  2850. msecs_to_jiffies(5000));
  2851. }
  2852. }
  2853. if (!info->tx_enabled)
  2854. info->tx_enabled = true;
  2855. }
  2856. static void tx_stop(MGSLPC_INFO *info)
  2857. {
  2858. if (debug_level >= DEBUG_LEVEL_ISR)
  2859. printk("%s(%d):tx_stop(%s)\n",
  2860. __FILE__,__LINE__, info->device_name );
  2861. del_timer(&info->tx_timer);
  2862. info->tx_enabled = false;
  2863. info->tx_active = false;
  2864. }
  2865. /* Reset the adapter to a known state and prepare it for further use.
  2866. */
  2867. static void reset_device(MGSLPC_INFO *info)
  2868. {
  2869. /* power up both channels (set BIT7) */
  2870. write_reg(info, CHA + CCR0, 0x80);
  2871. write_reg(info, CHB + CCR0, 0x80);
  2872. write_reg(info, CHA + MODE, 0);
  2873. write_reg(info, CHB + MODE, 0);
  2874. /* disable all interrupts */
  2875. irq_disable(info, CHA, 0xffff);
  2876. irq_disable(info, CHB, 0xffff);
  2877. port_irq_disable(info, 0xff);
  2878. /* PCR Port Configuration Register
  2879. *
  2880. * 07..04 DEC[3..0] Serial I/F select outputs
  2881. * 03 output, 1=AUTO CTS control enabled
  2882. * 02 RI Ring Indicator input 0=active
  2883. * 01 DSR input 0=active
  2884. * 00 DTR output 0=active
  2885. *
  2886. * 0000 0110
  2887. */
  2888. write_reg(info, PCR, 0x06);
  2889. /* PVR Port Value Register
  2890. *
  2891. * 07..04 DEC[3..0] Serial I/F select (0000=disabled)
  2892. * 03 AUTO CTS output 1=enabled
  2893. * 02 RI Ring Indicator input
  2894. * 01 DSR input
  2895. * 00 DTR output (1=inactive)
  2896. *
  2897. * 0000 0001
  2898. */
  2899. // write_reg(info, PVR, PVR_DTR);
  2900. /* IPC Interrupt Port Configuration
  2901. *
  2902. * 07 VIS 1=Masked interrupts visible
  2903. * 06..05 Reserved, 0
  2904. * 04..03 SLA Slave address, 00 ignored
  2905. * 02 CASM Cascading Mode, 1=daisy chain
  2906. * 01..00 IC[1..0] Interrupt Config, 01=push-pull output, active low
  2907. *
  2908. * 0000 0101
  2909. */
  2910. write_reg(info, IPC, 0x05);
  2911. }
  2912. static void async_mode(MGSLPC_INFO *info)
  2913. {
  2914. unsigned char val;
  2915. /* disable all interrupts */
  2916. irq_disable(info, CHA, 0xffff);
  2917. irq_disable(info, CHB, 0xffff);
  2918. port_irq_disable(info, 0xff);
  2919. /* MODE
  2920. *
  2921. * 07 Reserved, 0
  2922. * 06 FRTS RTS State, 0=active
  2923. * 05 FCTS Flow Control on CTS
  2924. * 04 FLON Flow Control Enable
  2925. * 03 RAC Receiver Active, 0 = inactive
  2926. * 02 RTS 0=Auto RTS, 1=manual RTS
  2927. * 01 TRS Timer Resolution, 1=512
  2928. * 00 TLP Test Loop, 0 = no loop
  2929. *
  2930. * 0000 0110
  2931. */
  2932. val = 0x06;
  2933. if (info->params.loopback)
  2934. val |= BIT0;
  2935. /* preserve RTS state */
  2936. if (!(info->serial_signals & SerialSignal_RTS))
  2937. val |= BIT6;
  2938. write_reg(info, CHA + MODE, val);
  2939. /* CCR0
  2940. *
  2941. * 07 PU Power Up, 1=active, 0=power down
  2942. * 06 MCE Master Clock Enable, 1=enabled
  2943. * 05 Reserved, 0
  2944. * 04..02 SC[2..0] Encoding, 000=NRZ
  2945. * 01..00 SM[1..0] Serial Mode, 11=Async
  2946. *
  2947. * 1000 0011
  2948. */
  2949. write_reg(info, CHA + CCR0, 0x83);
  2950. /* CCR1
  2951. *
  2952. * 07..05 Reserved, 0
  2953. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2954. * 03 BCR Bit Clock Rate, 1=16x
  2955. * 02..00 CM[2..0] Clock Mode, 111=BRG
  2956. *
  2957. * 0001 1111
  2958. */
  2959. write_reg(info, CHA + CCR1, 0x1f);
  2960. /* CCR2 (channel A)
  2961. *
  2962. * 07..06 BGR[9..8] Baud rate bits 9..8
  2963. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2964. * 04 SSEL Clock source select, 1=submode b
  2965. * 03 TOE 0=TxCLK is input, 0=TxCLK is input
  2966. * 02 RWX Read/Write Exchange 0=disabled
  2967. * 01 Reserved, 0
  2968. * 00 DIV, data inversion 0=disabled, 1=enabled
  2969. *
  2970. * 0001 0000
  2971. */
  2972. write_reg(info, CHA + CCR2, 0x10);
  2973. /* CCR3
  2974. *
  2975. * 07..01 Reserved, 0
  2976. * 00 PSD DPLL Phase Shift Disable
  2977. *
  2978. * 0000 0000
  2979. */
  2980. write_reg(info, CHA + CCR3, 0);
  2981. /* CCR4
  2982. *
  2983. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2984. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2985. * 05 TST1 Test Pin, 0=normal operation
  2986. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2987. * 03..00 Reserved, must be 0
  2988. *
  2989. * 0101 0000
  2990. */
  2991. write_reg(info, CHA + CCR4, 0x50);
  2992. mgslpc_set_rate(info, CHA, info->params.data_rate * 16);
  2993. /* DAFO Data Format
  2994. *
  2995. * 07 Reserved, 0
  2996. * 06 XBRK transmit break, 0=normal operation
  2997. * 05 Stop bits (0=1, 1=2)
  2998. * 04..03 PAR[1..0] Parity (01=odd, 10=even)
  2999. * 02 PAREN Parity Enable
  3000. * 01..00 CHL[1..0] Character Length (00=8, 01=7)
  3001. *
  3002. */
  3003. val = 0x00;
  3004. if (info->params.data_bits != 8)
  3005. val |= BIT0; /* 7 bits */
  3006. if (info->params.stop_bits != 1)
  3007. val |= BIT5;
  3008. if (info->params.parity != ASYNC_PARITY_NONE)
  3009. {
  3010. val |= BIT2; /* Parity enable */
  3011. if (info->params.parity == ASYNC_PARITY_ODD)
  3012. val |= BIT3;
  3013. else
  3014. val |= BIT4;
  3015. }
  3016. write_reg(info, CHA + DAFO, val);
  3017. /* RFC Rx FIFO Control
  3018. *
  3019. * 07 Reserved, 0
  3020. * 06 DPS, 1=parity bit not stored in data byte
  3021. * 05 DXS, 0=all data stored in FIFO (including XON/XOFF)
  3022. * 04 RFDF Rx FIFO Data Format, 1=status byte stored in FIFO
  3023. * 03..02 RFTH[1..0], rx threshold, 11=16 status + 16 data byte
  3024. * 01 Reserved, 0
  3025. * 00 TCDE Terminate Char Detect Enable, 0=disabled
  3026. *
  3027. * 0101 1100
  3028. */
  3029. write_reg(info, CHA + RFC, 0x5c);
  3030. /* RLCR Receive length check register
  3031. *
  3032. * Max frame length = (RL + 1) * 32
  3033. */
  3034. write_reg(info, CHA + RLCR, 0);
  3035. /* XBCH Transmit Byte Count High
  3036. *
  3037. * 07 DMA mode, 0 = interrupt driven
  3038. * 06 NRM, 0=ABM (ignored)
  3039. * 05 CAS Carrier Auto Start
  3040. * 04 XC Transmit Continuously (ignored)
  3041. * 03..00 XBC[10..8] Transmit byte count bits 10..8
  3042. *
  3043. * 0000 0000
  3044. */
  3045. val = 0x00;
  3046. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  3047. val |= BIT5;
  3048. write_reg(info, CHA + XBCH, val);
  3049. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  3050. irq_enable(info, CHA, IRQ_CTS);
  3051. /* MODE:03 RAC Receiver Active, 1=active */
  3052. set_reg_bits(info, CHA + MODE, BIT3);
  3053. enable_auxclk(info);
  3054. if (info->params.flags & HDLC_FLAG_AUTO_CTS) {
  3055. irq_enable(info, CHB, IRQ_CTS);
  3056. /* PVR[3] 1=AUTO CTS active */
  3057. set_reg_bits(info, CHA + PVR, BIT3);
  3058. } else
  3059. clear_reg_bits(info, CHA + PVR, BIT3);
  3060. irq_enable(info, CHA,
  3061. IRQ_RXEOM + IRQ_RXFIFO + IRQ_BREAK_ON + IRQ_RXTIME +
  3062. IRQ_ALLSENT + IRQ_TXFIFO);
  3063. issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
  3064. wait_command_complete(info, CHA);
  3065. read_reg16(info, CHA + ISR); /* clear pending IRQs */
  3066. }
  3067. /* Set the HDLC idle mode for the transmitter.
  3068. */
  3069. static void tx_set_idle(MGSLPC_INFO *info)
  3070. {
  3071. /* Note: ESCC2 only supports flags and one idle modes */
  3072. if (info->idle_mode == HDLC_TXIDLE_FLAGS)
  3073. set_reg_bits(info, CHA + CCR1, BIT3);
  3074. else
  3075. clear_reg_bits(info, CHA + CCR1, BIT3);
  3076. }
  3077. /* get state of the V24 status (input) signals.
  3078. */
  3079. static void get_signals(MGSLPC_INFO *info)
  3080. {
  3081. unsigned char status = 0;
  3082. /* preserve DTR and RTS */
  3083. info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
  3084. if (read_reg(info, CHB + VSTR) & BIT7)
  3085. info->serial_signals |= SerialSignal_DCD;
  3086. if (read_reg(info, CHB + STAR) & BIT1)
  3087. info->serial_signals |= SerialSignal_CTS;
  3088. status = read_reg(info, CHA + PVR);
  3089. if (!(status & PVR_RI))
  3090. info->serial_signals |= SerialSignal_RI;
  3091. if (!(status & PVR_DSR))
  3092. info->serial_signals |= SerialSignal_DSR;
  3093. }
  3094. /* Set the state of DTR and RTS based on contents of
  3095. * serial_signals member of device extension.
  3096. */
  3097. static void set_signals(MGSLPC_INFO *info)
  3098. {
  3099. unsigned char val;
  3100. val = read_reg(info, CHA + MODE);
  3101. if (info->params.mode == MGSL_MODE_ASYNC) {
  3102. if (info->serial_signals & SerialSignal_RTS)
  3103. val &= ~BIT6;
  3104. else
  3105. val |= BIT6;
  3106. } else {
  3107. if (info->serial_signals & SerialSignal_RTS)
  3108. val |= BIT2;
  3109. else
  3110. val &= ~BIT2;
  3111. }
  3112. write_reg(info, CHA + MODE, val);
  3113. if (info->serial_signals & SerialSignal_DTR)
  3114. clear_reg_bits(info, CHA + PVR, PVR_DTR);
  3115. else
  3116. set_reg_bits(info, CHA + PVR, PVR_DTR);
  3117. }
  3118. static void rx_reset_buffers(MGSLPC_INFO *info)
  3119. {
  3120. RXBUF *buf;
  3121. int i;
  3122. info->rx_put = 0;
  3123. info->rx_get = 0;
  3124. info->rx_frame_count = 0;
  3125. for (i=0 ; i < info->rx_buf_count ; i++) {
  3126. buf = (RXBUF*)(info->rx_buf + (i * info->rx_buf_size));
  3127. buf->status = buf->count = 0;
  3128. }
  3129. }
  3130. /* Attempt to return a received HDLC frame
  3131. * Only frames received without errors are returned.
  3132. *
  3133. * Returns true if frame returned, otherwise false
  3134. */
  3135. static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty)
  3136. {
  3137. unsigned short status;
  3138. RXBUF *buf;
  3139. unsigned int framesize = 0;
  3140. unsigned long flags;
  3141. bool return_frame = false;
  3142. if (info->rx_frame_count == 0)
  3143. return false;
  3144. buf = (RXBUF*)(info->rx_buf + (info->rx_get * info->rx_buf_size));
  3145. status = buf->status;
  3146. /* 07 VFR 1=valid frame
  3147. * 06 RDO 1=data overrun
  3148. * 05 CRC 1=OK, 0=error
  3149. * 04 RAB 1=frame aborted
  3150. */
  3151. if ((status & 0xf0) != 0xA0) {
  3152. if (!(status & BIT7) || (status & BIT4))
  3153. info->icount.rxabort++;
  3154. else if (status & BIT6)
  3155. info->icount.rxover++;
  3156. else if (!(status & BIT5)) {
  3157. info->icount.rxcrc++;
  3158. if (info->params.crc_type & HDLC_CRC_RETURN_EX)
  3159. return_frame = true;
  3160. }
  3161. framesize = 0;
  3162. #if SYNCLINK_GENERIC_HDLC
  3163. {
  3164. info->netdev->stats.rx_errors++;
  3165. info->netdev->stats.rx_frame_errors++;
  3166. }
  3167. #endif
  3168. } else
  3169. return_frame = true;
  3170. if (return_frame)
  3171. framesize = buf->count;
  3172. if (debug_level >= DEBUG_LEVEL_BH)
  3173. printk("%s(%d):rx_get_frame(%s) status=%04X size=%d\n",
  3174. __FILE__,__LINE__,info->device_name,status,framesize);
  3175. if (debug_level >= DEBUG_LEVEL_DATA)
  3176. trace_block(info, buf->data, framesize, 0);
  3177. if (framesize) {
  3178. if ((info->params.crc_type & HDLC_CRC_RETURN_EX &&
  3179. framesize+1 > info->max_frame_size) ||
  3180. framesize > info->max_frame_size)
  3181. info->icount.rxlong++;
  3182. else {
  3183. if (status & BIT5)
  3184. info->icount.rxok++;
  3185. if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
  3186. *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR;
  3187. ++framesize;
  3188. }
  3189. #if SYNCLINK_GENERIC_HDLC
  3190. if (info->netcount)
  3191. hdlcdev_rx(info, buf->data, framesize);
  3192. else
  3193. #endif
  3194. ldisc_receive_buf(tty, buf->data, info->flag_buf, framesize);
  3195. }
  3196. }
  3197. spin_lock_irqsave(&info->lock,flags);
  3198. buf->status = buf->count = 0;
  3199. info->rx_frame_count--;
  3200. info->rx_get++;
  3201. if (info->rx_get >= info->rx_buf_count)
  3202. info->rx_get = 0;
  3203. spin_unlock_irqrestore(&info->lock,flags);
  3204. return true;
  3205. }
  3206. static bool register_test(MGSLPC_INFO *info)
  3207. {
  3208. static unsigned char patterns[] =
  3209. { 0x00, 0xff, 0xaa, 0x55, 0x69, 0x96, 0x0f };
  3210. static unsigned int count = ARRAY_SIZE(patterns);
  3211. unsigned int i;
  3212. bool rc = true;
  3213. unsigned long flags;
  3214. spin_lock_irqsave(&info->lock,flags);
  3215. reset_device(info);
  3216. for (i = 0; i < count; i++) {
  3217. write_reg(info, XAD1, patterns[i]);
  3218. write_reg(info, XAD2, patterns[(i + 1) % count]);
  3219. if ((read_reg(info, XAD1) != patterns[i]) ||
  3220. (read_reg(info, XAD2) != patterns[(i + 1) % count])) {
  3221. rc = false;
  3222. break;
  3223. }
  3224. }
  3225. spin_unlock_irqrestore(&info->lock,flags);
  3226. return rc;
  3227. }
  3228. static bool irq_test(MGSLPC_INFO *info)
  3229. {
  3230. unsigned long end_time;
  3231. unsigned long flags;
  3232. spin_lock_irqsave(&info->lock,flags);
  3233. reset_device(info);
  3234. info->testing_irq = true;
  3235. hdlc_mode(info);
  3236. info->irq_occurred = false;
  3237. /* init hdlc mode */
  3238. irq_enable(info, CHA, IRQ_TIMER);
  3239. write_reg(info, CHA + TIMR, 0); /* 512 cycles */
  3240. issue_command(info, CHA, CMD_START_TIMER);
  3241. spin_unlock_irqrestore(&info->lock,flags);
  3242. end_time=100;
  3243. while(end_time-- && !info->irq_occurred) {
  3244. msleep_interruptible(10);
  3245. }
  3246. info->testing_irq = false;
  3247. spin_lock_irqsave(&info->lock,flags);
  3248. reset_device(info);
  3249. spin_unlock_irqrestore(&info->lock,flags);
  3250. return info->irq_occurred;
  3251. }
  3252. static int adapter_test(MGSLPC_INFO *info)
  3253. {
  3254. if (!register_test(info)) {
  3255. info->init_error = DiagStatus_AddressFailure;
  3256. printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
  3257. __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
  3258. return -ENODEV;
  3259. }
  3260. if (!irq_test(info)) {
  3261. info->init_error = DiagStatus_IrqFailure;
  3262. printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
  3263. __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
  3264. return -ENODEV;
  3265. }
  3266. if (debug_level >= DEBUG_LEVEL_INFO)
  3267. printk("%s(%d):device %s passed diagnostics\n",
  3268. __FILE__,__LINE__,info->device_name);
  3269. return 0;
  3270. }
  3271. static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit)
  3272. {
  3273. int i;
  3274. int linecount;
  3275. if (xmit)
  3276. printk("%s tx data:\n",info->device_name);
  3277. else
  3278. printk("%s rx data:\n",info->device_name);
  3279. while(count) {
  3280. if (count > 16)
  3281. linecount = 16;
  3282. else
  3283. linecount = count;
  3284. for(i=0;i<linecount;i++)
  3285. printk("%02X ",(unsigned char)data[i]);
  3286. for(;i<17;i++)
  3287. printk(" ");
  3288. for(i=0;i<linecount;i++) {
  3289. if (data[i]>=040 && data[i]<=0176)
  3290. printk("%c",data[i]);
  3291. else
  3292. printk(".");
  3293. }
  3294. printk("\n");
  3295. data += linecount;
  3296. count -= linecount;
  3297. }
  3298. }
  3299. /* HDLC frame time out
  3300. * update stats and do tx completion processing
  3301. */
  3302. static void tx_timeout(unsigned long context)
  3303. {
  3304. MGSLPC_INFO *info = (MGSLPC_INFO*)context;
  3305. unsigned long flags;
  3306. if ( debug_level >= DEBUG_LEVEL_INFO )
  3307. printk( "%s(%d):tx_timeout(%s)\n",
  3308. __FILE__,__LINE__,info->device_name);
  3309. if(info->tx_active &&
  3310. info->params.mode == MGSL_MODE_HDLC) {
  3311. info->icount.txtimeout++;
  3312. }
  3313. spin_lock_irqsave(&info->lock,flags);
  3314. info->tx_active = false;
  3315. info->tx_count = info->tx_put = info->tx_get = 0;
  3316. spin_unlock_irqrestore(&info->lock,flags);
  3317. #if SYNCLINK_GENERIC_HDLC
  3318. if (info->netcount)
  3319. hdlcdev_tx_done(info);
  3320. else
  3321. #endif
  3322. {
  3323. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3324. bh_transmit(info, tty);
  3325. tty_kref_put(tty);
  3326. }
  3327. }
  3328. #if SYNCLINK_GENERIC_HDLC
  3329. /**
  3330. * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
  3331. * set encoding and frame check sequence (FCS) options
  3332. *
  3333. * dev pointer to network device structure
  3334. * encoding serial encoding setting
  3335. * parity FCS setting
  3336. *
  3337. * returns 0 if success, otherwise error code
  3338. */
  3339. static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
  3340. unsigned short parity)
  3341. {
  3342. MGSLPC_INFO *info = dev_to_port(dev);
  3343. struct tty_struct *tty;
  3344. unsigned char new_encoding;
  3345. unsigned short new_crctype;
  3346. /* return error if TTY interface open */
  3347. if (info->port.count)
  3348. return -EBUSY;
  3349. switch (encoding)
  3350. {
  3351. case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
  3352. case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
  3353. case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
  3354. case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
  3355. case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
  3356. default: return -EINVAL;
  3357. }
  3358. switch (parity)
  3359. {
  3360. case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
  3361. case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
  3362. case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
  3363. default: return -EINVAL;
  3364. }
  3365. info->params.encoding = new_encoding;
  3366. info->params.crc_type = new_crctype;
  3367. /* if network interface up, reprogram hardware */
  3368. if (info->netcount) {
  3369. tty = tty_port_tty_get(&info->port);
  3370. mgslpc_program_hw(info, tty);
  3371. tty_kref_put(tty);
  3372. }
  3373. return 0;
  3374. }
  3375. /**
  3376. * called by generic HDLC layer to send frame
  3377. *
  3378. * skb socket buffer containing HDLC frame
  3379. * dev pointer to network device structure
  3380. */
  3381. static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
  3382. struct net_device *dev)
  3383. {
  3384. MGSLPC_INFO *info = dev_to_port(dev);
  3385. unsigned long flags;
  3386. if (debug_level >= DEBUG_LEVEL_INFO)
  3387. printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
  3388. /* stop sending until this frame completes */
  3389. netif_stop_queue(dev);
  3390. /* copy data to device buffers */
  3391. skb_copy_from_linear_data(skb, info->tx_buf, skb->len);
  3392. info->tx_get = 0;
  3393. info->tx_put = info->tx_count = skb->len;
  3394. /* update network statistics */
  3395. dev->stats.tx_packets++;
  3396. dev->stats.tx_bytes += skb->len;
  3397. /* done with socket buffer, so free it */
  3398. dev_kfree_skb(skb);
  3399. /* save start time for transmit timeout detection */
  3400. dev->trans_start = jiffies;
  3401. /* start hardware transmitter if necessary */
  3402. spin_lock_irqsave(&info->lock,flags);
  3403. if (!info->tx_active) {
  3404. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3405. tx_start(info, tty);
  3406. tty_kref_put(tty);
  3407. }
  3408. spin_unlock_irqrestore(&info->lock,flags);
  3409. return NETDEV_TX_OK;
  3410. }
  3411. /**
  3412. * called by network layer when interface enabled
  3413. * claim resources and initialize hardware
  3414. *
  3415. * dev pointer to network device structure
  3416. *
  3417. * returns 0 if success, otherwise error code
  3418. */
  3419. static int hdlcdev_open(struct net_device *dev)
  3420. {
  3421. MGSLPC_INFO *info = dev_to_port(dev);
  3422. struct tty_struct *tty;
  3423. int rc;
  3424. unsigned long flags;
  3425. if (debug_level >= DEBUG_LEVEL_INFO)
  3426. printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
  3427. /* generic HDLC layer open processing */
  3428. if ((rc = hdlc_open(dev)))
  3429. return rc;
  3430. /* arbitrate between network and tty opens */
  3431. spin_lock_irqsave(&info->netlock, flags);
  3432. if (info->port.count != 0 || info->netcount != 0) {
  3433. printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
  3434. spin_unlock_irqrestore(&info->netlock, flags);
  3435. return -EBUSY;
  3436. }
  3437. info->netcount=1;
  3438. spin_unlock_irqrestore(&info->netlock, flags);
  3439. tty = tty_port_tty_get(&info->port);
  3440. /* claim resources and init adapter */
  3441. if ((rc = startup(info, tty)) != 0) {
  3442. tty_kref_put(tty);
  3443. spin_lock_irqsave(&info->netlock, flags);
  3444. info->netcount=0;
  3445. spin_unlock_irqrestore(&info->netlock, flags);
  3446. return rc;
  3447. }
  3448. /* assert DTR and RTS, apply hardware settings */
  3449. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  3450. mgslpc_program_hw(info, tty);
  3451. tty_kref_put(tty);
  3452. /* enable network layer transmit */
  3453. dev->trans_start = jiffies;
  3454. netif_start_queue(dev);
  3455. /* inform generic HDLC layer of current DCD status */
  3456. spin_lock_irqsave(&info->lock, flags);
  3457. get_signals(info);
  3458. spin_unlock_irqrestore(&info->lock, flags);
  3459. if (info->serial_signals & SerialSignal_DCD)
  3460. netif_carrier_on(dev);
  3461. else
  3462. netif_carrier_off(dev);
  3463. return 0;
  3464. }
  3465. /**
  3466. * called by network layer when interface is disabled
  3467. * shutdown hardware and release resources
  3468. *
  3469. * dev pointer to network device structure
  3470. *
  3471. * returns 0 if success, otherwise error code
  3472. */
  3473. static int hdlcdev_close(struct net_device *dev)
  3474. {
  3475. MGSLPC_INFO *info = dev_to_port(dev);
  3476. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3477. unsigned long flags;
  3478. if (debug_level >= DEBUG_LEVEL_INFO)
  3479. printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
  3480. netif_stop_queue(dev);
  3481. /* shutdown adapter and release resources */
  3482. shutdown(info, tty);
  3483. tty_kref_put(tty);
  3484. hdlc_close(dev);
  3485. spin_lock_irqsave(&info->netlock, flags);
  3486. info->netcount=0;
  3487. spin_unlock_irqrestore(&info->netlock, flags);
  3488. return 0;
  3489. }
  3490. /**
  3491. * called by network layer to process IOCTL call to network device
  3492. *
  3493. * dev pointer to network device structure
  3494. * ifr pointer to network interface request structure
  3495. * cmd IOCTL command code
  3496. *
  3497. * returns 0 if success, otherwise error code
  3498. */
  3499. static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  3500. {
  3501. const size_t size = sizeof(sync_serial_settings);
  3502. sync_serial_settings new_line;
  3503. sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
  3504. MGSLPC_INFO *info = dev_to_port(dev);
  3505. unsigned int flags;
  3506. if (debug_level >= DEBUG_LEVEL_INFO)
  3507. printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
  3508. /* return error if TTY interface open */
  3509. if (info->port.count)
  3510. return -EBUSY;
  3511. if (cmd != SIOCWANDEV)
  3512. return hdlc_ioctl(dev, ifr, cmd);
  3513. switch(ifr->ifr_settings.type) {
  3514. case IF_GET_IFACE: /* return current sync_serial_settings */
  3515. ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
  3516. if (ifr->ifr_settings.size < size) {
  3517. ifr->ifr_settings.size = size; /* data size wanted */
  3518. return -ENOBUFS;
  3519. }
  3520. flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3521. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3522. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3523. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  3524. switch (flags){
  3525. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
  3526. case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
  3527. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
  3528. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
  3529. default: new_line.clock_type = CLOCK_DEFAULT;
  3530. }
  3531. new_line.clock_rate = info->params.clock_speed;
  3532. new_line.loopback = info->params.loopback ? 1:0;
  3533. if (copy_to_user(line, &new_line, size))
  3534. return -EFAULT;
  3535. return 0;
  3536. case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
  3537. if(!capable(CAP_NET_ADMIN))
  3538. return -EPERM;
  3539. if (copy_from_user(&new_line, line, size))
  3540. return -EFAULT;
  3541. switch (new_line.clock_type)
  3542. {
  3543. case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
  3544. case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
  3545. case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
  3546. case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
  3547. case CLOCK_DEFAULT: flags = info->params.flags &
  3548. (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3549. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3550. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3551. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
  3552. default: return -EINVAL;
  3553. }
  3554. if (new_line.loopback != 0 && new_line.loopback != 1)
  3555. return -EINVAL;
  3556. info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3557. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3558. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3559. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  3560. info->params.flags |= flags;
  3561. info->params.loopback = new_line.loopback;
  3562. if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
  3563. info->params.clock_speed = new_line.clock_rate;
  3564. else
  3565. info->params.clock_speed = 0;
  3566. /* if network interface up, reprogram hardware */
  3567. if (info->netcount) {
  3568. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3569. mgslpc_program_hw(info, tty);
  3570. tty_kref_put(tty);
  3571. }
  3572. return 0;
  3573. default:
  3574. return hdlc_ioctl(dev, ifr, cmd);
  3575. }
  3576. }
  3577. /**
  3578. * called by network layer when transmit timeout is detected
  3579. *
  3580. * dev pointer to network device structure
  3581. */
  3582. static void hdlcdev_tx_timeout(struct net_device *dev)
  3583. {
  3584. MGSLPC_INFO *info = dev_to_port(dev);
  3585. unsigned long flags;
  3586. if (debug_level >= DEBUG_LEVEL_INFO)
  3587. printk("hdlcdev_tx_timeout(%s)\n",dev->name);
  3588. dev->stats.tx_errors++;
  3589. dev->stats.tx_aborted_errors++;
  3590. spin_lock_irqsave(&info->lock,flags);
  3591. tx_stop(info);
  3592. spin_unlock_irqrestore(&info->lock,flags);
  3593. netif_wake_queue(dev);
  3594. }
  3595. /**
  3596. * called by device driver when transmit completes
  3597. * reenable network layer transmit if stopped
  3598. *
  3599. * info pointer to device instance information
  3600. */
  3601. static void hdlcdev_tx_done(MGSLPC_INFO *info)
  3602. {
  3603. if (netif_queue_stopped(info->netdev))
  3604. netif_wake_queue(info->netdev);
  3605. }
  3606. /**
  3607. * called by device driver when frame received
  3608. * pass frame to network layer
  3609. *
  3610. * info pointer to device instance information
  3611. * buf pointer to buffer contianing frame data
  3612. * size count of data bytes in buf
  3613. */
  3614. static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size)
  3615. {
  3616. struct sk_buff *skb = dev_alloc_skb(size);
  3617. struct net_device *dev = info->netdev;
  3618. if (debug_level >= DEBUG_LEVEL_INFO)
  3619. printk("hdlcdev_rx(%s)\n",dev->name);
  3620. if (skb == NULL) {
  3621. printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
  3622. dev->stats.rx_dropped++;
  3623. return;
  3624. }
  3625. memcpy(skb_put(skb, size), buf, size);
  3626. skb->protocol = hdlc_type_trans(skb, dev);
  3627. dev->stats.rx_packets++;
  3628. dev->stats.rx_bytes += size;
  3629. netif_rx(skb);
  3630. }
  3631. static const struct net_device_ops hdlcdev_ops = {
  3632. .ndo_open = hdlcdev_open,
  3633. .ndo_stop = hdlcdev_close,
  3634. .ndo_change_mtu = hdlc_change_mtu,
  3635. .ndo_start_xmit = hdlc_start_xmit,
  3636. .ndo_do_ioctl = hdlcdev_ioctl,
  3637. .ndo_tx_timeout = hdlcdev_tx_timeout,
  3638. };
  3639. /**
  3640. * called by device driver when adding device instance
  3641. * do generic HDLC initialization
  3642. *
  3643. * info pointer to device instance information
  3644. *
  3645. * returns 0 if success, otherwise error code
  3646. */
  3647. static int hdlcdev_init(MGSLPC_INFO *info)
  3648. {
  3649. int rc;
  3650. struct net_device *dev;
  3651. hdlc_device *hdlc;
  3652. /* allocate and initialize network and HDLC layer objects */
  3653. if (!(dev = alloc_hdlcdev(info))) {
  3654. printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
  3655. return -ENOMEM;
  3656. }
  3657. /* for network layer reporting purposes only */
  3658. dev->base_addr = info->io_base;
  3659. dev->irq = info->irq_level;
  3660. /* network layer callbacks and settings */
  3661. dev->netdev_ops = &hdlcdev_ops;
  3662. dev->watchdog_timeo = 10 * HZ;
  3663. dev->tx_queue_len = 50;
  3664. /* generic HDLC layer callbacks and settings */
  3665. hdlc = dev_to_hdlc(dev);
  3666. hdlc->attach = hdlcdev_attach;
  3667. hdlc->xmit = hdlcdev_xmit;
  3668. /* register objects with HDLC layer */
  3669. if ((rc = register_hdlc_device(dev))) {
  3670. printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
  3671. free_netdev(dev);
  3672. return rc;
  3673. }
  3674. info->netdev = dev;
  3675. return 0;
  3676. }
  3677. /**
  3678. * called by device driver when removing device instance
  3679. * do generic HDLC cleanup
  3680. *
  3681. * info pointer to device instance information
  3682. */
  3683. static void hdlcdev_exit(MGSLPC_INFO *info)
  3684. {
  3685. unregister_hdlc_device(info->netdev);
  3686. free_netdev(info->netdev);
  3687. info->netdev = NULL;
  3688. }
  3689. #endif /* CONFIG_HDLC */