cciss.h 7.7 KB

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  1. #ifndef CCISS_H
  2. #define CCISS_H
  3. #include <linux/genhd.h>
  4. #include <linux/mutex.h>
  5. #include "cciss_cmd.h"
  6. #define NWD_SHIFT 4
  7. #define MAX_PART (1 << NWD_SHIFT)
  8. #define IO_OK 0
  9. #define IO_ERROR 1
  10. #define IO_NEEDS_RETRY 3
  11. #define VENDOR_LEN 8
  12. #define MODEL_LEN 16
  13. #define REV_LEN 4
  14. struct ctlr_info;
  15. typedef struct ctlr_info ctlr_info_t;
  16. struct access_method {
  17. void (*submit_command)(ctlr_info_t *h, CommandList_struct *c);
  18. void (*set_intr_mask)(ctlr_info_t *h, unsigned long val);
  19. unsigned long (*fifo_full)(ctlr_info_t *h);
  20. unsigned long (*intr_pending)(ctlr_info_t *h);
  21. unsigned long (*command_completed)(ctlr_info_t *h);
  22. };
  23. typedef struct _drive_info_struct
  24. {
  25. unsigned char LunID[8];
  26. int usage_count;
  27. struct request_queue *queue;
  28. sector_t nr_blocks;
  29. int block_size;
  30. int heads;
  31. int sectors;
  32. int cylinders;
  33. int raid_level; /* set to -1 to indicate that
  34. * the drive is not in use/configured
  35. */
  36. int busy_configuring; /* This is set when a drive is being removed
  37. * to prevent it from being opened or it's
  38. * queue from being started.
  39. */
  40. struct device dev;
  41. __u8 serial_no[16]; /* from inquiry page 0x83,
  42. * not necc. null terminated.
  43. */
  44. char vendor[VENDOR_LEN + 1]; /* SCSI vendor string */
  45. char model[MODEL_LEN + 1]; /* SCSI model string */
  46. char rev[REV_LEN + 1]; /* SCSI revision string */
  47. char device_initialized; /* indicates whether dev is initialized */
  48. } drive_info_struct;
  49. struct Cmd_sg_list {
  50. SGDescriptor_struct *sgchain;
  51. dma_addr_t sg_chain_dma;
  52. int chain_block_size;
  53. };
  54. struct ctlr_info
  55. {
  56. int ctlr;
  57. char devname[8];
  58. char *product_name;
  59. char firm_ver[4]; // Firmware version
  60. struct pci_dev *pdev;
  61. __u32 board_id;
  62. void __iomem *vaddr;
  63. unsigned long paddr;
  64. int nr_cmds; /* Number of commands allowed on this controller */
  65. CfgTable_struct __iomem *cfgtable;
  66. int interrupts_enabled;
  67. int major;
  68. int max_commands;
  69. int commands_outstanding;
  70. int max_outstanding; /* Debug */
  71. int num_luns;
  72. int highest_lun;
  73. int usage_count; /* number of opens all all minor devices */
  74. /* Need space for temp sg list
  75. * number of scatter/gathers supported
  76. * number of scatter/gathers in chained block
  77. */
  78. struct scatterlist **scatter_list;
  79. int maxsgentries;
  80. int chainsize;
  81. int max_cmd_sgentries;
  82. struct Cmd_sg_list **cmd_sg_list;
  83. # define DOORBELL_INT 0
  84. # define PERF_MODE_INT 1
  85. # define SIMPLE_MODE_INT 2
  86. # define MEMQ_MODE_INT 3
  87. unsigned int intr[4];
  88. unsigned int msix_vector;
  89. unsigned int msi_vector;
  90. int cciss_max_sectors;
  91. BYTE cciss_read;
  92. BYTE cciss_write;
  93. BYTE cciss_read_capacity;
  94. // information about each logical volume
  95. drive_info_struct *drv[CISS_MAX_LUN];
  96. struct access_method access;
  97. /* queue and queue Info */
  98. struct hlist_head reqQ;
  99. struct hlist_head cmpQ;
  100. unsigned int Qdepth;
  101. unsigned int maxQsinceinit;
  102. unsigned int maxSG;
  103. spinlock_t lock;
  104. //* pointers to command and error info pool */
  105. CommandList_struct *cmd_pool;
  106. dma_addr_t cmd_pool_dhandle;
  107. ErrorInfo_struct *errinfo_pool;
  108. dma_addr_t errinfo_pool_dhandle;
  109. unsigned long *cmd_pool_bits;
  110. int nr_allocs;
  111. int nr_frees;
  112. int busy_configuring;
  113. int busy_initializing;
  114. int busy_scanning;
  115. struct mutex busy_shutting_down;
  116. /* This element holds the zero based queue number of the last
  117. * queue to be started. It is used for fairness.
  118. */
  119. int next_to_run;
  120. // Disk structures we need to pass back
  121. struct gendisk *gendisk[CISS_MAX_LUN];
  122. #ifdef CONFIG_CISS_SCSI_TAPE
  123. void *scsi_ctlr; /* ptr to structure containing scsi related stuff */
  124. /* list of block side commands the scsi error handling sucked up */
  125. /* and saved for later processing */
  126. #endif
  127. unsigned char alive;
  128. struct list_head scan_list;
  129. struct completion scan_wait;
  130. struct device dev;
  131. };
  132. /* Defining the diffent access_menthods */
  133. /*
  134. * Memory mapped FIFO interface (SMART 53xx cards)
  135. */
  136. #define SA5_DOORBELL 0x20
  137. #define SA5_REQUEST_PORT_OFFSET 0x40
  138. #define SA5_REPLY_INTR_MASK_OFFSET 0x34
  139. #define SA5_REPLY_PORT_OFFSET 0x44
  140. #define SA5_INTR_STATUS 0x30
  141. #define SA5_SCRATCHPAD_OFFSET 0xB0
  142. #define SA5_CTCFG_OFFSET 0xB4
  143. #define SA5_CTMEM_OFFSET 0xB8
  144. #define SA5_INTR_OFF 0x08
  145. #define SA5B_INTR_OFF 0x04
  146. #define SA5_INTR_PENDING 0x08
  147. #define SA5B_INTR_PENDING 0x04
  148. #define FIFO_EMPTY 0xffffffff
  149. #define CCISS_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
  150. #define CISS_ERROR_BIT 0x02
  151. #define CCISS_INTR_ON 1
  152. #define CCISS_INTR_OFF 0
  153. /*
  154. Send the command to the hardware
  155. */
  156. static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c)
  157. {
  158. #ifdef CCISS_DEBUG
  159. printk("Sending %x - down to controller\n", c->busaddr );
  160. #endif /* CCISS_DEBUG */
  161. writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
  162. h->commands_outstanding++;
  163. if ( h->commands_outstanding > h->max_outstanding)
  164. h->max_outstanding = h->commands_outstanding;
  165. }
  166. /*
  167. * This card is the opposite of the other cards.
  168. * 0 turns interrupts on...
  169. * 0x08 turns them off...
  170. */
  171. static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)
  172. {
  173. if (val)
  174. { /* Turn interrupts on */
  175. h->interrupts_enabled = 1;
  176. writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  177. } else /* Turn them off */
  178. {
  179. h->interrupts_enabled = 0;
  180. writel( SA5_INTR_OFF,
  181. h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  182. }
  183. }
  184. /*
  185. * This card is the opposite of the other cards.
  186. * 0 turns interrupts on...
  187. * 0x04 turns them off...
  188. */
  189. static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)
  190. {
  191. if (val)
  192. { /* Turn interrupts on */
  193. h->interrupts_enabled = 1;
  194. writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  195. } else /* Turn them off */
  196. {
  197. h->interrupts_enabled = 0;
  198. writel( SA5B_INTR_OFF,
  199. h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  200. }
  201. }
  202. /*
  203. * Returns true if fifo is full.
  204. *
  205. */
  206. static unsigned long SA5_fifo_full(ctlr_info_t *h)
  207. {
  208. if( h->commands_outstanding >= h->max_commands)
  209. return(1);
  210. else
  211. return(0);
  212. }
  213. /*
  214. * returns value read from hardware.
  215. * returns FIFO_EMPTY if there is nothing to read
  216. */
  217. static unsigned long SA5_completed(ctlr_info_t *h)
  218. {
  219. unsigned long register_value
  220. = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
  221. if(register_value != FIFO_EMPTY)
  222. {
  223. h->commands_outstanding--;
  224. #ifdef CCISS_DEBUG
  225. printk("cciss: Read %lx back from board\n", register_value);
  226. #endif /* CCISS_DEBUG */
  227. }
  228. #ifdef CCISS_DEBUG
  229. else
  230. {
  231. printk("cciss: FIFO Empty read\n");
  232. }
  233. #endif
  234. return ( register_value);
  235. }
  236. /*
  237. * Returns true if an interrupt is pending..
  238. */
  239. static unsigned long SA5_intr_pending(ctlr_info_t *h)
  240. {
  241. unsigned long register_value =
  242. readl(h->vaddr + SA5_INTR_STATUS);
  243. #ifdef CCISS_DEBUG
  244. printk("cciss: intr_pending %lx\n", register_value);
  245. #endif /* CCISS_DEBUG */
  246. if( register_value & SA5_INTR_PENDING)
  247. return 1;
  248. return 0 ;
  249. }
  250. /*
  251. * Returns true if an interrupt is pending..
  252. */
  253. static unsigned long SA5B_intr_pending(ctlr_info_t *h)
  254. {
  255. unsigned long register_value =
  256. readl(h->vaddr + SA5_INTR_STATUS);
  257. #ifdef CCISS_DEBUG
  258. printk("cciss: intr_pending %lx\n", register_value);
  259. #endif /* CCISS_DEBUG */
  260. if( register_value & SA5B_INTR_PENDING)
  261. return 1;
  262. return 0 ;
  263. }
  264. static struct access_method SA5_access = {
  265. SA5_submit_command,
  266. SA5_intr_mask,
  267. SA5_fifo_full,
  268. SA5_intr_pending,
  269. SA5_completed,
  270. };
  271. static struct access_method SA5B_access = {
  272. SA5_submit_command,
  273. SA5B_intr_mask,
  274. SA5_fifo_full,
  275. SA5B_intr_pending,
  276. SA5_completed,
  277. };
  278. struct board_type {
  279. __u32 board_id;
  280. char *product_name;
  281. struct access_method *access;
  282. int nr_cmds; /* Max cmds this kind of ctlr can handle. */
  283. };
  284. #define CCISS_LOCK(i) (&hba[i]->lock)
  285. #endif /* CCISS_H */