setup-sh7785.c 15 KB

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  1. /*
  2. * SH7785 Setup
  3. *
  4. * Copyright (C) 2007 Paul Mundt
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/platform_device.h>
  11. #include <linux/init.h>
  12. #include <linux/serial.h>
  13. #include <linux/serial_sci.h>
  14. #include <linux/io.h>
  15. #include <linux/mm.h>
  16. #include <linux/sh_timer.h>
  17. #include <asm/dma-sh.h>
  18. #include <asm/mmzone.h>
  19. static struct plat_sci_port scif0_platform_data = {
  20. .mapbase = 0xffea0000,
  21. .flags = UPF_BOOT_AUTOCONF,
  22. .type = PORT_SCIF,
  23. .irqs = { 40, 40, 40, 40 },
  24. .clk = "scif_fck",
  25. };
  26. static struct platform_device scif0_device = {
  27. .name = "sh-sci",
  28. .id = 0,
  29. .dev = {
  30. .platform_data = &scif0_platform_data,
  31. },
  32. };
  33. static struct plat_sci_port scif1_platform_data = {
  34. .mapbase = 0xffeb0000,
  35. .flags = UPF_BOOT_AUTOCONF,
  36. .type = PORT_SCIF,
  37. .irqs = { 44, 44, 44, 44 },
  38. .clk = "scif_fck",
  39. };
  40. static struct platform_device scif1_device = {
  41. .name = "sh-sci",
  42. .id = 1,
  43. .dev = {
  44. .platform_data = &scif1_platform_data,
  45. },
  46. };
  47. static struct plat_sci_port scif2_platform_data = {
  48. .mapbase = 0xffec0000,
  49. .flags = UPF_BOOT_AUTOCONF,
  50. .type = PORT_SCIF,
  51. .irqs = { 60, 60, 60, 60 },
  52. .clk = "scif_fck",
  53. };
  54. static struct platform_device scif2_device = {
  55. .name = "sh-sci",
  56. .id = 2,
  57. .dev = {
  58. .platform_data = &scif2_platform_data,
  59. },
  60. };
  61. static struct plat_sci_port scif3_platform_data = {
  62. .mapbase = 0xffed0000,
  63. .flags = UPF_BOOT_AUTOCONF,
  64. .type = PORT_SCIF,
  65. .irqs = { 61, 61, 61, 61 },
  66. .clk = "scif_fck",
  67. };
  68. static struct platform_device scif3_device = {
  69. .name = "sh-sci",
  70. .id = 3,
  71. .dev = {
  72. .platform_data = &scif3_platform_data,
  73. },
  74. };
  75. static struct plat_sci_port scif4_platform_data = {
  76. .mapbase = 0xffee0000,
  77. .flags = UPF_BOOT_AUTOCONF,
  78. .type = PORT_SCIF,
  79. .irqs = { 62, 62, 62, 62 },
  80. .clk = "scif_fck",
  81. };
  82. static struct platform_device scif4_device = {
  83. .name = "sh-sci",
  84. .id = 4,
  85. .dev = {
  86. .platform_data = &scif4_platform_data,
  87. },
  88. };
  89. static struct plat_sci_port scif5_platform_data = {
  90. .mapbase = 0xffef0000,
  91. .flags = UPF_BOOT_AUTOCONF,
  92. .type = PORT_SCIF,
  93. .irqs = { 63, 63, 63, 63 },
  94. .clk = "scif_fck",
  95. };
  96. static struct platform_device scif5_device = {
  97. .name = "sh-sci",
  98. .id = 5,
  99. .dev = {
  100. .platform_data = &scif5_platform_data,
  101. },
  102. };
  103. static struct sh_timer_config tmu0_platform_data = {
  104. .name = "TMU0",
  105. .channel_offset = 0x04,
  106. .timer_bit = 0,
  107. .clk = "tmu012_fck",
  108. .clockevent_rating = 200,
  109. };
  110. static struct resource tmu0_resources[] = {
  111. [0] = {
  112. .name = "TMU0",
  113. .start = 0xffd80008,
  114. .end = 0xffd80013,
  115. .flags = IORESOURCE_MEM,
  116. },
  117. [1] = {
  118. .start = 28,
  119. .flags = IORESOURCE_IRQ,
  120. },
  121. };
  122. static struct platform_device tmu0_device = {
  123. .name = "sh_tmu",
  124. .id = 0,
  125. .dev = {
  126. .platform_data = &tmu0_platform_data,
  127. },
  128. .resource = tmu0_resources,
  129. .num_resources = ARRAY_SIZE(tmu0_resources),
  130. };
  131. static struct sh_timer_config tmu1_platform_data = {
  132. .name = "TMU1",
  133. .channel_offset = 0x10,
  134. .timer_bit = 1,
  135. .clk = "tmu012_fck",
  136. .clocksource_rating = 200,
  137. };
  138. static struct resource tmu1_resources[] = {
  139. [0] = {
  140. .name = "TMU1",
  141. .start = 0xffd80014,
  142. .end = 0xffd8001f,
  143. .flags = IORESOURCE_MEM,
  144. },
  145. [1] = {
  146. .start = 29,
  147. .flags = IORESOURCE_IRQ,
  148. },
  149. };
  150. static struct platform_device tmu1_device = {
  151. .name = "sh_tmu",
  152. .id = 1,
  153. .dev = {
  154. .platform_data = &tmu1_platform_data,
  155. },
  156. .resource = tmu1_resources,
  157. .num_resources = ARRAY_SIZE(tmu1_resources),
  158. };
  159. static struct sh_timer_config tmu2_platform_data = {
  160. .name = "TMU2",
  161. .channel_offset = 0x1c,
  162. .timer_bit = 2,
  163. .clk = "tmu012_fck",
  164. };
  165. static struct resource tmu2_resources[] = {
  166. [0] = {
  167. .name = "TMU2",
  168. .start = 0xffd80020,
  169. .end = 0xffd8002f,
  170. .flags = IORESOURCE_MEM,
  171. },
  172. [1] = {
  173. .start = 30,
  174. .flags = IORESOURCE_IRQ,
  175. },
  176. };
  177. static struct platform_device tmu2_device = {
  178. .name = "sh_tmu",
  179. .id = 2,
  180. .dev = {
  181. .platform_data = &tmu2_platform_data,
  182. },
  183. .resource = tmu2_resources,
  184. .num_resources = ARRAY_SIZE(tmu2_resources),
  185. };
  186. static struct sh_timer_config tmu3_platform_data = {
  187. .name = "TMU3",
  188. .channel_offset = 0x04,
  189. .timer_bit = 0,
  190. .clk = "tmu345_fck",
  191. };
  192. static struct resource tmu3_resources[] = {
  193. [0] = {
  194. .name = "TMU3",
  195. .start = 0xffdc0008,
  196. .end = 0xffdc0013,
  197. .flags = IORESOURCE_MEM,
  198. },
  199. [1] = {
  200. .start = 96,
  201. .flags = IORESOURCE_IRQ,
  202. },
  203. };
  204. static struct platform_device tmu3_device = {
  205. .name = "sh_tmu",
  206. .id = 3,
  207. .dev = {
  208. .platform_data = &tmu3_platform_data,
  209. },
  210. .resource = tmu3_resources,
  211. .num_resources = ARRAY_SIZE(tmu3_resources),
  212. };
  213. static struct sh_timer_config tmu4_platform_data = {
  214. .name = "TMU4",
  215. .channel_offset = 0x10,
  216. .timer_bit = 1,
  217. .clk = "tmu345_fck",
  218. };
  219. static struct resource tmu4_resources[] = {
  220. [0] = {
  221. .name = "TMU4",
  222. .start = 0xffdc0014,
  223. .end = 0xffdc001f,
  224. .flags = IORESOURCE_MEM,
  225. },
  226. [1] = {
  227. .start = 97,
  228. .flags = IORESOURCE_IRQ,
  229. },
  230. };
  231. static struct platform_device tmu4_device = {
  232. .name = "sh_tmu",
  233. .id = 4,
  234. .dev = {
  235. .platform_data = &tmu4_platform_data,
  236. },
  237. .resource = tmu4_resources,
  238. .num_resources = ARRAY_SIZE(tmu4_resources),
  239. };
  240. static struct sh_timer_config tmu5_platform_data = {
  241. .name = "TMU5",
  242. .channel_offset = 0x1c,
  243. .timer_bit = 2,
  244. .clk = "tmu345_fck",
  245. };
  246. static struct resource tmu5_resources[] = {
  247. [0] = {
  248. .name = "TMU5",
  249. .start = 0xffdc0020,
  250. .end = 0xffdc002b,
  251. .flags = IORESOURCE_MEM,
  252. },
  253. [1] = {
  254. .start = 98,
  255. .flags = IORESOURCE_IRQ,
  256. },
  257. };
  258. static struct platform_device tmu5_device = {
  259. .name = "sh_tmu",
  260. .id = 5,
  261. .dev = {
  262. .platform_data = &tmu5_platform_data,
  263. },
  264. .resource = tmu5_resources,
  265. .num_resources = ARRAY_SIZE(tmu5_resources),
  266. };
  267. static struct sh_dmae_pdata dma_platform_data = {
  268. .mode = (SHDMA_MIX_IRQ | SHDMA_DMAOR1),
  269. };
  270. static struct platform_device dma_device = {
  271. .name = "sh-dma-engine",
  272. .id = -1,
  273. .dev = {
  274. .platform_data = &dma_platform_data,
  275. },
  276. };
  277. static struct platform_device *sh7785_devices[] __initdata = {
  278. &scif0_device,
  279. &scif1_device,
  280. &scif2_device,
  281. &scif3_device,
  282. &scif4_device,
  283. &scif5_device,
  284. &tmu0_device,
  285. &tmu1_device,
  286. &tmu2_device,
  287. &tmu3_device,
  288. &tmu4_device,
  289. &tmu5_device,
  290. &dma_device,
  291. };
  292. static int __init sh7785_devices_setup(void)
  293. {
  294. return platform_add_devices(sh7785_devices,
  295. ARRAY_SIZE(sh7785_devices));
  296. }
  297. arch_initcall(sh7785_devices_setup);
  298. static struct platform_device *sh7785_early_devices[] __initdata = {
  299. &scif0_device,
  300. &scif1_device,
  301. &scif2_device,
  302. &scif3_device,
  303. &scif4_device,
  304. &scif5_device,
  305. &tmu0_device,
  306. &tmu1_device,
  307. &tmu2_device,
  308. &tmu3_device,
  309. &tmu4_device,
  310. &tmu5_device,
  311. };
  312. void __init plat_early_device_setup(void)
  313. {
  314. early_platform_add_devices(sh7785_early_devices,
  315. ARRAY_SIZE(sh7785_early_devices));
  316. }
  317. enum {
  318. UNUSED = 0,
  319. /* interrupt sources */
  320. IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
  321. IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
  322. IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
  323. IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
  324. IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
  325. IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
  326. IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
  327. IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
  328. IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  329. WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
  330. HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
  331. SCIF2, SCIF3, SCIF4, SCIF5,
  332. PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
  333. SIOF, MMCIF, DU, GDTA,
  334. TMU3, TMU4, TMU5,
  335. SSI0, SSI1,
  336. HAC0, HAC1,
  337. FLCTL, GPIO,
  338. /* interrupt groups */
  339. TMU012, TMU345
  340. };
  341. static struct intc_vect vectors[] __initdata = {
  342. INTC_VECT(WDT, 0x560),
  343. INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
  344. INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
  345. INTC_VECT(HUDI, 0x600),
  346. INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
  347. INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
  348. INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
  349. INTC_VECT(DMAC0, 0x6e0),
  350. INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
  351. INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
  352. INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
  353. INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
  354. INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
  355. INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
  356. INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
  357. INTC_VECT(DMAC1, 0x940),
  358. INTC_VECT(HSPI, 0x960),
  359. INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
  360. INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
  361. INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
  362. INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
  363. INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
  364. INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
  365. INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
  366. INTC_VECT(SIOF, 0xc00),
  367. INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
  368. INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
  369. INTC_VECT(DU, 0xd80),
  370. INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
  371. INTC_VECT(GDTA, 0xde0),
  372. INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
  373. INTC_VECT(TMU5, 0xe40),
  374. INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
  375. INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
  376. INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
  377. INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
  378. INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
  379. INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
  380. };
  381. static struct intc_group groups[] __initdata = {
  382. INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
  383. INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
  384. };
  385. static struct intc_mask_reg mask_registers[] __initdata = {
  386. { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
  387. { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
  388. { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
  389. { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
  390. IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
  391. IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
  392. IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
  393. IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
  394. IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
  395. IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
  396. IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
  397. { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
  398. { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
  399. FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
  400. PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
  401. SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
  402. };
  403. static struct intc_prio_reg prio_registers[] __initdata = {
  404. { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
  405. IRQ4, IRQ5, IRQ6, IRQ7 } },
  406. { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
  407. TMU2, TMU2_TICPI } },
  408. { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
  409. { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
  410. SCIF2, SCIF3 } },
  411. { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
  412. { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
  413. { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
  414. PCISERR, PCIINTA } },
  415. { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
  416. PCIINTD, PCIC5 } },
  417. { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
  418. { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
  419. { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
  420. };
  421. static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
  422. mask_registers, prio_registers, NULL);
  423. /* Support for external interrupt pins in IRQ mode */
  424. static struct intc_vect vectors_irq0123[] __initdata = {
  425. INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
  426. INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
  427. };
  428. static struct intc_vect vectors_irq4567[] __initdata = {
  429. INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
  430. INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
  431. };
  432. static struct intc_sense_reg sense_registers[] __initdata = {
  433. { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
  434. IRQ4, IRQ5, IRQ6, IRQ7 } },
  435. };
  436. static struct intc_mask_reg ack_registers[] __initdata = {
  437. { 0xffd00024, 0, 32, /* INTREQ */
  438. { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
  439. };
  440. static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
  441. vectors_irq0123, NULL, mask_registers,
  442. prio_registers, sense_registers, ack_registers);
  443. static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
  444. vectors_irq4567, NULL, mask_registers,
  445. prio_registers, sense_registers, ack_registers);
  446. /* External interrupt pins in IRL mode */
  447. static struct intc_vect vectors_irl0123[] __initdata = {
  448. INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
  449. INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
  450. INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
  451. INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
  452. INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
  453. INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
  454. INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
  455. INTC_VECT(IRL0_HHHL, 0x3c0),
  456. };
  457. static struct intc_vect vectors_irl4567[] __initdata = {
  458. INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
  459. INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
  460. INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
  461. INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
  462. INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
  463. INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
  464. INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
  465. INTC_VECT(IRL4_HHHL, 0xcc0),
  466. };
  467. static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
  468. NULL, mask_registers, NULL, NULL);
  469. static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
  470. NULL, mask_registers, NULL, NULL);
  471. #define INTC_ICR0 0xffd00000
  472. #define INTC_INTMSK0 0xffd00044
  473. #define INTC_INTMSK1 0xffd00048
  474. #define INTC_INTMSK2 0xffd40080
  475. #define INTC_INTMSKCLR1 0xffd00068
  476. #define INTC_INTMSKCLR2 0xffd40084
  477. void __init plat_irq_setup(void)
  478. {
  479. /* disable IRQ3-0 + IRQ7-4 */
  480. ctrl_outl(0xff000000, INTC_INTMSK0);
  481. /* disable IRL3-0 + IRL7-4 */
  482. ctrl_outl(0xc0000000, INTC_INTMSK1);
  483. ctrl_outl(0xfffefffe, INTC_INTMSK2);
  484. /* select IRL mode for IRL3-0 + IRL7-4 */
  485. ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
  486. /* disable holding function, ie enable "SH-4 Mode" */
  487. ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
  488. register_intc_controller(&intc_desc);
  489. }
  490. void __init plat_irq_setup_pins(int mode)
  491. {
  492. switch (mode) {
  493. case IRQ_MODE_IRQ7654:
  494. /* select IRQ mode for IRL7-4 */
  495. ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
  496. register_intc_controller(&intc_desc_irq4567);
  497. break;
  498. case IRQ_MODE_IRQ3210:
  499. /* select IRQ mode for IRL3-0 */
  500. ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
  501. register_intc_controller(&intc_desc_irq0123);
  502. break;
  503. case IRQ_MODE_IRL7654:
  504. /* enable IRL7-4 but don't provide any masking */
  505. ctrl_outl(0x40000000, INTC_INTMSKCLR1);
  506. ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
  507. break;
  508. case IRQ_MODE_IRL3210:
  509. /* enable IRL0-3 but don't provide any masking */
  510. ctrl_outl(0x80000000, INTC_INTMSKCLR1);
  511. ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
  512. break;
  513. case IRQ_MODE_IRL7654_MASK:
  514. /* enable IRL7-4 and mask using cpu intc controller */
  515. ctrl_outl(0x40000000, INTC_INTMSKCLR1);
  516. register_intc_controller(&intc_desc_irl4567);
  517. break;
  518. case IRQ_MODE_IRL3210_MASK:
  519. /* enable IRL0-3 and mask using cpu intc controller */
  520. ctrl_outl(0x80000000, INTC_INTMSKCLR1);
  521. register_intc_controller(&intc_desc_irl0123);
  522. break;
  523. default:
  524. BUG();
  525. }
  526. }
  527. void __init plat_mem_setup(void)
  528. {
  529. /* Register the URAM space as Node 1 */
  530. setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
  531. }