setup-sh7770.c 18 KB

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  1. /*
  2. * SH7770 Setup
  3. *
  4. * Copyright (C) 2006 - 2008 Paul Mundt
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/platform_device.h>
  11. #include <linux/init.h>
  12. #include <linux/serial.h>
  13. #include <linux/serial_sci.h>
  14. #include <linux/sh_timer.h>
  15. #include <linux/io.h>
  16. static struct plat_sci_port scif0_platform_data = {
  17. .mapbase = 0xff923000,
  18. .flags = UPF_BOOT_AUTOCONF,
  19. .type = PORT_SCIF,
  20. .irqs = { 61, 61, 61, 61 },
  21. };
  22. static struct platform_device scif0_device = {
  23. .name = "sh-sci",
  24. .id = 0,
  25. .dev = {
  26. .platform_data = &scif0_platform_data,
  27. },
  28. };
  29. static struct plat_sci_port scif1_platform_data = {
  30. .mapbase = 0xff924000,
  31. .flags = UPF_BOOT_AUTOCONF,
  32. .type = PORT_SCIF,
  33. .irqs = { 62, 62, 62, 62 },
  34. };
  35. static struct platform_device scif1_device = {
  36. .name = "sh-sci",
  37. .id = 1,
  38. .dev = {
  39. .platform_data = &scif1_platform_data,
  40. },
  41. };
  42. static struct plat_sci_port scif2_platform_data = {
  43. .mapbase = 0xff925000,
  44. .flags = UPF_BOOT_AUTOCONF,
  45. .type = PORT_SCIF,
  46. .irqs = { 63, 63, 63, 63 },
  47. };
  48. static struct platform_device scif2_device = {
  49. .name = "sh-sci",
  50. .id = 2,
  51. .dev = {
  52. .platform_data = &scif2_platform_data,
  53. },
  54. };
  55. static struct plat_sci_port scif3_platform_data = {
  56. .mapbase = 0xff926000,
  57. .flags = UPF_BOOT_AUTOCONF,
  58. .type = PORT_SCIF,
  59. .irqs = { 64, 64, 64, 64 },
  60. };
  61. static struct platform_device scif3_device = {
  62. .name = "sh-sci",
  63. .id = 3,
  64. .dev = {
  65. .platform_data = &scif3_platform_data,
  66. },
  67. };
  68. static struct plat_sci_port scif4_platform_data = {
  69. .mapbase = 0xff927000,
  70. .flags = UPF_BOOT_AUTOCONF,
  71. .type = PORT_SCIF,
  72. .irqs = { 65, 65, 65, 65 },
  73. };
  74. static struct platform_device scif4_device = {
  75. .name = "sh-sci",
  76. .id = 4,
  77. .dev = {
  78. .platform_data = &scif4_platform_data,
  79. },
  80. };
  81. static struct plat_sci_port scif5_platform_data = {
  82. .mapbase = 0xff928000,
  83. .flags = UPF_BOOT_AUTOCONF,
  84. .type = PORT_SCIF,
  85. .irqs = { 66, 66, 66, 66 },
  86. };
  87. static struct platform_device scif5_device = {
  88. .name = "sh-sci",
  89. .id = 5,
  90. .dev = {
  91. .platform_data = &scif5_platform_data,
  92. },
  93. };
  94. static struct plat_sci_port scif6_platform_data = {
  95. .mapbase = 0xff929000,
  96. .flags = UPF_BOOT_AUTOCONF,
  97. .type = PORT_SCIF,
  98. .irqs = { 67, 67, 67, 67 },
  99. };
  100. static struct platform_device scif6_device = {
  101. .name = "sh-sci",
  102. .id = 6,
  103. .dev = {
  104. .platform_data = &scif6_platform_data,
  105. },
  106. };
  107. static struct plat_sci_port scif7_platform_data = {
  108. .mapbase = 0xff92a000,
  109. .flags = UPF_BOOT_AUTOCONF,
  110. .type = PORT_SCIF,
  111. .irqs = { 68, 68, 68, 68 },
  112. };
  113. static struct platform_device scif7_device = {
  114. .name = "sh-sci",
  115. .id = 7,
  116. .dev = {
  117. .platform_data = &scif7_platform_data,
  118. },
  119. };
  120. static struct plat_sci_port scif8_platform_data = {
  121. .mapbase = 0xff92b000,
  122. .flags = UPF_BOOT_AUTOCONF,
  123. .type = PORT_SCIF,
  124. .irqs = { 69, 69, 69, 69 },
  125. };
  126. static struct platform_device scif8_device = {
  127. .name = "sh-sci",
  128. .id = 8,
  129. .dev = {
  130. .platform_data = &scif8_platform_data,
  131. },
  132. };
  133. static struct plat_sci_port scif9_platform_data = {
  134. .mapbase = 0xff92c000,
  135. .flags = UPF_BOOT_AUTOCONF,
  136. .type = PORT_SCIF,
  137. .irqs = { 70, 70, 70, 70 },
  138. };
  139. static struct platform_device scif9_device = {
  140. .name = "sh-sci",
  141. .id = 9,
  142. .dev = {
  143. .platform_data = &scif9_platform_data,
  144. },
  145. };
  146. static struct sh_timer_config tmu0_platform_data = {
  147. .name = "TMU0",
  148. .channel_offset = 0x04,
  149. .timer_bit = 0,
  150. .clk = "peripheral_clk",
  151. .clockevent_rating = 200,
  152. };
  153. static struct resource tmu0_resources[] = {
  154. [0] = {
  155. .name = "TMU0",
  156. .start = 0xffd80008,
  157. .end = 0xffd80013,
  158. .flags = IORESOURCE_MEM,
  159. },
  160. [1] = {
  161. .start = 16,
  162. .flags = IORESOURCE_IRQ,
  163. },
  164. };
  165. static struct platform_device tmu0_device = {
  166. .name = "sh_tmu",
  167. .id = 0,
  168. .dev = {
  169. .platform_data = &tmu0_platform_data,
  170. },
  171. .resource = tmu0_resources,
  172. .num_resources = ARRAY_SIZE(tmu0_resources),
  173. };
  174. static struct sh_timer_config tmu1_platform_data = {
  175. .name = "TMU1",
  176. .channel_offset = 0x10,
  177. .timer_bit = 1,
  178. .clk = "peripheral_clk",
  179. .clocksource_rating = 200,
  180. };
  181. static struct resource tmu1_resources[] = {
  182. [0] = {
  183. .name = "TMU1",
  184. .start = 0xffd80014,
  185. .end = 0xffd8001f,
  186. .flags = IORESOURCE_MEM,
  187. },
  188. [1] = {
  189. .start = 17,
  190. .flags = IORESOURCE_IRQ,
  191. },
  192. };
  193. static struct platform_device tmu1_device = {
  194. .name = "sh_tmu",
  195. .id = 1,
  196. .dev = {
  197. .platform_data = &tmu1_platform_data,
  198. },
  199. .resource = tmu1_resources,
  200. .num_resources = ARRAY_SIZE(tmu1_resources),
  201. };
  202. static struct sh_timer_config tmu2_platform_data = {
  203. .name = "TMU2",
  204. .channel_offset = 0x1c,
  205. .timer_bit = 2,
  206. .clk = "peripheral_clk",
  207. };
  208. static struct resource tmu2_resources[] = {
  209. [0] = {
  210. .name = "TMU2",
  211. .start = 0xffd80020,
  212. .end = 0xffd8002f,
  213. .flags = IORESOURCE_MEM,
  214. },
  215. [1] = {
  216. .start = 18,
  217. .flags = IORESOURCE_IRQ,
  218. },
  219. };
  220. static struct platform_device tmu2_device = {
  221. .name = "sh_tmu",
  222. .id = 2,
  223. .dev = {
  224. .platform_data = &tmu2_platform_data,
  225. },
  226. .resource = tmu2_resources,
  227. .num_resources = ARRAY_SIZE(tmu2_resources),
  228. };
  229. static struct sh_timer_config tmu3_platform_data = {
  230. .name = "TMU3",
  231. .channel_offset = 0x04,
  232. .timer_bit = 0,
  233. .clk = "peripheral_clk",
  234. };
  235. static struct resource tmu3_resources[] = {
  236. [0] = {
  237. .name = "TMU3",
  238. .start = 0xffd81008,
  239. .end = 0xffd81013,
  240. .flags = IORESOURCE_MEM,
  241. },
  242. [1] = {
  243. .start = 19,
  244. .flags = IORESOURCE_IRQ,
  245. },
  246. };
  247. static struct platform_device tmu3_device = {
  248. .name = "sh_tmu",
  249. .id = 3,
  250. .dev = {
  251. .platform_data = &tmu3_platform_data,
  252. },
  253. .resource = tmu3_resources,
  254. .num_resources = ARRAY_SIZE(tmu3_resources),
  255. };
  256. static struct sh_timer_config tmu4_platform_data = {
  257. .name = "TMU4",
  258. .channel_offset = 0x10,
  259. .timer_bit = 1,
  260. .clk = "peripheral_clk",
  261. };
  262. static struct resource tmu4_resources[] = {
  263. [0] = {
  264. .name = "TMU4",
  265. .start = 0xffd81014,
  266. .end = 0xffd8101f,
  267. .flags = IORESOURCE_MEM,
  268. },
  269. [1] = {
  270. .start = 20,
  271. .flags = IORESOURCE_IRQ,
  272. },
  273. };
  274. static struct platform_device tmu4_device = {
  275. .name = "sh_tmu",
  276. .id = 4,
  277. .dev = {
  278. .platform_data = &tmu4_platform_data,
  279. },
  280. .resource = tmu4_resources,
  281. .num_resources = ARRAY_SIZE(tmu4_resources),
  282. };
  283. static struct sh_timer_config tmu5_platform_data = {
  284. .name = "TMU5",
  285. .channel_offset = 0x1c,
  286. .timer_bit = 2,
  287. .clk = "peripheral_clk",
  288. };
  289. static struct resource tmu5_resources[] = {
  290. [0] = {
  291. .name = "TMU5",
  292. .start = 0xffd81020,
  293. .end = 0xffd8102f,
  294. .flags = IORESOURCE_MEM,
  295. },
  296. [1] = {
  297. .start = 21,
  298. .flags = IORESOURCE_IRQ,
  299. },
  300. };
  301. static struct platform_device tmu5_device = {
  302. .name = "sh_tmu",
  303. .id = 5,
  304. .dev = {
  305. .platform_data = &tmu5_platform_data,
  306. },
  307. .resource = tmu5_resources,
  308. .num_resources = ARRAY_SIZE(tmu5_resources),
  309. };
  310. static struct sh_timer_config tmu6_platform_data = {
  311. .name = "TMU6",
  312. .channel_offset = 0x04,
  313. .timer_bit = 0,
  314. .clk = "peripheral_clk",
  315. };
  316. static struct resource tmu6_resources[] = {
  317. [0] = {
  318. .name = "TMU6",
  319. .start = 0xffd82008,
  320. .end = 0xffd82013,
  321. .flags = IORESOURCE_MEM,
  322. },
  323. [1] = {
  324. .start = 22,
  325. .flags = IORESOURCE_IRQ,
  326. },
  327. };
  328. static struct platform_device tmu6_device = {
  329. .name = "sh_tmu",
  330. .id = 6,
  331. .dev = {
  332. .platform_data = &tmu6_platform_data,
  333. },
  334. .resource = tmu6_resources,
  335. .num_resources = ARRAY_SIZE(tmu6_resources),
  336. };
  337. static struct sh_timer_config tmu7_platform_data = {
  338. .name = "TMU7",
  339. .channel_offset = 0x10,
  340. .timer_bit = 1,
  341. .clk = "peripheral_clk",
  342. };
  343. static struct resource tmu7_resources[] = {
  344. [0] = {
  345. .name = "TMU7",
  346. .start = 0xffd82014,
  347. .end = 0xffd8201f,
  348. .flags = IORESOURCE_MEM,
  349. },
  350. [1] = {
  351. .start = 23,
  352. .flags = IORESOURCE_IRQ,
  353. },
  354. };
  355. static struct platform_device tmu7_device = {
  356. .name = "sh_tmu",
  357. .id = 7,
  358. .dev = {
  359. .platform_data = &tmu7_platform_data,
  360. },
  361. .resource = tmu7_resources,
  362. .num_resources = ARRAY_SIZE(tmu7_resources),
  363. };
  364. static struct sh_timer_config tmu8_platform_data = {
  365. .name = "TMU8",
  366. .channel_offset = 0x1c,
  367. .timer_bit = 2,
  368. .clk = "peripheral_clk",
  369. };
  370. static struct resource tmu8_resources[] = {
  371. [0] = {
  372. .name = "TMU8",
  373. .start = 0xffd82020,
  374. .end = 0xffd8202b,
  375. .flags = IORESOURCE_MEM,
  376. },
  377. [1] = {
  378. .start = 24,
  379. .flags = IORESOURCE_IRQ,
  380. },
  381. };
  382. static struct platform_device tmu8_device = {
  383. .name = "sh_tmu",
  384. .id = 8,
  385. .dev = {
  386. .platform_data = &tmu8_platform_data,
  387. },
  388. .resource = tmu8_resources,
  389. .num_resources = ARRAY_SIZE(tmu8_resources),
  390. };
  391. static struct platform_device *sh7770_devices[] __initdata = {
  392. &scif0_device,
  393. &scif1_device,
  394. &scif2_device,
  395. &scif3_device,
  396. &scif4_device,
  397. &scif5_device,
  398. &scif6_device,
  399. &scif7_device,
  400. &scif8_device,
  401. &scif9_device,
  402. &tmu0_device,
  403. &tmu1_device,
  404. &tmu2_device,
  405. &tmu3_device,
  406. &tmu4_device,
  407. &tmu5_device,
  408. &tmu6_device,
  409. &tmu7_device,
  410. &tmu8_device,
  411. };
  412. static int __init sh7770_devices_setup(void)
  413. {
  414. return platform_add_devices(sh7770_devices,
  415. ARRAY_SIZE(sh7770_devices));
  416. }
  417. arch_initcall(sh7770_devices_setup);
  418. static struct platform_device *sh7770_early_devices[] __initdata = {
  419. &scif0_device,
  420. &scif1_device,
  421. &scif2_device,
  422. &scif3_device,
  423. &scif4_device,
  424. &scif5_device,
  425. &scif6_device,
  426. &scif7_device,
  427. &scif8_device,
  428. &scif9_device,
  429. &tmu0_device,
  430. &tmu1_device,
  431. &tmu2_device,
  432. &tmu3_device,
  433. &tmu4_device,
  434. &tmu5_device,
  435. &tmu6_device,
  436. &tmu7_device,
  437. &tmu8_device,
  438. };
  439. void __init plat_early_device_setup(void)
  440. {
  441. early_platform_add_devices(sh7770_early_devices,
  442. ARRAY_SIZE(sh7770_early_devices));
  443. }
  444. enum {
  445. UNUSED = 0,
  446. /* interrupt sources */
  447. IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
  448. IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
  449. IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
  450. IRL_HHLL, IRL_HHLH, IRL_HHHL,
  451. IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
  452. GPIO,
  453. TMU0, TMU1, TMU2, TMU2_TICPI,
  454. TMU3, TMU4, TMU5, TMU5_TICPI,
  455. TMU6, TMU7, TMU8,
  456. HAC, IPI, SPDIF, HUDI, I2C,
  457. DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
  458. I2S0, I2S1, I2S2, I2S3,
  459. SRC_RX, SRC_TX, SRC_SPDIF,
  460. DU, VIDEO_IN, REMOTE, YUV, USB, ATAPI, CAN, GPS, GFX2D,
  461. GFX3D_MBX, GFX3D_DMAC,
  462. EXBUS_ATA,
  463. SPI0, SPI1,
  464. SCIF089, SCIF1234, SCIF567,
  465. ADC,
  466. BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
  467. BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
  468. BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31,
  469. /* interrupt groups */
  470. TMU, DMAC, I2S, SRC, GFX3D, SPI, SCIF, BBDMAC,
  471. };
  472. static struct intc_vect vectors[] __initdata = {
  473. INTC_VECT(GPIO, 0x3e0),
  474. INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
  475. INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
  476. INTC_VECT(TMU3, 0x480), INTC_VECT(TMU4, 0x4a0),
  477. INTC_VECT(TMU5, 0x4c0), INTC_VECT(TMU5_TICPI, 0x4e0),
  478. INTC_VECT(TMU6, 0x500), INTC_VECT(TMU7, 0x520),
  479. INTC_VECT(TMU8, 0x540),
  480. INTC_VECT(HAC, 0x580), INTC_VECT(IPI, 0x5c0),
  481. INTC_VECT(SPDIF, 0x5e0),
  482. INTC_VECT(HUDI, 0x600), INTC_VECT(I2C, 0x620),
  483. INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
  484. INTC_VECT(DMAC0_DMINT2, 0x680),
  485. INTC_VECT(I2S0, 0x6a0), INTC_VECT(I2S1, 0x6c0),
  486. INTC_VECT(I2S2, 0x6e0), INTC_VECT(I2S3, 0x700),
  487. INTC_VECT(SRC_RX, 0x720), INTC_VECT(SRC_TX, 0x740),
  488. INTC_VECT(SRC_SPDIF, 0x760),
  489. INTC_VECT(DU, 0x780), INTC_VECT(VIDEO_IN, 0x7a0),
  490. INTC_VECT(REMOTE, 0x7c0), INTC_VECT(YUV, 0x7e0),
  491. INTC_VECT(USB, 0x840), INTC_VECT(ATAPI, 0x860),
  492. INTC_VECT(CAN, 0x880), INTC_VECT(GPS, 0x8a0),
  493. INTC_VECT(GFX2D, 0x8c0),
  494. INTC_VECT(GFX3D_MBX, 0x900), INTC_VECT(GFX3D_DMAC, 0x920),
  495. INTC_VECT(EXBUS_ATA, 0x940),
  496. INTC_VECT(SPI0, 0x960), INTC_VECT(SPI1, 0x980),
  497. INTC_VECT(SCIF089, 0x9a0), INTC_VECT(SCIF1234, 0x9c0),
  498. INTC_VECT(SCIF1234, 0x9e0), INTC_VECT(SCIF1234, 0xa00),
  499. INTC_VECT(SCIF1234, 0xa20), INTC_VECT(SCIF567, 0xa40),
  500. INTC_VECT(SCIF567, 0xa60), INTC_VECT(SCIF567, 0xa80),
  501. INTC_VECT(SCIF089, 0xaa0), INTC_VECT(SCIF089, 0xac0),
  502. INTC_VECT(ADC, 0xb20),
  503. INTC_VECT(BBDMAC_0_3, 0xba0), INTC_VECT(BBDMAC_0_3, 0xbc0),
  504. INTC_VECT(BBDMAC_0_3, 0xbe0), INTC_VECT(BBDMAC_0_3, 0xc00),
  505. INTC_VECT(BBDMAC_4_7, 0xc20), INTC_VECT(BBDMAC_4_7, 0xc40),
  506. INTC_VECT(BBDMAC_4_7, 0xc60), INTC_VECT(BBDMAC_4_7, 0xc80),
  507. INTC_VECT(BBDMAC_8_10, 0xca0), INTC_VECT(BBDMAC_8_10, 0xcc0),
  508. INTC_VECT(BBDMAC_8_10, 0xce0), INTC_VECT(BBDMAC_11_14, 0xd00),
  509. INTC_VECT(BBDMAC_11_14, 0xd20), INTC_VECT(BBDMAC_11_14, 0xd40),
  510. INTC_VECT(BBDMAC_11_14, 0xd60), INTC_VECT(BBDMAC_15_18, 0xd80),
  511. INTC_VECT(BBDMAC_15_18, 0xda0), INTC_VECT(BBDMAC_15_18, 0xdc0),
  512. INTC_VECT(BBDMAC_15_18, 0xde0), INTC_VECT(BBDMAC_19_22, 0xe00),
  513. INTC_VECT(BBDMAC_19_22, 0xe20), INTC_VECT(BBDMAC_19_22, 0xe40),
  514. INTC_VECT(BBDMAC_19_22, 0xe60), INTC_VECT(BBDMAC_23_26, 0xe80),
  515. INTC_VECT(BBDMAC_23_26, 0xea0), INTC_VECT(BBDMAC_23_26, 0xec0),
  516. INTC_VECT(BBDMAC_23_26, 0xee0), INTC_VECT(BBDMAC_27, 0xf00),
  517. INTC_VECT(BBDMAC_28, 0xf20), INTC_VECT(BBDMAC_29, 0xf40),
  518. INTC_VECT(BBDMAC_30, 0xf60), INTC_VECT(BBDMAC_31, 0xf80),
  519. };
  520. static struct intc_group groups[] __initdata = {
  521. INTC_GROUP(TMU, TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
  522. TMU5_TICPI, TMU6, TMU7, TMU8),
  523. INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2),
  524. INTC_GROUP(I2S, I2S0, I2S1, I2S2, I2S3),
  525. INTC_GROUP(SRC, SRC_RX, SRC_TX, SRC_SPDIF),
  526. INTC_GROUP(GFX3D, GFX3D_MBX, GFX3D_DMAC),
  527. INTC_GROUP(SPI, SPI0, SPI1),
  528. INTC_GROUP(SCIF, SCIF089, SCIF1234, SCIF567),
  529. INTC_GROUP(BBDMAC,
  530. BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
  531. BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
  532. BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31),
  533. };
  534. static struct intc_mask_reg mask_registers[] __initdata = {
  535. { 0xffe00040, 0xffe00044, 32, /* INT2MSKR / INT2MSKCR */
  536. { 0, BBDMAC, ADC, SCIF, SPI, EXBUS_ATA, GFX3D, GFX2D,
  537. GPS, CAN, ATAPI, USB, YUV, REMOTE, VIDEO_IN, DU, SRC, I2S,
  538. DMAC, I2C, HUDI, SPDIF, IPI, HAC, TMU, GPIO } },
  539. };
  540. static struct intc_prio_reg prio_registers[] __initdata = {
  541. { 0xffe00000, 0, 32, 8, /* INT2PRI0 */ { GPIO, TMU0, 0, HAC } },
  542. { 0xffe00004, 0, 32, 8, /* INT2PRI1 */ { IPI, SPDIF, HUDI, I2C } },
  543. { 0xffe00008, 0, 32, 8, /* INT2PRI2 */ { DMAC, I2S, SRC, DU } },
  544. { 0xffe0000c, 0, 32, 8, /* INT2PRI3 */ { VIDEO_IN, REMOTE, YUV, USB } },
  545. { 0xffe00010, 0, 32, 8, /* INT2PRI4 */ { ATAPI, CAN, GPS, GFX2D } },
  546. { 0xffe00014, 0, 32, 8, /* INT2PRI5 */ { 0, GFX3D, EXBUS_ATA, SPI } },
  547. { 0xffe00018, 0, 32, 8, /* INT2PRI6 */ { SCIF1234, SCIF567, SCIF089 } },
  548. { 0xffe0001c, 0, 32, 8, /* INT2PRI7 */ { ADC, 0, 0, BBDMAC_0_3 } },
  549. { 0xffe00020, 0, 32, 8, /* INT2PRI8 */
  550. { BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14, BBDMAC_15_18 } },
  551. { 0xffe00024, 0, 32, 8, /* INT2PRI9 */
  552. { BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27, BBDMAC_28 } },
  553. { 0xffe00028, 0, 32, 8, /* INT2PRI10 */
  554. { BBDMAC_29, BBDMAC_30, BBDMAC_31 } },
  555. { 0xffe0002c, 0, 32, 8, /* INT2PRI11 */
  556. { TMU1, TMU2, TMU2_TICPI, TMU3 } },
  557. { 0xffe00030, 0, 32, 8, /* INT2PRI12 */
  558. { TMU4, TMU5, TMU5_TICPI, TMU6 } },
  559. { 0xffe00034, 0, 32, 8, /* INT2PRI13 */
  560. { TMU7, TMU8 } },
  561. };
  562. static DECLARE_INTC_DESC(intc_desc, "sh7770", vectors, groups,
  563. mask_registers, prio_registers, NULL);
  564. /* Support for external interrupt pins in IRQ mode */
  565. static struct intc_vect irq_vectors[] __initdata = {
  566. INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
  567. INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
  568. INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
  569. };
  570. static struct intc_mask_reg irq_mask_registers[] __initdata = {
  571. { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
  572. { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, } },
  573. };
  574. static struct intc_prio_reg irq_prio_registers[] __initdata = {
  575. { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
  576. IRQ4, IRQ5, } },
  577. };
  578. static struct intc_sense_reg irq_sense_registers[] __initdata = {
  579. { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
  580. IRQ4, IRQ5, } },
  581. };
  582. static DECLARE_INTC_DESC(intc_irq_desc, "sh7770-irq", irq_vectors,
  583. NULL, irq_mask_registers, irq_prio_registers,
  584. irq_sense_registers);
  585. /* External interrupt pins in IRL mode */
  586. static struct intc_vect irl_vectors[] __initdata = {
  587. INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
  588. INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
  589. INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
  590. INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
  591. INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
  592. INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
  593. INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
  594. INTC_VECT(IRL_HHHL, 0x3c0),
  595. };
  596. static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
  597. { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
  598. { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
  599. IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
  600. IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
  601. IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
  602. };
  603. static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
  604. { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
  605. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  606. IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
  607. IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
  608. IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
  609. IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
  610. };
  611. static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
  612. NULL, irl7654_mask_registers, NULL, NULL);
  613. static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
  614. NULL, irl3210_mask_registers, NULL, NULL);
  615. #define INTC_ICR0 0xffd00000
  616. #define INTC_INTMSK0 0xffd00044
  617. #define INTC_INTMSK1 0xffd00048
  618. #define INTC_INTMSK2 0xffd40080
  619. #define INTC_INTMSKCLR1 0xffd00068
  620. #define INTC_INTMSKCLR2 0xffd40084
  621. void __init plat_irq_setup(void)
  622. {
  623. /* disable IRQ7-0 */
  624. ctrl_outl(0xff000000, INTC_INTMSK0);
  625. /* disable IRL3-0 + IRL7-4 */
  626. ctrl_outl(0xc0000000, INTC_INTMSK1);
  627. ctrl_outl(0xfffefffe, INTC_INTMSK2);
  628. /* select IRL mode for IRL3-0 + IRL7-4 */
  629. ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
  630. /* disable holding function, ie enable "SH-4 Mode" */
  631. ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
  632. register_intc_controller(&intc_desc);
  633. }
  634. void __init plat_irq_setup_pins(int mode)
  635. {
  636. switch (mode) {
  637. case IRQ_MODE_IRQ:
  638. /* select IRQ mode for IRL3-0 + IRL7-4 */
  639. ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
  640. register_intc_controller(&intc_irq_desc);
  641. break;
  642. case IRQ_MODE_IRL7654:
  643. /* enable IRL7-4 but don't provide any masking */
  644. ctrl_outl(0x40000000, INTC_INTMSKCLR1);
  645. ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
  646. break;
  647. case IRQ_MODE_IRL3210:
  648. /* enable IRL0-3 but don't provide any masking */
  649. ctrl_outl(0x80000000, INTC_INTMSKCLR1);
  650. ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
  651. break;
  652. case IRQ_MODE_IRL7654_MASK:
  653. /* enable IRL7-4 and mask using cpu intc controller */
  654. ctrl_outl(0x40000000, INTC_INTMSKCLR1);
  655. register_intc_controller(&intc_irl7654_desc);
  656. break;
  657. case IRQ_MODE_IRL3210_MASK:
  658. /* enable IRL0-3 and mask using cpu intc controller */
  659. ctrl_outl(0x80000000, INTC_INTMSKCLR1);
  660. register_intc_controller(&intc_irl3210_desc);
  661. break;
  662. default:
  663. BUG();
  664. }
  665. }