setup-sh7343.c 13 KB

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  1. /*
  2. * SH7343 Setup
  3. *
  4. * Copyright (C) 2006 Paul Mundt
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/platform_device.h>
  11. #include <linux/init.h>
  12. #include <linux/serial.h>
  13. #include <linux/serial_sci.h>
  14. #include <linux/uio_driver.h>
  15. #include <linux/sh_timer.h>
  16. #include <asm/clock.h>
  17. /* Serial */
  18. static struct plat_sci_port scif0_platform_data = {
  19. .mapbase = 0xffe00000,
  20. .flags = UPF_BOOT_AUTOCONF,
  21. .type = PORT_SCIF,
  22. .irqs = { 80, 80, 80, 80 },
  23. .clk = "scif0",
  24. };
  25. static struct platform_device scif0_device = {
  26. .name = "sh-sci",
  27. .id = 0,
  28. .dev = {
  29. .platform_data = &scif0_platform_data,
  30. },
  31. };
  32. static struct plat_sci_port scif1_platform_data = {
  33. .mapbase = 0xffe10000,
  34. .flags = UPF_BOOT_AUTOCONF,
  35. .type = PORT_SCIF,
  36. .irqs = { 81, 81, 81, 81 },
  37. .clk = "scif1",
  38. };
  39. static struct platform_device scif1_device = {
  40. .name = "sh-sci",
  41. .id = 1,
  42. .dev = {
  43. .platform_data = &scif1_platform_data,
  44. },
  45. };
  46. static struct plat_sci_port scif2_platform_data = {
  47. .mapbase = 0xffe20000,
  48. .flags = UPF_BOOT_AUTOCONF,
  49. .type = PORT_SCIF,
  50. .irqs = { 82, 82, 82, 82 },
  51. .clk = "scif2",
  52. };
  53. static struct platform_device scif2_device = {
  54. .name = "sh-sci",
  55. .id = 2,
  56. .dev = {
  57. .platform_data = &scif2_platform_data,
  58. },
  59. };
  60. static struct plat_sci_port scif3_platform_data = {
  61. .mapbase = 0xffe30000,
  62. .flags = UPF_BOOT_AUTOCONF,
  63. .type = PORT_SCIF,
  64. .irqs = { 83, 83, 83, 83 },
  65. .clk = "scif3",
  66. };
  67. static struct platform_device scif3_device = {
  68. .name = "sh-sci",
  69. .id = 3,
  70. .dev = {
  71. .platform_data = &scif3_platform_data,
  72. },
  73. };
  74. static struct resource iic0_resources[] = {
  75. [0] = {
  76. .name = "IIC0",
  77. .start = 0x04470000,
  78. .end = 0x04470017,
  79. .flags = IORESOURCE_MEM,
  80. },
  81. [1] = {
  82. .start = 96,
  83. .end = 99,
  84. .flags = IORESOURCE_IRQ,
  85. },
  86. };
  87. static struct platform_device iic0_device = {
  88. .name = "i2c-sh_mobile",
  89. .id = 0, /* "i2c0" clock */
  90. .num_resources = ARRAY_SIZE(iic0_resources),
  91. .resource = iic0_resources,
  92. };
  93. static struct resource iic1_resources[] = {
  94. [0] = {
  95. .name = "IIC1",
  96. .start = 0x04750000,
  97. .end = 0x04750017,
  98. .flags = IORESOURCE_MEM,
  99. },
  100. [1] = {
  101. .start = 44,
  102. .end = 47,
  103. .flags = IORESOURCE_IRQ,
  104. },
  105. };
  106. static struct platform_device iic1_device = {
  107. .name = "i2c-sh_mobile",
  108. .id = 1, /* "i2c1" clock */
  109. .num_resources = ARRAY_SIZE(iic1_resources),
  110. .resource = iic1_resources,
  111. };
  112. static struct uio_info vpu_platform_data = {
  113. .name = "VPU4",
  114. .version = "0",
  115. .irq = 60,
  116. };
  117. static struct resource vpu_resources[] = {
  118. [0] = {
  119. .name = "VPU",
  120. .start = 0xfe900000,
  121. .end = 0xfe9022eb,
  122. .flags = IORESOURCE_MEM,
  123. },
  124. [1] = {
  125. /* place holder for contiguous memory */
  126. },
  127. };
  128. static struct platform_device vpu_device = {
  129. .name = "uio_pdrv_genirq",
  130. .id = 0,
  131. .dev = {
  132. .platform_data = &vpu_platform_data,
  133. },
  134. .resource = vpu_resources,
  135. .num_resources = ARRAY_SIZE(vpu_resources),
  136. };
  137. static struct uio_info veu_platform_data = {
  138. .name = "VEU",
  139. .version = "0",
  140. .irq = 54,
  141. };
  142. static struct resource veu_resources[] = {
  143. [0] = {
  144. .name = "VEU",
  145. .start = 0xfe920000,
  146. .end = 0xfe9200b7,
  147. .flags = IORESOURCE_MEM,
  148. },
  149. [1] = {
  150. /* place holder for contiguous memory */
  151. },
  152. };
  153. static struct platform_device veu_device = {
  154. .name = "uio_pdrv_genirq",
  155. .id = 1,
  156. .dev = {
  157. .platform_data = &veu_platform_data,
  158. },
  159. .resource = veu_resources,
  160. .num_resources = ARRAY_SIZE(veu_resources),
  161. };
  162. static struct uio_info jpu_platform_data = {
  163. .name = "JPU",
  164. .version = "0",
  165. .irq = 27,
  166. };
  167. static struct resource jpu_resources[] = {
  168. [0] = {
  169. .name = "JPU",
  170. .start = 0xfea00000,
  171. .end = 0xfea102d3,
  172. .flags = IORESOURCE_MEM,
  173. },
  174. [1] = {
  175. /* place holder for contiguous memory */
  176. },
  177. };
  178. static struct platform_device jpu_device = {
  179. .name = "uio_pdrv_genirq",
  180. .id = 2,
  181. .dev = {
  182. .platform_data = &jpu_platform_data,
  183. },
  184. .resource = jpu_resources,
  185. .num_resources = ARRAY_SIZE(jpu_resources),
  186. };
  187. static struct sh_timer_config cmt_platform_data = {
  188. .name = "CMT",
  189. .channel_offset = 0x60,
  190. .timer_bit = 5,
  191. .clk = "cmt0",
  192. .clockevent_rating = 125,
  193. .clocksource_rating = 200,
  194. };
  195. static struct resource cmt_resources[] = {
  196. [0] = {
  197. .name = "CMT",
  198. .start = 0x044a0060,
  199. .end = 0x044a006b,
  200. .flags = IORESOURCE_MEM,
  201. },
  202. [1] = {
  203. .start = 104,
  204. .flags = IORESOURCE_IRQ,
  205. },
  206. };
  207. static struct platform_device cmt_device = {
  208. .name = "sh_cmt",
  209. .id = 0,
  210. .dev = {
  211. .platform_data = &cmt_platform_data,
  212. },
  213. .resource = cmt_resources,
  214. .num_resources = ARRAY_SIZE(cmt_resources),
  215. };
  216. static struct sh_timer_config tmu0_platform_data = {
  217. .name = "TMU0",
  218. .channel_offset = 0x04,
  219. .timer_bit = 0,
  220. .clk = "tmu0",
  221. .clockevent_rating = 200,
  222. };
  223. static struct resource tmu0_resources[] = {
  224. [0] = {
  225. .name = "TMU0",
  226. .start = 0xffd80008,
  227. .end = 0xffd80013,
  228. .flags = IORESOURCE_MEM,
  229. },
  230. [1] = {
  231. .start = 16,
  232. .flags = IORESOURCE_IRQ,
  233. },
  234. };
  235. static struct platform_device tmu0_device = {
  236. .name = "sh_tmu",
  237. .id = 0,
  238. .dev = {
  239. .platform_data = &tmu0_platform_data,
  240. },
  241. .resource = tmu0_resources,
  242. .num_resources = ARRAY_SIZE(tmu0_resources),
  243. };
  244. static struct sh_timer_config tmu1_platform_data = {
  245. .name = "TMU1",
  246. .channel_offset = 0x10,
  247. .timer_bit = 1,
  248. .clk = "tmu0",
  249. .clocksource_rating = 200,
  250. };
  251. static struct resource tmu1_resources[] = {
  252. [0] = {
  253. .name = "TMU1",
  254. .start = 0xffd80014,
  255. .end = 0xffd8001f,
  256. .flags = IORESOURCE_MEM,
  257. },
  258. [1] = {
  259. .start = 17,
  260. .flags = IORESOURCE_IRQ,
  261. },
  262. };
  263. static struct platform_device tmu1_device = {
  264. .name = "sh_tmu",
  265. .id = 1,
  266. .dev = {
  267. .platform_data = &tmu1_platform_data,
  268. },
  269. .resource = tmu1_resources,
  270. .num_resources = ARRAY_SIZE(tmu1_resources),
  271. };
  272. static struct sh_timer_config tmu2_platform_data = {
  273. .name = "TMU2",
  274. .channel_offset = 0x1c,
  275. .timer_bit = 2,
  276. .clk = "tmu0",
  277. };
  278. static struct resource tmu2_resources[] = {
  279. [0] = {
  280. .name = "TMU2",
  281. .start = 0xffd80020,
  282. .end = 0xffd8002b,
  283. .flags = IORESOURCE_MEM,
  284. },
  285. [1] = {
  286. .start = 18,
  287. .flags = IORESOURCE_IRQ,
  288. },
  289. };
  290. static struct platform_device tmu2_device = {
  291. .name = "sh_tmu",
  292. .id = 2,
  293. .dev = {
  294. .platform_data = &tmu2_platform_data,
  295. },
  296. .resource = tmu2_resources,
  297. .num_resources = ARRAY_SIZE(tmu2_resources),
  298. };
  299. static struct platform_device *sh7343_devices[] __initdata = {
  300. &scif0_device,
  301. &scif1_device,
  302. &scif2_device,
  303. &scif3_device,
  304. &cmt_device,
  305. &tmu0_device,
  306. &tmu1_device,
  307. &tmu2_device,
  308. &iic0_device,
  309. &iic1_device,
  310. &vpu_device,
  311. &veu_device,
  312. &jpu_device,
  313. };
  314. static int __init sh7343_devices_setup(void)
  315. {
  316. platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
  317. platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
  318. platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
  319. return platform_add_devices(sh7343_devices,
  320. ARRAY_SIZE(sh7343_devices));
  321. }
  322. arch_initcall(sh7343_devices_setup);
  323. static struct platform_device *sh7343_early_devices[] __initdata = {
  324. &scif0_device,
  325. &scif1_device,
  326. &scif2_device,
  327. &scif3_device,
  328. &cmt_device,
  329. &tmu0_device,
  330. &tmu1_device,
  331. &tmu2_device,
  332. };
  333. void __init plat_early_device_setup(void)
  334. {
  335. early_platform_add_devices(sh7343_early_devices,
  336. ARRAY_SIZE(sh7343_early_devices));
  337. }
  338. enum {
  339. UNUSED = 0,
  340. /* interrupt sources */
  341. IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  342. DMAC0, DMAC1, DMAC2, DMAC3,
  343. VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
  344. MFI, VPU, TPU, Z3D4, USBI0, USBI1,
  345. MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY,
  346. DMAC4, DMAC5, DMAC_DADERR,
  347. KEYSC,
  348. SCIF, SCIF1, SCIF2, SCIF3,
  349. SIOF0, SIOF1, SIO,
  350. FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
  351. I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
  352. I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
  353. SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI,
  354. IRDA,
  355. SDHI0, SDHI1, SDHI2, SDHI3,
  356. CMT, TSIF, SIU,
  357. TMU0, TMU1, TMU2,
  358. JPU, LCDC,
  359. /* interrupt groups */
  360. DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, SDHI, USB,
  361. };
  362. static struct intc_vect vectors[] __initdata = {
  363. INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
  364. INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
  365. INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
  366. INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
  367. INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0),
  368. INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0),
  369. INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
  370. INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
  371. INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
  372. INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
  373. INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980),
  374. INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0),
  375. INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40),
  376. INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20),
  377. INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60),
  378. INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
  379. INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
  380. INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20),
  381. INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60),
  382. INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0),
  383. INTC_VECT(SIO, 0xd00),
  384. INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
  385. INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
  386. INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
  387. INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
  388. INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
  389. INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
  390. INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
  391. INTC_VECT(SIU, 0xf80),
  392. INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
  393. INTC_VECT(TMU2, 0x440),
  394. INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
  395. };
  396. static struct intc_group groups[] __initdata = {
  397. INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
  398. INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
  399. INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR),
  400. INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
  401. INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
  402. FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
  403. INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
  404. INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
  405. INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI),
  406. INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
  407. INTC_GROUP(USB, USBI0, USBI1),
  408. };
  409. static struct intc_mask_reg mask_registers[] __initdata = {
  410. { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
  411. { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
  412. { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
  413. { 0, 0, 0, VPU, 0, 0, 0, MFI } },
  414. { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
  415. { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
  416. { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
  417. { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
  418. { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
  419. { KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } },
  420. { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
  421. { 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } },
  422. { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
  423. { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
  424. FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
  425. { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
  426. { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } },
  427. { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
  428. { 0, 0, 0, CMT, 0, USBI1, USBI0 } },
  429. { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
  430. { MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } },
  431. { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
  432. { I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } },
  433. { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
  434. { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
  435. };
  436. static struct intc_prio_reg prio_registers[] __initdata = {
  437. { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
  438. { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
  439. { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
  440. { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
  441. { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } },
  442. { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } },
  443. { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } },
  444. { 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } },
  445. { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
  446. { 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } },
  447. { 0xa4140010, 0, 32, 4, /* INTPRI00 */
  448. { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
  449. };
  450. static struct intc_sense_reg sense_registers[] __initdata = {
  451. { 0xa414001c, 16, 2, /* ICR1 */
  452. { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
  453. };
  454. static struct intc_mask_reg ack_registers[] __initdata = {
  455. { 0xa4140024, 0, 8, /* INTREQ00 */
  456. { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
  457. };
  458. static DECLARE_INTC_DESC_ACK(intc_desc, "sh7343", vectors, groups,
  459. mask_registers, prio_registers, sense_registers,
  460. ack_registers);
  461. void __init plat_irq_setup(void)
  462. {
  463. register_intc_controller(&intc_desc);
  464. }