setup-sh7760.c 8.4 KB

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  1. /*
  2. * SH7760 Setup
  3. *
  4. * Copyright (C) 2006 Paul Mundt
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/platform_device.h>
  11. #include <linux/init.h>
  12. #include <linux/serial.h>
  13. #include <linux/sh_timer.h>
  14. #include <linux/serial_sci.h>
  15. #include <linux/io.h>
  16. enum {
  17. UNUSED = 0,
  18. /* interrupt sources */
  19. IRL0, IRL1, IRL2, IRL3,
  20. HUDI, GPIOI, DMAC,
  21. IRQ4, IRQ5, IRQ6, IRQ7,
  22. HCAN20, HCAN21,
  23. SSI0, SSI1,
  24. HAC0, HAC1,
  25. I2C0, I2C1,
  26. USB, LCDC,
  27. DMABRG0, DMABRG1, DMABRG2,
  28. SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
  29. SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
  30. SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
  31. SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
  32. HSPI,
  33. MMCIF0, MMCIF1, MMCIF2, MMCIF3,
  34. MFI, ADC, CMT,
  35. TMU0, TMU1, TMU2,
  36. WDT, REF,
  37. /* interrupt groups */
  38. DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF,
  39. };
  40. static struct intc_vect vectors[] __initdata = {
  41. INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
  42. INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
  43. INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
  44. INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
  45. INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
  46. INTC_VECT(DMAC, 0x6c0),
  47. INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
  48. INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
  49. INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
  50. INTC_VECT(SSI0, 0x940), INTC_VECT(SSI1, 0x960),
  51. INTC_VECT(HAC0, 0x980), INTC_VECT(HAC1, 0x9a0),
  52. INTC_VECT(I2C0, 0x9c0), INTC_VECT(I2C1, 0x9e0),
  53. INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),
  54. INTC_VECT(DMABRG0, 0xa80), INTC_VECT(DMABRG1, 0xaa0),
  55. INTC_VECT(DMABRG2, 0xac0),
  56. INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
  57. INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
  58. INTC_VECT(SCIF1_ERI, 0xb00), INTC_VECT(SCIF1_RXI, 0xb20),
  59. INTC_VECT(SCIF1_BRI, 0xb40), INTC_VECT(SCIF1_TXI, 0xb60),
  60. INTC_VECT(SCIF2_ERI, 0xb80), INTC_VECT(SCIF2_RXI, 0xba0),
  61. INTC_VECT(SCIF2_BRI, 0xbc0), INTC_VECT(SCIF2_TXI, 0xbe0),
  62. INTC_VECT(SIM_ERI, 0xc00), INTC_VECT(SIM_RXI, 0xc20),
  63. INTC_VECT(SIM_TXI, 0xc40), INTC_VECT(SIM_TEI, 0xc60),
  64. INTC_VECT(HSPI, 0xc80),
  65. INTC_VECT(MMCIF0, 0xd00), INTC_VECT(MMCIF1, 0xd20),
  66. INTC_VECT(MMCIF2, 0xd40), INTC_VECT(MMCIF3, 0xd60),
  67. INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */
  68. INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0),
  69. INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
  70. INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
  71. INTC_VECT(WDT, 0x560),
  72. INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
  73. };
  74. static struct intc_group groups[] __initdata = {
  75. INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2),
  76. INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
  77. INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
  78. INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
  79. INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
  80. INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3),
  81. };
  82. static struct intc_mask_reg mask_registers[] __initdata = {
  83. { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
  84. { IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21,
  85. SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
  86. 0, DMABRG0, DMABRG1, DMABRG2,
  87. SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
  88. SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
  89. SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, } },
  90. { 0xfe080044, 0xfe080064, 32, /* INTMSK04 / INTMSKCLR04 */
  91. { 0, 0, 0, 0, 0, 0, 0, 0,
  92. SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
  93. HSPI, MMCIF0, MMCIF1, MMCIF2,
  94. MMCIF3, 0, 0, 0, 0, 0, 0, 0,
  95. 0, MFI, 0, 0, 0, 0, ADC, CMT, } },
  96. };
  97. static struct intc_prio_reg prio_registers[] __initdata = {
  98. { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
  99. { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
  100. { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } },
  101. { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
  102. { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
  103. { 0xfe080004, 0, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1,
  104. HAC0, HAC1, I2C0, I2C1 } },
  105. { 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,
  106. SCIF1, SCIF2, SIM, HSPI } },
  107. { 0xfe08000c, 0, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0,
  108. MFI, 0, ADC, CMT } },
  109. };
  110. static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups,
  111. mask_registers, prio_registers, NULL);
  112. static struct intc_vect vectors_irq[] __initdata = {
  113. INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
  114. INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
  115. };
  116. static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
  117. mask_registers, prio_registers, NULL);
  118. static struct plat_sci_port scif0_platform_data = {
  119. .mapbase = 0xfe600000,
  120. .flags = UPF_BOOT_AUTOCONF,
  121. .type = PORT_SCIF,
  122. .irqs = { 52, 53, 55, 54 },
  123. };
  124. static struct platform_device scif0_device = {
  125. .name = "sh-sci",
  126. .id = 0,
  127. .dev = {
  128. .platform_data = &scif0_platform_data,
  129. },
  130. };
  131. static struct plat_sci_port scif1_platform_data = {
  132. .mapbase = 0xfe610000,
  133. .flags = UPF_BOOT_AUTOCONF,
  134. .type = PORT_SCIF,
  135. .irqs = { 72, 73, 75, 74 },
  136. };
  137. static struct platform_device scif1_device = {
  138. .name = "sh-sci",
  139. .id = 1,
  140. .dev = {
  141. .platform_data = &scif1_platform_data,
  142. },
  143. };
  144. static struct plat_sci_port scif2_platform_data = {
  145. .mapbase = 0xfe620000,
  146. .flags = UPF_BOOT_AUTOCONF,
  147. .type = PORT_SCIF,
  148. .irqs = { 76, 77, 79, 78 },
  149. };
  150. static struct platform_device scif2_device = {
  151. .name = "sh-sci",
  152. .id = 2,
  153. .dev = {
  154. .platform_data = &scif2_platform_data,
  155. },
  156. };
  157. static struct plat_sci_port scif3_platform_data = {
  158. .mapbase = 0xfe480000,
  159. .flags = UPF_BOOT_AUTOCONF,
  160. .type = PORT_SCI,
  161. .irqs = { 80, 81, 82, 0 },
  162. };
  163. static struct platform_device scif3_device = {
  164. .name = "sh-sci",
  165. .id = 3,
  166. .dev = {
  167. .platform_data = &scif3_platform_data,
  168. },
  169. };
  170. static struct sh_timer_config tmu0_platform_data = {
  171. .name = "TMU0",
  172. .channel_offset = 0x04,
  173. .timer_bit = 0,
  174. .clk = "peripheral_clk",
  175. .clockevent_rating = 200,
  176. };
  177. static struct resource tmu0_resources[] = {
  178. [0] = {
  179. .name = "TMU0",
  180. .start = 0xffd80008,
  181. .end = 0xffd80013,
  182. .flags = IORESOURCE_MEM,
  183. },
  184. [1] = {
  185. .start = 16,
  186. .flags = IORESOURCE_IRQ,
  187. },
  188. };
  189. static struct platform_device tmu0_device = {
  190. .name = "sh_tmu",
  191. .id = 0,
  192. .dev = {
  193. .platform_data = &tmu0_platform_data,
  194. },
  195. .resource = tmu0_resources,
  196. .num_resources = ARRAY_SIZE(tmu0_resources),
  197. };
  198. static struct sh_timer_config tmu1_platform_data = {
  199. .name = "TMU1",
  200. .channel_offset = 0x10,
  201. .timer_bit = 1,
  202. .clk = "peripheral_clk",
  203. .clocksource_rating = 200,
  204. };
  205. static struct resource tmu1_resources[] = {
  206. [0] = {
  207. .name = "TMU1",
  208. .start = 0xffd80014,
  209. .end = 0xffd8001f,
  210. .flags = IORESOURCE_MEM,
  211. },
  212. [1] = {
  213. .start = 17,
  214. .flags = IORESOURCE_IRQ,
  215. },
  216. };
  217. static struct platform_device tmu1_device = {
  218. .name = "sh_tmu",
  219. .id = 1,
  220. .dev = {
  221. .platform_data = &tmu1_platform_data,
  222. },
  223. .resource = tmu1_resources,
  224. .num_resources = ARRAY_SIZE(tmu1_resources),
  225. };
  226. static struct sh_timer_config tmu2_platform_data = {
  227. .name = "TMU2",
  228. .channel_offset = 0x1c,
  229. .timer_bit = 2,
  230. .clk = "peripheral_clk",
  231. };
  232. static struct resource tmu2_resources[] = {
  233. [0] = {
  234. .name = "TMU2",
  235. .start = 0xffd80020,
  236. .end = 0xffd8002f,
  237. .flags = IORESOURCE_MEM,
  238. },
  239. [1] = {
  240. .start = 18,
  241. .flags = IORESOURCE_IRQ,
  242. },
  243. };
  244. static struct platform_device tmu2_device = {
  245. .name = "sh_tmu",
  246. .id = 2,
  247. .dev = {
  248. .platform_data = &tmu2_platform_data,
  249. },
  250. .resource = tmu2_resources,
  251. .num_resources = ARRAY_SIZE(tmu2_resources),
  252. };
  253. static struct platform_device *sh7760_devices[] __initdata = {
  254. &scif0_device,
  255. &scif1_device,
  256. &scif2_device,
  257. &scif3_device,
  258. &tmu0_device,
  259. &tmu1_device,
  260. &tmu2_device,
  261. };
  262. static int __init sh7760_devices_setup(void)
  263. {
  264. return platform_add_devices(sh7760_devices,
  265. ARRAY_SIZE(sh7760_devices));
  266. }
  267. arch_initcall(sh7760_devices_setup);
  268. static struct platform_device *sh7760_early_devices[] __initdata = {
  269. &scif0_device,
  270. &scif1_device,
  271. &scif2_device,
  272. &scif3_device,
  273. &tmu0_device,
  274. &tmu1_device,
  275. &tmu2_device,
  276. };
  277. void __init plat_early_device_setup(void)
  278. {
  279. early_platform_add_devices(sh7760_early_devices,
  280. ARRAY_SIZE(sh7760_early_devices));
  281. }
  282. #define INTC_ICR 0xffd00000UL
  283. #define INTC_ICR_IRLM (1 << 7)
  284. void __init plat_irq_setup_pins(int mode)
  285. {
  286. switch (mode) {
  287. case IRQ_MODE_IRQ:
  288. ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
  289. register_intc_controller(&intc_desc_irq);
  290. break;
  291. default:
  292. BUG();
  293. }
  294. }
  295. void __init plat_irq_setup(void)
  296. {
  297. register_intc_controller(&intc_desc);
  298. }