setup-sh7750.c 11 KB

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  1. /*
  2. * SH7750/SH7751 Setup
  3. *
  4. * Copyright (C) 2006 Paul Mundt
  5. * Copyright (C) 2006 Jamie Lenehan
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file "COPYING" in the main directory of this archive
  9. * for more details.
  10. */
  11. #include <linux/platform_device.h>
  12. #include <linux/init.h>
  13. #include <linux/serial.h>
  14. #include <linux/io.h>
  15. #include <linux/sh_timer.h>
  16. #include <linux/serial_sci.h>
  17. static struct resource rtc_resources[] = {
  18. [0] = {
  19. .start = 0xffc80000,
  20. .end = 0xffc80000 + 0x58 - 1,
  21. .flags = IORESOURCE_IO,
  22. },
  23. [1] = {
  24. /* Shared Period/Carry/Alarm IRQ */
  25. .start = 20,
  26. .flags = IORESOURCE_IRQ,
  27. },
  28. };
  29. static struct platform_device rtc_device = {
  30. .name = "sh-rtc",
  31. .id = -1,
  32. .num_resources = ARRAY_SIZE(rtc_resources),
  33. .resource = rtc_resources,
  34. };
  35. static struct plat_sci_port scif0_platform_data = {
  36. .mapbase = 0xffe00000,
  37. .flags = UPF_BOOT_AUTOCONF,
  38. .type = PORT_SCI,
  39. .irqs = { 23, 23, 23, 0 },
  40. };
  41. static struct platform_device scif0_device = {
  42. .name = "sh-sci",
  43. .id = 0,
  44. .dev = {
  45. .platform_data = &scif0_platform_data,
  46. },
  47. };
  48. static struct plat_sci_port scif1_platform_data = {
  49. .mapbase = 0xffe80000,
  50. .flags = UPF_BOOT_AUTOCONF,
  51. .type = PORT_SCIF,
  52. .irqs = { 40, 40, 40, 40 },
  53. };
  54. static struct platform_device scif1_device = {
  55. .name = "sh-sci",
  56. .id = 1,
  57. .dev = {
  58. .platform_data = &scif1_platform_data,
  59. },
  60. };
  61. static struct sh_timer_config tmu0_platform_data = {
  62. .name = "TMU0",
  63. .channel_offset = 0x04,
  64. .timer_bit = 0,
  65. .clk = "peripheral_clk",
  66. .clockevent_rating = 200,
  67. };
  68. static struct resource tmu0_resources[] = {
  69. [0] = {
  70. .name = "TMU0",
  71. .start = 0xffd80008,
  72. .end = 0xffd80013,
  73. .flags = IORESOURCE_MEM,
  74. },
  75. [1] = {
  76. .start = 16,
  77. .flags = IORESOURCE_IRQ,
  78. },
  79. };
  80. static struct platform_device tmu0_device = {
  81. .name = "sh_tmu",
  82. .id = 0,
  83. .dev = {
  84. .platform_data = &tmu0_platform_data,
  85. },
  86. .resource = tmu0_resources,
  87. .num_resources = ARRAY_SIZE(tmu0_resources),
  88. };
  89. static struct sh_timer_config tmu1_platform_data = {
  90. .name = "TMU1",
  91. .channel_offset = 0x10,
  92. .timer_bit = 1,
  93. .clk = "peripheral_clk",
  94. .clocksource_rating = 200,
  95. };
  96. static struct resource tmu1_resources[] = {
  97. [0] = {
  98. .name = "TMU1",
  99. .start = 0xffd80014,
  100. .end = 0xffd8001f,
  101. .flags = IORESOURCE_MEM,
  102. },
  103. [1] = {
  104. .start = 17,
  105. .flags = IORESOURCE_IRQ,
  106. },
  107. };
  108. static struct platform_device tmu1_device = {
  109. .name = "sh_tmu",
  110. .id = 1,
  111. .dev = {
  112. .platform_data = &tmu1_platform_data,
  113. },
  114. .resource = tmu1_resources,
  115. .num_resources = ARRAY_SIZE(tmu1_resources),
  116. };
  117. static struct sh_timer_config tmu2_platform_data = {
  118. .name = "TMU2",
  119. .channel_offset = 0x1c,
  120. .timer_bit = 2,
  121. .clk = "peripheral_clk",
  122. };
  123. static struct resource tmu2_resources[] = {
  124. [0] = {
  125. .name = "TMU2",
  126. .start = 0xffd80020,
  127. .end = 0xffd8002f,
  128. .flags = IORESOURCE_MEM,
  129. },
  130. [1] = {
  131. .start = 18,
  132. .flags = IORESOURCE_IRQ,
  133. },
  134. };
  135. static struct platform_device tmu2_device = {
  136. .name = "sh_tmu",
  137. .id = 2,
  138. .dev = {
  139. .platform_data = &tmu2_platform_data,
  140. },
  141. .resource = tmu2_resources,
  142. .num_resources = ARRAY_SIZE(tmu2_resources),
  143. };
  144. /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
  145. #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
  146. defined(CONFIG_CPU_SUBTYPE_SH7751) || \
  147. defined(CONFIG_CPU_SUBTYPE_SH7751R)
  148. static struct sh_timer_config tmu3_platform_data = {
  149. .name = "TMU3",
  150. .channel_offset = 0x04,
  151. .timer_bit = 0,
  152. .clk = "peripheral_clk",
  153. };
  154. static struct resource tmu3_resources[] = {
  155. [0] = {
  156. .name = "TMU3",
  157. .start = 0xfe100008,
  158. .end = 0xfe100013,
  159. .flags = IORESOURCE_MEM,
  160. },
  161. [1] = {
  162. .start = 72,
  163. .flags = IORESOURCE_IRQ,
  164. },
  165. };
  166. static struct platform_device tmu3_device = {
  167. .name = "sh_tmu",
  168. .id = 3,
  169. .dev = {
  170. .platform_data = &tmu3_platform_data,
  171. },
  172. .resource = tmu3_resources,
  173. .num_resources = ARRAY_SIZE(tmu3_resources),
  174. };
  175. static struct sh_timer_config tmu4_platform_data = {
  176. .name = "TMU4",
  177. .channel_offset = 0x10,
  178. .timer_bit = 1,
  179. .clk = "peripheral_clk",
  180. };
  181. static struct resource tmu4_resources[] = {
  182. [0] = {
  183. .name = "TMU4",
  184. .start = 0xfe100014,
  185. .end = 0xfe10001f,
  186. .flags = IORESOURCE_MEM,
  187. },
  188. [1] = {
  189. .start = 76,
  190. .flags = IORESOURCE_IRQ,
  191. },
  192. };
  193. static struct platform_device tmu4_device = {
  194. .name = "sh_tmu",
  195. .id = 4,
  196. .dev = {
  197. .platform_data = &tmu4_platform_data,
  198. },
  199. .resource = tmu4_resources,
  200. .num_resources = ARRAY_SIZE(tmu4_resources),
  201. };
  202. #endif
  203. static struct platform_device *sh7750_devices[] __initdata = {
  204. &scif0_device,
  205. &scif1_device,
  206. &rtc_device,
  207. &tmu0_device,
  208. &tmu1_device,
  209. &tmu2_device,
  210. #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
  211. defined(CONFIG_CPU_SUBTYPE_SH7751) || \
  212. defined(CONFIG_CPU_SUBTYPE_SH7751R)
  213. &tmu3_device,
  214. &tmu4_device,
  215. #endif
  216. };
  217. static int __init sh7750_devices_setup(void)
  218. {
  219. return platform_add_devices(sh7750_devices,
  220. ARRAY_SIZE(sh7750_devices));
  221. }
  222. arch_initcall(sh7750_devices_setup);
  223. static struct platform_device *sh7750_early_devices[] __initdata = {
  224. &scif0_device,
  225. &scif1_device,
  226. &tmu0_device,
  227. &tmu1_device,
  228. &tmu2_device,
  229. #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
  230. defined(CONFIG_CPU_SUBTYPE_SH7751) || \
  231. defined(CONFIG_CPU_SUBTYPE_SH7751R)
  232. &tmu3_device,
  233. &tmu4_device,
  234. #endif
  235. };
  236. void __init plat_early_device_setup(void)
  237. {
  238. early_platform_add_devices(sh7750_early_devices,
  239. ARRAY_SIZE(sh7750_early_devices));
  240. }
  241. enum {
  242. UNUSED = 0,
  243. /* interrupt sources */
  244. IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
  245. HUDI, GPIOI, DMAC,
  246. PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
  247. PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
  248. TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
  249. /* interrupt groups */
  250. PCIC1,
  251. };
  252. static struct intc_vect vectors[] __initdata = {
  253. INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
  254. INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
  255. INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
  256. INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
  257. INTC_VECT(RTC, 0x4c0),
  258. INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
  259. INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
  260. INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
  261. INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
  262. INTC_VECT(WDT, 0x560),
  263. INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
  264. };
  265. static struct intc_prio_reg prio_registers[] __initdata = {
  266. { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
  267. { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
  268. { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
  269. { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
  270. { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
  271. TMU4, TMU3,
  272. PCIC1, PCIC0_PCISERR } },
  273. };
  274. static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
  275. NULL, prio_registers, NULL);
  276. /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
  277. #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
  278. defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
  279. defined(CONFIG_CPU_SUBTYPE_SH7751) || \
  280. defined(CONFIG_CPU_SUBTYPE_SH7091)
  281. static struct intc_vect vectors_dma4[] __initdata = {
  282. INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
  283. INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
  284. INTC_VECT(DMAC, 0x6c0),
  285. };
  286. static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
  287. vectors_dma4, NULL,
  288. NULL, prio_registers, NULL);
  289. #endif
  290. /* SH7750R and SH7751R both have 8-channel DMA controllers */
  291. #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
  292. static struct intc_vect vectors_dma8[] __initdata = {
  293. INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
  294. INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
  295. INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
  296. INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
  297. INTC_VECT(DMAC, 0x6c0),
  298. };
  299. static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
  300. vectors_dma8, NULL,
  301. NULL, prio_registers, NULL);
  302. #endif
  303. /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
  304. #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
  305. defined(CONFIG_CPU_SUBTYPE_SH7751) || \
  306. defined(CONFIG_CPU_SUBTYPE_SH7751R)
  307. static struct intc_vect vectors_tmu34[] __initdata = {
  308. INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
  309. };
  310. static struct intc_mask_reg mask_registers[] __initdata = {
  311. { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
  312. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  313. 0, 0, 0, 0, 0, 0, TMU4, TMU3,
  314. PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
  315. PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
  316. PCIC1_PCIDMA3, PCIC0_PCISERR } },
  317. };
  318. static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
  319. vectors_tmu34, NULL,
  320. mask_registers, prio_registers, NULL);
  321. #endif
  322. /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
  323. static struct intc_vect vectors_irlm[] __initdata = {
  324. INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
  325. INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
  326. };
  327. static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
  328. NULL, prio_registers, NULL);
  329. /* SH7751 and SH7751R both have PCI */
  330. #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
  331. static struct intc_vect vectors_pci[] __initdata = {
  332. INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
  333. INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
  334. INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
  335. INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
  336. };
  337. static struct intc_group groups_pci[] __initdata = {
  338. INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
  339. PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
  340. };
  341. static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
  342. mask_registers, prio_registers, NULL);
  343. #endif
  344. #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
  345. defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
  346. defined(CONFIG_CPU_SUBTYPE_SH7091)
  347. void __init plat_irq_setup(void)
  348. {
  349. /*
  350. * same vectors for SH7750, SH7750S and SH7091 except for IRLM,
  351. * see below..
  352. */
  353. register_intc_controller(&intc_desc);
  354. register_intc_controller(&intc_desc_dma4);
  355. }
  356. #endif
  357. #if defined(CONFIG_CPU_SUBTYPE_SH7750R)
  358. void __init plat_irq_setup(void)
  359. {
  360. register_intc_controller(&intc_desc);
  361. register_intc_controller(&intc_desc_dma8);
  362. register_intc_controller(&intc_desc_tmu34);
  363. }
  364. #endif
  365. #if defined(CONFIG_CPU_SUBTYPE_SH7751)
  366. void __init plat_irq_setup(void)
  367. {
  368. register_intc_controller(&intc_desc);
  369. register_intc_controller(&intc_desc_dma4);
  370. register_intc_controller(&intc_desc_tmu34);
  371. register_intc_controller(&intc_desc_pci);
  372. }
  373. #endif
  374. #if defined(CONFIG_CPU_SUBTYPE_SH7751R)
  375. void __init plat_irq_setup(void)
  376. {
  377. register_intc_controller(&intc_desc);
  378. register_intc_controller(&intc_desc_dma8);
  379. register_intc_controller(&intc_desc_tmu34);
  380. register_intc_controller(&intc_desc_pci);
  381. }
  382. #endif
  383. #define INTC_ICR 0xffd00000UL
  384. #define INTC_ICR_IRLM (1<<7)
  385. void __init plat_irq_setup_pins(int mode)
  386. {
  387. #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
  388. BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
  389. return;
  390. #endif
  391. switch (mode) {
  392. case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
  393. ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
  394. register_intc_controller(&intc_desc_irlm);
  395. break;
  396. default:
  397. BUG();
  398. }
  399. }