setup-sh770x.c 7.2 KB

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  1. /*
  2. * SH3 Setup code for SH7706, SH7707, SH7708, SH7709
  3. *
  4. * Copyright (C) 2007 Magnus Damm
  5. * Copyright (C) 2009 Paul Mundt
  6. *
  7. * Based on setup-sh7709.c
  8. *
  9. * Copyright (C) 2006 Paul Mundt
  10. *
  11. * This file is subject to the terms and conditions of the GNU General Public
  12. * License. See the file "COPYING" in the main directory of this archive
  13. * for more details.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/io.h>
  17. #include <linux/irq.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/serial.h>
  20. #include <linux/serial_sci.h>
  21. #include <linux/sh_timer.h>
  22. enum {
  23. UNUSED = 0,
  24. /* interrupt sources */
  25. IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
  26. PINT07, PINT815,
  27. DMAC, SCIF0, SCIF2, SCI, ADC_ADI,
  28. LCDC, PCC0, PCC1,
  29. TMU0, TMU1, TMU2,
  30. RTC, WDT, REF,
  31. };
  32. static struct intc_vect vectors[] __initdata = {
  33. INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
  34. INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
  35. INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
  36. INTC_VECT(RTC, 0x4c0),
  37. INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500),
  38. INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540),
  39. INTC_VECT(WDT, 0x560),
  40. INTC_VECT(REF, 0x580),
  41. INTC_VECT(REF, 0x5a0),
  42. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  43. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  44. defined(CONFIG_CPU_SUBTYPE_SH7709)
  45. /* IRQ0->5 are handled in setup-sh3.c */
  46. INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
  47. INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
  48. INTC_VECT(ADC_ADI, 0x980),
  49. INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
  50. INTC_VECT(SCIF2, 0x940), INTC_VECT(SCIF2, 0x960),
  51. #endif
  52. #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  53. defined(CONFIG_CPU_SUBTYPE_SH7709)
  54. INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
  55. INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
  56. INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
  57. #endif
  58. #if defined(CONFIG_CPU_SUBTYPE_SH7707)
  59. INTC_VECT(LCDC, 0x9a0),
  60. INTC_VECT(PCC0, 0x9c0), INTC_VECT(PCC1, 0x9e0),
  61. #endif
  62. };
  63. static struct intc_prio_reg prio_registers[] __initdata = {
  64. { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
  65. { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
  66. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  67. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  68. defined(CONFIG_CPU_SUBTYPE_SH7709)
  69. { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
  70. { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
  71. { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
  72. #endif
  73. #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  74. defined(CONFIG_CPU_SUBTYPE_SH7709)
  75. { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } },
  76. { 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } },
  77. #endif
  78. #if defined(CONFIG_CPU_SUBTYPE_SH7707)
  79. { 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
  80. #endif
  81. };
  82. static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, NULL,
  83. NULL, prio_registers, NULL);
  84. static struct resource rtc_resources[] = {
  85. [0] = {
  86. .start = 0xfffffec0,
  87. .end = 0xfffffec0 + 0x1e,
  88. .flags = IORESOURCE_IO,
  89. },
  90. [1] = {
  91. .start = 20,
  92. .flags = IORESOURCE_IRQ,
  93. },
  94. };
  95. static struct platform_device rtc_device = {
  96. .name = "sh-rtc",
  97. .id = -1,
  98. .num_resources = ARRAY_SIZE(rtc_resources),
  99. .resource = rtc_resources,
  100. };
  101. static struct plat_sci_port scif0_platform_data = {
  102. .mapbase = 0xfffffe80,
  103. .flags = UPF_BOOT_AUTOCONF,
  104. .type = PORT_SCI,
  105. .irqs = { 23, 23, 23, 0 },
  106. };
  107. static struct platform_device scif0_device = {
  108. .name = "sh-sci",
  109. .id = 0,
  110. .dev = {
  111. .platform_data = &scif0_platform_data,
  112. },
  113. };
  114. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  115. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  116. defined(CONFIG_CPU_SUBTYPE_SH7709)
  117. static struct plat_sci_port scif1_platform_data = {
  118. .mapbase = 0xa4000150,
  119. .flags = UPF_BOOT_AUTOCONF,
  120. .type = PORT_SCIF,
  121. .irqs = { 56, 56, 56, 56 },
  122. };
  123. static struct platform_device scif1_device = {
  124. .name = "sh-sci",
  125. .id = 1,
  126. .dev = {
  127. .platform_data = &scif1_platform_data,
  128. },
  129. };
  130. #endif
  131. #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  132. defined(CONFIG_CPU_SUBTYPE_SH7709)
  133. static struct plat_sci_port scif2_platform_data = {
  134. .mapbase = 0xa4000140,
  135. .flags = UPF_BOOT_AUTOCONF,
  136. .type = PORT_IRDA,
  137. .irqs = { 52, 52, 52, 52 },
  138. };
  139. static struct platform_device scif2_device = {
  140. .name = "sh-sci",
  141. .id = 2,
  142. .dev = {
  143. .platform_data = &scif2_platform_data,
  144. },
  145. };
  146. #endif
  147. static struct sh_timer_config tmu0_platform_data = {
  148. .name = "TMU0",
  149. .channel_offset = 0x02,
  150. .timer_bit = 0,
  151. .clk = "peripheral_clk",
  152. .clockevent_rating = 200,
  153. };
  154. static struct resource tmu0_resources[] = {
  155. [0] = {
  156. .name = "TMU0",
  157. .start = 0xfffffe94,
  158. .end = 0xfffffe9f,
  159. .flags = IORESOURCE_MEM,
  160. },
  161. [1] = {
  162. .start = 16,
  163. .flags = IORESOURCE_IRQ,
  164. },
  165. };
  166. static struct platform_device tmu0_device = {
  167. .name = "sh_tmu",
  168. .id = 0,
  169. .dev = {
  170. .platform_data = &tmu0_platform_data,
  171. },
  172. .resource = tmu0_resources,
  173. .num_resources = ARRAY_SIZE(tmu0_resources),
  174. };
  175. static struct sh_timer_config tmu1_platform_data = {
  176. .name = "TMU1",
  177. .channel_offset = 0xe,
  178. .timer_bit = 1,
  179. .clk = "peripheral_clk",
  180. .clocksource_rating = 200,
  181. };
  182. static struct resource tmu1_resources[] = {
  183. [0] = {
  184. .name = "TMU1",
  185. .start = 0xfffffea0,
  186. .end = 0xfffffeab,
  187. .flags = IORESOURCE_MEM,
  188. },
  189. [1] = {
  190. .start = 17,
  191. .flags = IORESOURCE_IRQ,
  192. },
  193. };
  194. static struct platform_device tmu1_device = {
  195. .name = "sh_tmu",
  196. .id = 1,
  197. .dev = {
  198. .platform_data = &tmu1_platform_data,
  199. },
  200. .resource = tmu1_resources,
  201. .num_resources = ARRAY_SIZE(tmu1_resources),
  202. };
  203. static struct sh_timer_config tmu2_platform_data = {
  204. .name = "TMU2",
  205. .channel_offset = 0x1a,
  206. .timer_bit = 2,
  207. .clk = "peripheral_clk",
  208. };
  209. static struct resource tmu2_resources[] = {
  210. [0] = {
  211. .name = "TMU2",
  212. .start = 0xfffffeac,
  213. .end = 0xfffffebb,
  214. .flags = IORESOURCE_MEM,
  215. },
  216. [1] = {
  217. .start = 18,
  218. .flags = IORESOURCE_IRQ,
  219. },
  220. };
  221. static struct platform_device tmu2_device = {
  222. .name = "sh_tmu",
  223. .id = 2,
  224. .dev = {
  225. .platform_data = &tmu2_platform_data,
  226. },
  227. .resource = tmu2_resources,
  228. .num_resources = ARRAY_SIZE(tmu2_resources),
  229. };
  230. static struct platform_device *sh770x_devices[] __initdata = {
  231. &scif0_device,
  232. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  233. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  234. defined(CONFIG_CPU_SUBTYPE_SH7709)
  235. &scif1_device,
  236. #endif
  237. #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  238. defined(CONFIG_CPU_SUBTYPE_SH7709)
  239. &scif2_device,
  240. #endif
  241. &tmu0_device,
  242. &tmu1_device,
  243. &tmu2_device,
  244. &rtc_device,
  245. };
  246. static int __init sh770x_devices_setup(void)
  247. {
  248. return platform_add_devices(sh770x_devices,
  249. ARRAY_SIZE(sh770x_devices));
  250. }
  251. arch_initcall(sh770x_devices_setup);
  252. static struct platform_device *sh770x_early_devices[] __initdata = {
  253. &scif0_device,
  254. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  255. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  256. defined(CONFIG_CPU_SUBTYPE_SH7709)
  257. &scif1_device,
  258. #endif
  259. #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  260. defined(CONFIG_CPU_SUBTYPE_SH7709)
  261. &scif2_device,
  262. #endif
  263. &tmu0_device,
  264. &tmu1_device,
  265. &tmu2_device,
  266. };
  267. void __init plat_early_device_setup(void)
  268. {
  269. early_platform_add_devices(sh770x_early_devices,
  270. ARRAY_SIZE(sh770x_early_devices));
  271. }
  272. void __init plat_irq_setup(void)
  273. {
  274. register_intc_controller(&intc_desc);
  275. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  276. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  277. defined(CONFIG_CPU_SUBTYPE_SH7709)
  278. plat_irq_setup_sh3();
  279. #endif
  280. }