setup.c 27 KB

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  1. /*
  2. * Copyright (C) 2009 Renesas Solutions Corp.
  3. *
  4. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/init.h>
  11. #include <linux/device.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/mtd/physmap.h>
  14. #include <linux/gpio.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/io.h>
  17. #include <linux/delay.h>
  18. #include <linux/usb/r8a66597.h>
  19. #include <linux/i2c.h>
  20. #include <linux/i2c/tsc2007.h>
  21. #include <linux/spi/spi.h>
  22. #include <linux/spi/sh_msiof.h>
  23. #include <linux/spi/mmc_spi.h>
  24. #include <linux/mmc/host.h>
  25. #include <linux/input.h>
  26. #include <linux/input/sh_keysc.h>
  27. #include <linux/mfd/sh_mobile_sdhi.h>
  28. #include <video/sh_mobile_lcdc.h>
  29. #include <sound/sh_fsi.h>
  30. #include <media/sh_mobile_ceu.h>
  31. #include <media/tw9910.h>
  32. #include <media/mt9t112.h>
  33. #include <asm/heartbeat.h>
  34. #include <asm/sh_eth.h>
  35. #include <asm/clock.h>
  36. #include <asm/suspend.h>
  37. #include <cpu/sh7724.h>
  38. /*
  39. * Address Interface BusWidth
  40. *-----------------------------------------
  41. * 0x0000_0000 uboot 16bit
  42. * 0x0004_0000 Linux romImage 16bit
  43. * 0x0014_0000 MTD for Linux 16bit
  44. * 0x0400_0000 Internal I/O 16/32bit
  45. * 0x0800_0000 DRAM 32bit
  46. * 0x1800_0000 MFI 16bit
  47. */
  48. /* SWITCH
  49. *------------------------------
  50. * DS2[1] = FlashROM write protect ON : write protect
  51. * OFF : No write protect
  52. * DS2[2] = RMII / TS, SCIF ON : RMII
  53. * OFF : TS, SCIF3
  54. * DS2[3] = Camera / Video ON : Camera
  55. * OFF : NTSC/PAL (IN)
  56. * DS2[5] = NTSC_OUT Clock ON : On board OSC
  57. * OFF : SH7724 DV_CLK
  58. * DS2[6-7] = MMC / SD ON-OFF : SD
  59. * OFF-ON : MMC
  60. */
  61. /* Heartbeat */
  62. static unsigned char led_pos[] = { 0, 1, 2, 3 };
  63. static struct heartbeat_data heartbeat_data = {
  64. .regsize = 8,
  65. .nr_bits = 4,
  66. .bit_pos = led_pos,
  67. };
  68. static struct resource heartbeat_resources[] = {
  69. [0] = {
  70. .start = 0xA405012C, /* PTG */
  71. .end = 0xA405012E - 1,
  72. .flags = IORESOURCE_MEM,
  73. },
  74. };
  75. static struct platform_device heartbeat_device = {
  76. .name = "heartbeat",
  77. .id = -1,
  78. .dev = {
  79. .platform_data = &heartbeat_data,
  80. },
  81. .num_resources = ARRAY_SIZE(heartbeat_resources),
  82. .resource = heartbeat_resources,
  83. };
  84. /* MTD */
  85. static struct mtd_partition nor_flash_partitions[] = {
  86. {
  87. .name = "boot loader",
  88. .offset = 0,
  89. .size = (5 * 1024 * 1024),
  90. .mask_flags = MTD_WRITEABLE, /* force read-only */
  91. }, {
  92. .name = "free-area",
  93. .offset = MTDPART_OFS_APPEND,
  94. .size = MTDPART_SIZ_FULL,
  95. },
  96. };
  97. static struct physmap_flash_data nor_flash_data = {
  98. .width = 2,
  99. .parts = nor_flash_partitions,
  100. .nr_parts = ARRAY_SIZE(nor_flash_partitions),
  101. };
  102. static struct resource nor_flash_resources[] = {
  103. [0] = {
  104. .name = "NOR Flash",
  105. .start = 0x00000000,
  106. .end = 0x03ffffff,
  107. .flags = IORESOURCE_MEM,
  108. }
  109. };
  110. static struct platform_device nor_flash_device = {
  111. .name = "physmap-flash",
  112. .resource = nor_flash_resources,
  113. .num_resources = ARRAY_SIZE(nor_flash_resources),
  114. .dev = {
  115. .platform_data = &nor_flash_data,
  116. },
  117. };
  118. /* SH Eth */
  119. #define SH_ETH_ADDR (0xA4600000)
  120. static struct resource sh_eth_resources[] = {
  121. [0] = {
  122. .start = SH_ETH_ADDR,
  123. .end = SH_ETH_ADDR + 0x1FC,
  124. .flags = IORESOURCE_MEM,
  125. },
  126. [1] = {
  127. .start = 91,
  128. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  129. },
  130. };
  131. struct sh_eth_plat_data sh_eth_plat = {
  132. .phy = 0x1f, /* SMSC LAN8700 */
  133. .edmac_endian = EDMAC_LITTLE_ENDIAN,
  134. .ether_link_active_low = 1
  135. };
  136. static struct platform_device sh_eth_device = {
  137. .name = "sh-eth",
  138. .id = 0,
  139. .dev = {
  140. .platform_data = &sh_eth_plat,
  141. },
  142. .num_resources = ARRAY_SIZE(sh_eth_resources),
  143. .resource = sh_eth_resources,
  144. .archdata = {
  145. .hwblk_id = HWBLK_ETHER,
  146. },
  147. };
  148. /* USB0 host */
  149. void usb0_port_power(int port, int power)
  150. {
  151. gpio_set_value(GPIO_PTB4, power);
  152. }
  153. static struct r8a66597_platdata usb0_host_data = {
  154. .on_chip = 1,
  155. .port_power = usb0_port_power,
  156. };
  157. static struct resource usb0_host_resources[] = {
  158. [0] = {
  159. .start = 0xa4d80000,
  160. .end = 0xa4d80124 - 1,
  161. .flags = IORESOURCE_MEM,
  162. },
  163. [1] = {
  164. .start = 65,
  165. .end = 65,
  166. .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
  167. },
  168. };
  169. static struct platform_device usb0_host_device = {
  170. .name = "r8a66597_hcd",
  171. .id = 0,
  172. .dev = {
  173. .dma_mask = NULL, /* not use dma */
  174. .coherent_dma_mask = 0xffffffff,
  175. .platform_data = &usb0_host_data,
  176. },
  177. .num_resources = ARRAY_SIZE(usb0_host_resources),
  178. .resource = usb0_host_resources,
  179. };
  180. /* USB1 host/function */
  181. void usb1_port_power(int port, int power)
  182. {
  183. gpio_set_value(GPIO_PTB5, power);
  184. }
  185. static struct r8a66597_platdata usb1_common_data = {
  186. .on_chip = 1,
  187. .port_power = usb1_port_power,
  188. };
  189. static struct resource usb1_common_resources[] = {
  190. [0] = {
  191. .start = 0xa4d90000,
  192. .end = 0xa4d90124 - 1,
  193. .flags = IORESOURCE_MEM,
  194. },
  195. [1] = {
  196. .start = 66,
  197. .end = 66,
  198. .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
  199. },
  200. };
  201. static struct platform_device usb1_common_device = {
  202. /* .name will be added in arch_setup */
  203. .id = 1,
  204. .dev = {
  205. .dma_mask = NULL, /* not use dma */
  206. .coherent_dma_mask = 0xffffffff,
  207. .platform_data = &usb1_common_data,
  208. },
  209. .num_resources = ARRAY_SIZE(usb1_common_resources),
  210. .resource = usb1_common_resources,
  211. };
  212. /* LCDC */
  213. static struct sh_mobile_lcdc_info lcdc_info = {
  214. .ch[0] = {
  215. .interface_type = RGB18,
  216. .chan = LCDC_CHAN_MAINLCD,
  217. .bpp = 16,
  218. .lcd_cfg = {
  219. .sync = 0, /* hsync and vsync are active low */
  220. },
  221. .lcd_size_cfg = { /* 7.0 inch */
  222. .width = 152,
  223. .height = 91,
  224. },
  225. .board_cfg = {
  226. },
  227. }
  228. };
  229. static struct resource lcdc_resources[] = {
  230. [0] = {
  231. .name = "LCDC",
  232. .start = 0xfe940000,
  233. .end = 0xfe942fff,
  234. .flags = IORESOURCE_MEM,
  235. },
  236. [1] = {
  237. .start = 106,
  238. .flags = IORESOURCE_IRQ,
  239. },
  240. };
  241. static struct platform_device lcdc_device = {
  242. .name = "sh_mobile_lcdc_fb",
  243. .num_resources = ARRAY_SIZE(lcdc_resources),
  244. .resource = lcdc_resources,
  245. .dev = {
  246. .platform_data = &lcdc_info,
  247. },
  248. .archdata = {
  249. .hwblk_id = HWBLK_LCDC,
  250. },
  251. };
  252. /* CEU0 */
  253. static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
  254. .flags = SH_CEU_FLAG_USE_8BIT_BUS,
  255. };
  256. static struct resource ceu0_resources[] = {
  257. [0] = {
  258. .name = "CEU0",
  259. .start = 0xfe910000,
  260. .end = 0xfe91009f,
  261. .flags = IORESOURCE_MEM,
  262. },
  263. [1] = {
  264. .start = 52,
  265. .flags = IORESOURCE_IRQ,
  266. },
  267. [2] = {
  268. /* place holder for contiguous memory */
  269. },
  270. };
  271. static struct platform_device ceu0_device = {
  272. .name = "sh_mobile_ceu",
  273. .id = 0, /* "ceu0" clock */
  274. .num_resources = ARRAY_SIZE(ceu0_resources),
  275. .resource = ceu0_resources,
  276. .dev = {
  277. .platform_data = &sh_mobile_ceu0_info,
  278. },
  279. .archdata = {
  280. .hwblk_id = HWBLK_CEU0,
  281. },
  282. };
  283. /* CEU1 */
  284. static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
  285. .flags = SH_CEU_FLAG_USE_8BIT_BUS,
  286. };
  287. static struct resource ceu1_resources[] = {
  288. [0] = {
  289. .name = "CEU1",
  290. .start = 0xfe914000,
  291. .end = 0xfe91409f,
  292. .flags = IORESOURCE_MEM,
  293. },
  294. [1] = {
  295. .start = 63,
  296. .flags = IORESOURCE_IRQ,
  297. },
  298. [2] = {
  299. /* place holder for contiguous memory */
  300. },
  301. };
  302. static struct platform_device ceu1_device = {
  303. .name = "sh_mobile_ceu",
  304. .id = 1, /* "ceu1" clock */
  305. .num_resources = ARRAY_SIZE(ceu1_resources),
  306. .resource = ceu1_resources,
  307. .dev = {
  308. .platform_data = &sh_mobile_ceu1_info,
  309. },
  310. .archdata = {
  311. .hwblk_id = HWBLK_CEU1,
  312. },
  313. };
  314. /* I2C device */
  315. static struct i2c_board_info i2c0_devices[] = {
  316. {
  317. I2C_BOARD_INFO("da7210", 0x1a),
  318. },
  319. };
  320. static struct i2c_board_info i2c1_devices[] = {
  321. {
  322. I2C_BOARD_INFO("r2025sd", 0x32),
  323. },
  324. };
  325. /* KEYSC */
  326. static struct sh_keysc_info keysc_info = {
  327. .mode = SH_KEYSC_MODE_1,
  328. .scan_timing = 3,
  329. .delay = 50,
  330. .kycr2_delay = 100,
  331. .keycodes = { KEY_1, 0, 0, 0, 0,
  332. KEY_2, 0, 0, 0, 0,
  333. KEY_3, 0, 0, 0, 0,
  334. KEY_4, 0, 0, 0, 0,
  335. KEY_5, 0, 0, 0, 0,
  336. KEY_6, 0, 0, 0, 0, },
  337. };
  338. static struct resource keysc_resources[] = {
  339. [0] = {
  340. .name = "KEYSC",
  341. .start = 0x044b0000,
  342. .end = 0x044b000f,
  343. .flags = IORESOURCE_MEM,
  344. },
  345. [1] = {
  346. .start = 79,
  347. .flags = IORESOURCE_IRQ,
  348. },
  349. };
  350. static struct platform_device keysc_device = {
  351. .name = "sh_keysc",
  352. .id = 0, /* keysc0 clock */
  353. .num_resources = ARRAY_SIZE(keysc_resources),
  354. .resource = keysc_resources,
  355. .dev = {
  356. .platform_data = &keysc_info,
  357. },
  358. .archdata = {
  359. .hwblk_id = HWBLK_KEYSC,
  360. },
  361. };
  362. /* TouchScreen */
  363. #define IRQ0 32
  364. static int ts_get_pendown_state(void)
  365. {
  366. int val = 0;
  367. gpio_free(GPIO_FN_INTC_IRQ0);
  368. gpio_request(GPIO_PTZ0, NULL);
  369. gpio_direction_input(GPIO_PTZ0);
  370. val = gpio_get_value(GPIO_PTZ0);
  371. gpio_free(GPIO_PTZ0);
  372. gpio_request(GPIO_FN_INTC_IRQ0, NULL);
  373. return val ? 0 : 1;
  374. }
  375. static int ts_init(void)
  376. {
  377. gpio_request(GPIO_FN_INTC_IRQ0, NULL);
  378. return 0;
  379. }
  380. struct tsc2007_platform_data tsc2007_info = {
  381. .model = 2007,
  382. .x_plate_ohms = 180,
  383. .get_pendown_state = ts_get_pendown_state,
  384. .init_platform_hw = ts_init,
  385. };
  386. static struct i2c_board_info ts_i2c_clients = {
  387. I2C_BOARD_INFO("tsc2007", 0x48),
  388. .type = "tsc2007",
  389. .platform_data = &tsc2007_info,
  390. .irq = IRQ0,
  391. };
  392. #ifdef CONFIG_MFD_SH_MOBILE_SDHI
  393. /* SHDI0 */
  394. static void sdhi0_set_pwr(struct platform_device *pdev, int state)
  395. {
  396. gpio_set_value(GPIO_PTB6, state);
  397. }
  398. static struct sh_mobile_sdhi_info sdhi0_info = {
  399. .set_pwr = sdhi0_set_pwr,
  400. };
  401. static struct resource sdhi0_resources[] = {
  402. [0] = {
  403. .name = "SDHI0",
  404. .start = 0x04ce0000,
  405. .end = 0x04ce01ff,
  406. .flags = IORESOURCE_MEM,
  407. },
  408. [1] = {
  409. .start = 101,
  410. .flags = IORESOURCE_IRQ,
  411. },
  412. };
  413. static struct platform_device sdhi0_device = {
  414. .name = "sh_mobile_sdhi",
  415. .num_resources = ARRAY_SIZE(sdhi0_resources),
  416. .resource = sdhi0_resources,
  417. .id = 0,
  418. .dev = {
  419. .platform_data = &sdhi0_info,
  420. },
  421. .archdata = {
  422. .hwblk_id = HWBLK_SDHI0,
  423. },
  424. };
  425. /* SHDI1 */
  426. static void sdhi1_set_pwr(struct platform_device *pdev, int state)
  427. {
  428. gpio_set_value(GPIO_PTB7, state);
  429. }
  430. static struct sh_mobile_sdhi_info sdhi1_info = {
  431. .set_pwr = sdhi1_set_pwr,
  432. };
  433. static struct resource sdhi1_resources[] = {
  434. [0] = {
  435. .name = "SDHI1",
  436. .start = 0x04cf0000,
  437. .end = 0x04cf01ff,
  438. .flags = IORESOURCE_MEM,
  439. },
  440. [1] = {
  441. .start = 24,
  442. .flags = IORESOURCE_IRQ,
  443. },
  444. };
  445. static struct platform_device sdhi1_device = {
  446. .name = "sh_mobile_sdhi",
  447. .num_resources = ARRAY_SIZE(sdhi1_resources),
  448. .resource = sdhi1_resources,
  449. .id = 1,
  450. .dev = {
  451. .platform_data = &sdhi1_info,
  452. },
  453. .archdata = {
  454. .hwblk_id = HWBLK_SDHI1,
  455. },
  456. };
  457. #else
  458. /* MMC SPI */
  459. static int mmc_spi_get_ro(struct device *dev)
  460. {
  461. return gpio_get_value(GPIO_PTY6);
  462. }
  463. static int mmc_spi_get_cd(struct device *dev)
  464. {
  465. return !gpio_get_value(GPIO_PTY7);
  466. }
  467. static void mmc_spi_setpower(struct device *dev, unsigned int maskval)
  468. {
  469. gpio_set_value(GPIO_PTB6, maskval ? 1 : 0);
  470. }
  471. static struct mmc_spi_platform_data mmc_spi_info = {
  472. .get_ro = mmc_spi_get_ro,
  473. .get_cd = mmc_spi_get_cd,
  474. .caps = MMC_CAP_NEEDS_POLL,
  475. .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3.3V only */
  476. .setpower = mmc_spi_setpower,
  477. };
  478. static struct spi_board_info spi_bus[] = {
  479. {
  480. .modalias = "mmc_spi",
  481. .platform_data = &mmc_spi_info,
  482. .max_speed_hz = 5000000,
  483. .mode = SPI_MODE_0,
  484. .controller_data = (void *) GPIO_PTM4,
  485. },
  486. };
  487. /* MSIOF0 */
  488. static struct sh_msiof_spi_info msiof0_data = {
  489. .num_chipselect = 1,
  490. };
  491. static struct resource msiof0_resources[] = {
  492. [0] = {
  493. .name = "MSIOF0",
  494. .start = 0xa4c40000,
  495. .end = 0xa4c40063,
  496. .flags = IORESOURCE_MEM,
  497. },
  498. [1] = {
  499. .start = 84,
  500. .flags = IORESOURCE_IRQ,
  501. },
  502. };
  503. static struct platform_device msiof0_device = {
  504. .name = "spi_sh_msiof",
  505. .id = 0, /* MSIOF0 */
  506. .dev = {
  507. .platform_data = &msiof0_data,
  508. },
  509. .num_resources = ARRAY_SIZE(msiof0_resources),
  510. .resource = msiof0_resources,
  511. .archdata = {
  512. .hwblk_id = HWBLK_MSIOF0,
  513. },
  514. };
  515. #endif
  516. /* I2C Video/Camera */
  517. static struct i2c_board_info i2c_camera[] = {
  518. {
  519. I2C_BOARD_INFO("tw9910", 0x45),
  520. },
  521. {
  522. /* 1st camera */
  523. I2C_BOARD_INFO("mt9t112", 0x3c),
  524. },
  525. {
  526. /* 2nd camera */
  527. I2C_BOARD_INFO("mt9t112", 0x3c),
  528. },
  529. };
  530. /* tw9910 */
  531. static int tw9910_power(struct device *dev, int mode)
  532. {
  533. int val = mode ? 0 : 1;
  534. gpio_set_value(GPIO_PTU2, val);
  535. if (mode)
  536. mdelay(100);
  537. return 0;
  538. }
  539. static struct tw9910_video_info tw9910_info = {
  540. .buswidth = SOCAM_DATAWIDTH_8,
  541. .mpout = TW9910_MPO_FIELD,
  542. };
  543. static struct soc_camera_link tw9910_link = {
  544. .i2c_adapter_id = 0,
  545. .bus_id = 1,
  546. .power = tw9910_power,
  547. .board_info = &i2c_camera[0],
  548. .module_name = "tw9910",
  549. .priv = &tw9910_info,
  550. };
  551. /* mt9t112 */
  552. static int mt9t112_power1(struct device *dev, int mode)
  553. {
  554. gpio_set_value(GPIO_PTA3, mode);
  555. if (mode)
  556. mdelay(100);
  557. return 0;
  558. }
  559. static struct mt9t112_camera_info mt9t112_info1 = {
  560. .flags = MT9T112_FLAG_PCLK_RISING_EDGE | MT9T112_FLAG_DATAWIDTH_8,
  561. .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
  562. };
  563. static struct soc_camera_link mt9t112_link1 = {
  564. .i2c_adapter_id = 0,
  565. .power = mt9t112_power1,
  566. .bus_id = 0,
  567. .board_info = &i2c_camera[1],
  568. .module_name = "mt9t112",
  569. .priv = &mt9t112_info1,
  570. };
  571. static int mt9t112_power2(struct device *dev, int mode)
  572. {
  573. gpio_set_value(GPIO_PTA4, mode);
  574. if (mode)
  575. mdelay(100);
  576. return 0;
  577. }
  578. static struct mt9t112_camera_info mt9t112_info2 = {
  579. .flags = MT9T112_FLAG_PCLK_RISING_EDGE | MT9T112_FLAG_DATAWIDTH_8,
  580. .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
  581. };
  582. static struct soc_camera_link mt9t112_link2 = {
  583. .i2c_adapter_id = 1,
  584. .power = mt9t112_power2,
  585. .bus_id = 1,
  586. .board_info = &i2c_camera[2],
  587. .module_name = "mt9t112",
  588. .priv = &mt9t112_info2,
  589. };
  590. static struct platform_device camera_devices[] = {
  591. {
  592. .name = "soc-camera-pdrv",
  593. .id = 0,
  594. .dev = {
  595. .platform_data = &tw9910_link,
  596. },
  597. },
  598. {
  599. .name = "soc-camera-pdrv",
  600. .id = 1,
  601. .dev = {
  602. .platform_data = &mt9t112_link1,
  603. },
  604. },
  605. {
  606. .name = "soc-camera-pdrv",
  607. .id = 2,
  608. .dev = {
  609. .platform_data = &mt9t112_link2,
  610. },
  611. },
  612. };
  613. /* FSI */
  614. /*
  615. * FSI-B use external clock which came from da7210.
  616. * So, we should change parent of fsi
  617. */
  618. #define FCLKBCR 0xa415000c
  619. static void fsimck_init(struct clk *clk)
  620. {
  621. u32 status = ctrl_inl(clk->enable_reg);
  622. /* use external clock */
  623. status &= ~0x000000ff;
  624. status |= 0x00000080;
  625. ctrl_outl(status, clk->enable_reg);
  626. }
  627. static struct clk_ops fsimck_clk_ops = {
  628. .init = fsimck_init,
  629. };
  630. static struct clk fsimckb_clk = {
  631. .name = "fsimckb_clk",
  632. .id = -1,
  633. .ops = &fsimck_clk_ops,
  634. .enable_reg = (void __iomem *)FCLKBCR,
  635. .rate = 0, /* unknown */
  636. };
  637. struct sh_fsi_platform_info fsi_info = {
  638. .portb_flags = SH_FSI_BRS_INV |
  639. SH_FSI_OUT_SLAVE_MODE |
  640. SH_FSI_IN_SLAVE_MODE |
  641. SH_FSI_OFMT(I2S) |
  642. SH_FSI_IFMT(I2S),
  643. };
  644. static struct resource fsi_resources[] = {
  645. [0] = {
  646. .name = "FSI",
  647. .start = 0xFE3C0000,
  648. .end = 0xFE3C021d,
  649. .flags = IORESOURCE_MEM,
  650. },
  651. [1] = {
  652. .start = 108,
  653. .flags = IORESOURCE_IRQ,
  654. },
  655. };
  656. static struct platform_device fsi_device = {
  657. .name = "sh_fsi",
  658. .id = 0,
  659. .num_resources = ARRAY_SIZE(fsi_resources),
  660. .resource = fsi_resources,
  661. .dev = {
  662. .platform_data = &fsi_info,
  663. },
  664. .archdata = {
  665. .hwblk_id = HWBLK_SPU, /* FSI needs SPU hwblk */
  666. },
  667. };
  668. static struct platform_device *ecovec_devices[] __initdata = {
  669. &heartbeat_device,
  670. &nor_flash_device,
  671. &sh_eth_device,
  672. &usb0_host_device,
  673. &usb1_common_device,
  674. &lcdc_device,
  675. &ceu0_device,
  676. &ceu1_device,
  677. &keysc_device,
  678. #ifdef CONFIG_MFD_SH_MOBILE_SDHI
  679. &sdhi0_device,
  680. &sdhi1_device,
  681. #else
  682. &msiof0_device,
  683. #endif
  684. &camera_devices[0],
  685. &camera_devices[1],
  686. &camera_devices[2],
  687. &fsi_device,
  688. };
  689. #define EEPROM_ADDR 0x50
  690. static u8 mac_read(struct i2c_adapter *a, u8 command)
  691. {
  692. struct i2c_msg msg[2];
  693. u8 buf;
  694. int ret;
  695. msg[0].addr = EEPROM_ADDR;
  696. msg[0].flags = 0;
  697. msg[0].len = 1;
  698. msg[0].buf = &command;
  699. msg[1].addr = EEPROM_ADDR;
  700. msg[1].flags = I2C_M_RD;
  701. msg[1].len = 1;
  702. msg[1].buf = &buf;
  703. ret = i2c_transfer(a, msg, 2);
  704. if (ret < 0) {
  705. printk(KERN_ERR "error %d\n", ret);
  706. buf = 0xff;
  707. }
  708. return buf;
  709. }
  710. static void __init sh_eth_init(struct sh_eth_plat_data *pd)
  711. {
  712. struct i2c_adapter *a = i2c_get_adapter(1);
  713. int i;
  714. if (!a) {
  715. pr_err("can not get I2C 1\n");
  716. return;
  717. }
  718. /* read MAC address frome EEPROM */
  719. for (i = 0; i < sizeof(pd->mac_addr); i++) {
  720. pd->mac_addr[i] = mac_read(a, 0x10 + i);
  721. msleep(10);
  722. }
  723. }
  724. #define PORT_HIZA 0xA4050158
  725. #define IODRIVEA 0xA405018A
  726. extern char ecovec24_sdram_enter_start;
  727. extern char ecovec24_sdram_enter_end;
  728. extern char ecovec24_sdram_leave_start;
  729. extern char ecovec24_sdram_leave_end;
  730. static int __init arch_setup(void)
  731. {
  732. struct clk *clk;
  733. /* register board specific self-refresh code */
  734. sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
  735. &ecovec24_sdram_enter_start,
  736. &ecovec24_sdram_enter_end,
  737. &ecovec24_sdram_leave_start,
  738. &ecovec24_sdram_leave_end);
  739. /* enable STATUS0, STATUS2 and PDSTATUS */
  740. gpio_request(GPIO_FN_STATUS0, NULL);
  741. gpio_request(GPIO_FN_STATUS2, NULL);
  742. gpio_request(GPIO_FN_PDSTATUS, NULL);
  743. /* enable SCIFA0 */
  744. gpio_request(GPIO_FN_SCIF0_TXD, NULL);
  745. gpio_request(GPIO_FN_SCIF0_RXD, NULL);
  746. /* enable debug LED */
  747. gpio_request(GPIO_PTG0, NULL);
  748. gpio_request(GPIO_PTG1, NULL);
  749. gpio_request(GPIO_PTG2, NULL);
  750. gpio_request(GPIO_PTG3, NULL);
  751. gpio_direction_output(GPIO_PTG0, 0);
  752. gpio_direction_output(GPIO_PTG1, 0);
  753. gpio_direction_output(GPIO_PTG2, 0);
  754. gpio_direction_output(GPIO_PTG3, 0);
  755. ctrl_outw((ctrl_inw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA);
  756. /* enable SH-Eth */
  757. gpio_request(GPIO_PTA1, NULL);
  758. gpio_direction_output(GPIO_PTA1, 1);
  759. mdelay(20);
  760. gpio_request(GPIO_FN_RMII_RXD0, NULL);
  761. gpio_request(GPIO_FN_RMII_RXD1, NULL);
  762. gpio_request(GPIO_FN_RMII_TXD0, NULL);
  763. gpio_request(GPIO_FN_RMII_TXD1, NULL);
  764. gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
  765. gpio_request(GPIO_FN_RMII_TX_EN, NULL);
  766. gpio_request(GPIO_FN_RMII_RX_ER, NULL);
  767. gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
  768. gpio_request(GPIO_FN_MDIO, NULL);
  769. gpio_request(GPIO_FN_MDC, NULL);
  770. gpio_request(GPIO_FN_LNKSTA, NULL);
  771. /* enable USB */
  772. ctrl_outw(0x0000, 0xA4D80000);
  773. ctrl_outw(0x0000, 0xA4D90000);
  774. gpio_request(GPIO_PTB3, NULL);
  775. gpio_request(GPIO_PTB4, NULL);
  776. gpio_request(GPIO_PTB5, NULL);
  777. gpio_direction_input(GPIO_PTB3);
  778. gpio_direction_output(GPIO_PTB4, 0);
  779. gpio_direction_output(GPIO_PTB5, 0);
  780. ctrl_outw(0x0600, 0xa40501d4);
  781. ctrl_outw(0x0600, 0xa4050192);
  782. if (gpio_get_value(GPIO_PTB3)) {
  783. printk(KERN_INFO "USB1 function is selected\n");
  784. usb1_common_device.name = "r8a66597_udc";
  785. } else {
  786. printk(KERN_INFO "USB1 host is selected\n");
  787. usb1_common_device.name = "r8a66597_hcd";
  788. }
  789. /* enable LCDC */
  790. gpio_request(GPIO_FN_LCDD23, NULL);
  791. gpio_request(GPIO_FN_LCDD22, NULL);
  792. gpio_request(GPIO_FN_LCDD21, NULL);
  793. gpio_request(GPIO_FN_LCDD20, NULL);
  794. gpio_request(GPIO_FN_LCDD19, NULL);
  795. gpio_request(GPIO_FN_LCDD18, NULL);
  796. gpio_request(GPIO_FN_LCDD17, NULL);
  797. gpio_request(GPIO_FN_LCDD16, NULL);
  798. gpio_request(GPIO_FN_LCDD15, NULL);
  799. gpio_request(GPIO_FN_LCDD14, NULL);
  800. gpio_request(GPIO_FN_LCDD13, NULL);
  801. gpio_request(GPIO_FN_LCDD12, NULL);
  802. gpio_request(GPIO_FN_LCDD11, NULL);
  803. gpio_request(GPIO_FN_LCDD10, NULL);
  804. gpio_request(GPIO_FN_LCDD9, NULL);
  805. gpio_request(GPIO_FN_LCDD8, NULL);
  806. gpio_request(GPIO_FN_LCDD7, NULL);
  807. gpio_request(GPIO_FN_LCDD6, NULL);
  808. gpio_request(GPIO_FN_LCDD5, NULL);
  809. gpio_request(GPIO_FN_LCDD4, NULL);
  810. gpio_request(GPIO_FN_LCDD3, NULL);
  811. gpio_request(GPIO_FN_LCDD2, NULL);
  812. gpio_request(GPIO_FN_LCDD1, NULL);
  813. gpio_request(GPIO_FN_LCDD0, NULL);
  814. gpio_request(GPIO_FN_LCDDISP, NULL);
  815. gpio_request(GPIO_FN_LCDHSYN, NULL);
  816. gpio_request(GPIO_FN_LCDDCK, NULL);
  817. gpio_request(GPIO_FN_LCDVSYN, NULL);
  818. gpio_request(GPIO_FN_LCDDON, NULL);
  819. gpio_request(GPIO_FN_LCDLCLK, NULL);
  820. ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA);
  821. gpio_request(GPIO_PTE6, NULL);
  822. gpio_request(GPIO_PTU1, NULL);
  823. gpio_request(GPIO_PTR1, NULL);
  824. gpio_request(GPIO_PTA2, NULL);
  825. gpio_direction_input(GPIO_PTE6);
  826. gpio_direction_output(GPIO_PTU1, 0);
  827. gpio_direction_output(GPIO_PTR1, 0);
  828. gpio_direction_output(GPIO_PTA2, 0);
  829. /* I/O buffer drive ability is high */
  830. ctrl_outw((ctrl_inw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA);
  831. if (gpio_get_value(GPIO_PTE6)) {
  832. /* DVI */
  833. lcdc_info.clock_source = LCDC_CLK_EXTERNAL;
  834. lcdc_info.ch[0].clock_divider = 1,
  835. lcdc_info.ch[0].lcd_cfg.name = "DVI";
  836. lcdc_info.ch[0].lcd_cfg.xres = 1280;
  837. lcdc_info.ch[0].lcd_cfg.yres = 720;
  838. lcdc_info.ch[0].lcd_cfg.left_margin = 220;
  839. lcdc_info.ch[0].lcd_cfg.right_margin = 110;
  840. lcdc_info.ch[0].lcd_cfg.hsync_len = 40;
  841. lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
  842. lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
  843. lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
  844. gpio_set_value(GPIO_PTA2, 1);
  845. gpio_set_value(GPIO_PTU1, 1);
  846. } else {
  847. /* Panel */
  848. lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
  849. lcdc_info.ch[0].clock_divider = 2,
  850. lcdc_info.ch[0].lcd_cfg.name = "Panel";
  851. lcdc_info.ch[0].lcd_cfg.xres = 800;
  852. lcdc_info.ch[0].lcd_cfg.yres = 480;
  853. lcdc_info.ch[0].lcd_cfg.left_margin = 220;
  854. lcdc_info.ch[0].lcd_cfg.right_margin = 110;
  855. lcdc_info.ch[0].lcd_cfg.hsync_len = 70;
  856. lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
  857. lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
  858. lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
  859. gpio_set_value(GPIO_PTR1, 1);
  860. /* FIXME
  861. *
  862. * LCDDON control is needed for Panel,
  863. * but current sh_mobile_lcdc driver doesn't control it.
  864. * It is temporary correspondence
  865. */
  866. gpio_request(GPIO_PTF4, NULL);
  867. gpio_direction_output(GPIO_PTF4, 1);
  868. /* enable TouchScreen */
  869. i2c_register_board_info(0, &ts_i2c_clients, 1);
  870. set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW);
  871. }
  872. /* enable CEU0 */
  873. gpio_request(GPIO_FN_VIO0_D15, NULL);
  874. gpio_request(GPIO_FN_VIO0_D14, NULL);
  875. gpio_request(GPIO_FN_VIO0_D13, NULL);
  876. gpio_request(GPIO_FN_VIO0_D12, NULL);
  877. gpio_request(GPIO_FN_VIO0_D11, NULL);
  878. gpio_request(GPIO_FN_VIO0_D10, NULL);
  879. gpio_request(GPIO_FN_VIO0_D9, NULL);
  880. gpio_request(GPIO_FN_VIO0_D8, NULL);
  881. gpio_request(GPIO_FN_VIO0_D7, NULL);
  882. gpio_request(GPIO_FN_VIO0_D6, NULL);
  883. gpio_request(GPIO_FN_VIO0_D5, NULL);
  884. gpio_request(GPIO_FN_VIO0_D4, NULL);
  885. gpio_request(GPIO_FN_VIO0_D3, NULL);
  886. gpio_request(GPIO_FN_VIO0_D2, NULL);
  887. gpio_request(GPIO_FN_VIO0_D1, NULL);
  888. gpio_request(GPIO_FN_VIO0_D0, NULL);
  889. gpio_request(GPIO_FN_VIO0_VD, NULL);
  890. gpio_request(GPIO_FN_VIO0_CLK, NULL);
  891. gpio_request(GPIO_FN_VIO0_FLD, NULL);
  892. gpio_request(GPIO_FN_VIO0_HD, NULL);
  893. platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20);
  894. /* enable CEU1 */
  895. gpio_request(GPIO_FN_VIO1_D7, NULL);
  896. gpio_request(GPIO_FN_VIO1_D6, NULL);
  897. gpio_request(GPIO_FN_VIO1_D5, NULL);
  898. gpio_request(GPIO_FN_VIO1_D4, NULL);
  899. gpio_request(GPIO_FN_VIO1_D3, NULL);
  900. gpio_request(GPIO_FN_VIO1_D2, NULL);
  901. gpio_request(GPIO_FN_VIO1_D1, NULL);
  902. gpio_request(GPIO_FN_VIO1_D0, NULL);
  903. gpio_request(GPIO_FN_VIO1_FLD, NULL);
  904. gpio_request(GPIO_FN_VIO1_HD, NULL);
  905. gpio_request(GPIO_FN_VIO1_VD, NULL);
  906. gpio_request(GPIO_FN_VIO1_CLK, NULL);
  907. platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20);
  908. /* enable KEYSC */
  909. gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
  910. gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
  911. gpio_request(GPIO_FN_KEYOUT3, NULL);
  912. gpio_request(GPIO_FN_KEYOUT2, NULL);
  913. gpio_request(GPIO_FN_KEYOUT1, NULL);
  914. gpio_request(GPIO_FN_KEYOUT0, NULL);
  915. gpio_request(GPIO_FN_KEYIN0, NULL);
  916. /* enable user debug switch */
  917. gpio_request(GPIO_PTR0, NULL);
  918. gpio_request(GPIO_PTR4, NULL);
  919. gpio_request(GPIO_PTR5, NULL);
  920. gpio_request(GPIO_PTR6, NULL);
  921. gpio_direction_input(GPIO_PTR0);
  922. gpio_direction_input(GPIO_PTR4);
  923. gpio_direction_input(GPIO_PTR5);
  924. gpio_direction_input(GPIO_PTR6);
  925. #ifdef CONFIG_MFD_SH_MOBILE_SDHI
  926. /* enable SDHI0 on CN11 (needs DS2.4 set to ON) */
  927. gpio_request(GPIO_FN_SDHI0CD, NULL);
  928. gpio_request(GPIO_FN_SDHI0WP, NULL);
  929. gpio_request(GPIO_FN_SDHI0CMD, NULL);
  930. gpio_request(GPIO_FN_SDHI0CLK, NULL);
  931. gpio_request(GPIO_FN_SDHI0D3, NULL);
  932. gpio_request(GPIO_FN_SDHI0D2, NULL);
  933. gpio_request(GPIO_FN_SDHI0D1, NULL);
  934. gpio_request(GPIO_FN_SDHI0D0, NULL);
  935. gpio_request(GPIO_PTB6, NULL);
  936. gpio_direction_output(GPIO_PTB6, 0);
  937. /* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */
  938. gpio_request(GPIO_FN_SDHI1CD, NULL);
  939. gpio_request(GPIO_FN_SDHI1WP, NULL);
  940. gpio_request(GPIO_FN_SDHI1CMD, NULL);
  941. gpio_request(GPIO_FN_SDHI1CLK, NULL);
  942. gpio_request(GPIO_FN_SDHI1D3, NULL);
  943. gpio_request(GPIO_FN_SDHI1D2, NULL);
  944. gpio_request(GPIO_FN_SDHI1D1, NULL);
  945. gpio_request(GPIO_FN_SDHI1D0, NULL);
  946. gpio_request(GPIO_PTB7, NULL);
  947. gpio_direction_output(GPIO_PTB7, 0);
  948. /* I/O buffer drive ability is high for SDHI1 */
  949. ctrl_outw((ctrl_inw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA);
  950. #else
  951. /* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */
  952. gpio_request(GPIO_FN_MSIOF0_TXD, NULL);
  953. gpio_request(GPIO_FN_MSIOF0_RXD, NULL);
  954. gpio_request(GPIO_FN_MSIOF0_TSCK, NULL);
  955. gpio_request(GPIO_PTM4, NULL); /* software CS control of TSYNC pin */
  956. gpio_direction_output(GPIO_PTM4, 1); /* active low CS */
  957. gpio_request(GPIO_PTB6, NULL); /* 3.3V power control */
  958. gpio_direction_output(GPIO_PTB6, 0); /* disable power by default */
  959. gpio_request(GPIO_PTY6, NULL); /* write protect */
  960. gpio_direction_input(GPIO_PTY6);
  961. gpio_request(GPIO_PTY7, NULL); /* card detect */
  962. gpio_direction_input(GPIO_PTY7);
  963. spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus));
  964. #endif
  965. /* enable Video */
  966. gpio_request(GPIO_PTU2, NULL);
  967. gpio_direction_output(GPIO_PTU2, 1);
  968. /* enable Camera */
  969. gpio_request(GPIO_PTA3, NULL);
  970. gpio_request(GPIO_PTA4, NULL);
  971. gpio_direction_output(GPIO_PTA3, 0);
  972. gpio_direction_output(GPIO_PTA4, 0);
  973. /* enable FSI */
  974. gpio_request(GPIO_FN_FSIMCKB, NULL);
  975. gpio_request(GPIO_FN_FSIIBSD, NULL);
  976. gpio_request(GPIO_FN_FSIOBSD, NULL);
  977. gpio_request(GPIO_FN_FSIIBBCK, NULL);
  978. gpio_request(GPIO_FN_FSIIBLRCK, NULL);
  979. gpio_request(GPIO_FN_FSIOBBCK, NULL);
  980. gpio_request(GPIO_FN_FSIOBLRCK, NULL);
  981. gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
  982. /* change parent of FSI B */
  983. clk = clk_get(NULL, "fsib_clk");
  984. clk_register(&fsimckb_clk);
  985. clk_set_parent(clk, &fsimckb_clk);
  986. clk_set_rate(clk, 11000);
  987. clk_set_rate(&fsimckb_clk, 11000);
  988. clk_put(clk);
  989. gpio_request(GPIO_PTU0, NULL);
  990. gpio_direction_output(GPIO_PTU0, 0);
  991. mdelay(20);
  992. /* enable I2C device */
  993. i2c_register_board_info(0, i2c0_devices,
  994. ARRAY_SIZE(i2c0_devices));
  995. i2c_register_board_info(1, i2c1_devices,
  996. ARRAY_SIZE(i2c1_devices));
  997. return platform_add_devices(ecovec_devices,
  998. ARRAY_SIZE(ecovec_devices));
  999. }
  1000. arch_initcall(arch_setup);
  1001. static int __init devices_setup(void)
  1002. {
  1003. sh_eth_init(&sh_eth_plat);
  1004. return 0;
  1005. }
  1006. device_initcall(devices_setup);
  1007. static struct sh_machine_vector mv_ecovec __initmv = {
  1008. .mv_name = "R0P7724 (EcoVec)",
  1009. };