pq2ads-pci-pic.c 4.2 KB

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  1. /*
  2. * PQ2 ADS-style PCI interrupt controller
  3. *
  4. * Copyright 2007 Freescale Semiconductor, Inc.
  5. * Author: Scott Wood <scottwood@freescale.com>
  6. *
  7. * Loosely based on mpc82xx ADS support by Vitaly Bordug <vbordug@ru.mvista.com>
  8. * Copyright (c) 2006 MontaVista Software, Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License version 2 as published
  12. * by the Free Software Foundation.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/irq.h>
  17. #include <linux/types.h>
  18. #include <linux/bootmem.h>
  19. #include <asm/io.h>
  20. #include <asm/prom.h>
  21. #include <asm/cpm2.h>
  22. #include "pq2.h"
  23. static DEFINE_SPINLOCK(pci_pic_lock);
  24. struct pq2ads_pci_pic {
  25. struct device_node *node;
  26. struct irq_host *host;
  27. struct {
  28. u32 stat;
  29. u32 mask;
  30. } __iomem *regs;
  31. };
  32. #define NUM_IRQS 32
  33. static void pq2ads_pci_mask_irq(unsigned int virq)
  34. {
  35. struct pq2ads_pci_pic *priv = get_irq_chip_data(virq);
  36. int irq = NUM_IRQS - virq_to_hw(virq) - 1;
  37. if (irq != -1) {
  38. unsigned long flags;
  39. spin_lock_irqsave(&pci_pic_lock, flags);
  40. setbits32(&priv->regs->mask, 1 << irq);
  41. mb();
  42. spin_unlock_irqrestore(&pci_pic_lock, flags);
  43. }
  44. }
  45. static void pq2ads_pci_unmask_irq(unsigned int virq)
  46. {
  47. struct pq2ads_pci_pic *priv = get_irq_chip_data(virq);
  48. int irq = NUM_IRQS - virq_to_hw(virq) - 1;
  49. if (irq != -1) {
  50. unsigned long flags;
  51. spin_lock_irqsave(&pci_pic_lock, flags);
  52. clrbits32(&priv->regs->mask, 1 << irq);
  53. spin_unlock_irqrestore(&pci_pic_lock, flags);
  54. }
  55. }
  56. static struct irq_chip pq2ads_pci_ic = {
  57. .name = "PQ2 ADS PCI",
  58. .end = pq2ads_pci_unmask_irq,
  59. .mask = pq2ads_pci_mask_irq,
  60. .mask_ack = pq2ads_pci_mask_irq,
  61. .ack = pq2ads_pci_mask_irq,
  62. .unmask = pq2ads_pci_unmask_irq,
  63. .enable = pq2ads_pci_unmask_irq,
  64. .disable = pq2ads_pci_mask_irq
  65. };
  66. static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
  67. {
  68. struct pq2ads_pci_pic *priv = desc->handler_data;
  69. u32 stat, mask, pend;
  70. int bit;
  71. for (;;) {
  72. stat = in_be32(&priv->regs->stat);
  73. mask = in_be32(&priv->regs->mask);
  74. pend = stat & ~mask;
  75. if (!pend)
  76. break;
  77. for (bit = 0; pend != 0; ++bit, pend <<= 1) {
  78. if (pend & 0x80000000) {
  79. int virq = irq_linear_revmap(priv->host, bit);
  80. generic_handle_irq(virq);
  81. }
  82. }
  83. }
  84. }
  85. static int pci_pic_host_map(struct irq_host *h, unsigned int virq,
  86. irq_hw_number_t hw)
  87. {
  88. irq_to_desc(virq)->status |= IRQ_LEVEL;
  89. set_irq_chip_data(virq, h->host_data);
  90. set_irq_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
  91. return 0;
  92. }
  93. static void pci_host_unmap(struct irq_host *h, unsigned int virq)
  94. {
  95. /* remove chip and handler */
  96. set_irq_chip_data(virq, NULL);
  97. set_irq_chip(virq, NULL);
  98. }
  99. static struct irq_host_ops pci_pic_host_ops = {
  100. .map = pci_pic_host_map,
  101. .unmap = pci_host_unmap,
  102. };
  103. int __init pq2ads_pci_init_irq(void)
  104. {
  105. struct pq2ads_pci_pic *priv;
  106. struct irq_host *host;
  107. struct device_node *np;
  108. int ret = -ENODEV;
  109. int irq;
  110. np = of_find_compatible_node(NULL, NULL, "fsl,pq2ads-pci-pic");
  111. if (!np) {
  112. printk(KERN_ERR "No pci pic node in device tree.\n");
  113. of_node_put(np);
  114. goto out;
  115. }
  116. irq = irq_of_parse_and_map(np, 0);
  117. if (irq == NO_IRQ) {
  118. printk(KERN_ERR "No interrupt in pci pic node.\n");
  119. of_node_put(np);
  120. goto out;
  121. }
  122. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  123. if (!priv) {
  124. of_node_put(np);
  125. ret = -ENOMEM;
  126. goto out_unmap_irq;
  127. }
  128. /* PCI interrupt controller registers: status and mask */
  129. priv->regs = of_iomap(np, 0);
  130. if (!priv->regs) {
  131. printk(KERN_ERR "Cannot map PCI PIC registers.\n");
  132. goto out_free_bootmem;
  133. }
  134. /* mask all PCI interrupts */
  135. out_be32(&priv->regs->mask, ~0);
  136. mb();
  137. host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, NUM_IRQS,
  138. &pci_pic_host_ops, NUM_IRQS);
  139. if (!host) {
  140. ret = -ENOMEM;
  141. goto out_unmap_regs;
  142. }
  143. host->host_data = priv;
  144. priv->host = host;
  145. host->host_data = priv;
  146. set_irq_data(irq, priv);
  147. set_irq_chained_handler(irq, pq2ads_pci_irq_demux);
  148. of_node_put(np);
  149. return 0;
  150. out_unmap_regs:
  151. iounmap(priv->regs);
  152. out_free_bootmem:
  153. free_bootmem((unsigned long)priv,
  154. sizeof(struct pq2ads_pci_pic));
  155. of_node_put(np);
  156. out_unmap_irq:
  157. irq_dispose_mapping(irq);
  158. out:
  159. return ret;
  160. }