mpc52xx_lpbfifo.c 15 KB

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  1. /*
  2. * LocalPlus Bus FIFO driver for the Freescale MPC52xx.
  3. *
  4. * Copyright (C) 2009 Secret Lab Technologies Ltd.
  5. *
  6. * This file is released under the GPLv2
  7. *
  8. * Todo:
  9. * - Add support for multiple requests to be queued.
  10. */
  11. #include <linux/interrupt.h>
  12. #include <linux/kernel.h>
  13. #include <linux/of.h>
  14. #include <linux/of_platform.h>
  15. #include <linux/spinlock.h>
  16. #include <asm/io.h>
  17. #include <asm/prom.h>
  18. #include <asm/mpc52xx.h>
  19. #include <asm/time.h>
  20. #include <sysdev/bestcomm/bestcomm.h>
  21. #include <sysdev/bestcomm/bestcomm_priv.h>
  22. #include <sysdev/bestcomm/gen_bd.h>
  23. MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
  24. MODULE_DESCRIPTION("MPC5200 LocalPlus FIFO device driver");
  25. MODULE_LICENSE("GPL");
  26. #define LPBFIFO_REG_PACKET_SIZE (0x00)
  27. #define LPBFIFO_REG_START_ADDRESS (0x04)
  28. #define LPBFIFO_REG_CONTROL (0x08)
  29. #define LPBFIFO_REG_ENABLE (0x0C)
  30. #define LPBFIFO_REG_BYTES_DONE_STATUS (0x14)
  31. #define LPBFIFO_REG_FIFO_DATA (0x40)
  32. #define LPBFIFO_REG_FIFO_STATUS (0x44)
  33. #define LPBFIFO_REG_FIFO_CONTROL (0x48)
  34. #define LPBFIFO_REG_FIFO_ALARM (0x4C)
  35. struct mpc52xx_lpbfifo {
  36. struct device *dev;
  37. phys_addr_t regs_phys;
  38. void __iomem *regs;
  39. int irq;
  40. spinlock_t lock;
  41. struct bcom_task *bcom_tx_task;
  42. struct bcom_task *bcom_rx_task;
  43. struct bcom_task *bcom_cur_task;
  44. /* Current state data */
  45. struct mpc52xx_lpbfifo_request *req;
  46. int dma_irqs_enabled;
  47. };
  48. /* The MPC5200 has only one fifo, so only need one instance structure */
  49. static struct mpc52xx_lpbfifo lpbfifo;
  50. /**
  51. * mpc52xx_lpbfifo_kick - Trigger the next block of data to be transfered
  52. */
  53. static void mpc52xx_lpbfifo_kick(struct mpc52xx_lpbfifo_request *req)
  54. {
  55. size_t transfer_size = req->size - req->pos;
  56. struct bcom_bd *bd;
  57. void __iomem *reg;
  58. u32 *data;
  59. int i;
  60. int bit_fields;
  61. int dma = !(req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA);
  62. int write = req->flags & MPC52XX_LPBFIFO_FLAG_WRITE;
  63. int poll_dma = req->flags & MPC52XX_LPBFIFO_FLAG_POLL_DMA;
  64. /* Set and clear the reset bits; is good practice in User Manual */
  65. out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
  66. /* set master enable bit */
  67. out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x00000001);
  68. if (!dma) {
  69. /* While the FIFO can be setup for transfer sizes as large as
  70. * 16M-1, the FIFO itself is only 512 bytes deep and it does
  71. * not generate interrupts for FIFO full events (only transfer
  72. * complete will raise an IRQ). Therefore when not using
  73. * Bestcomm to drive the FIFO it needs to either be polled, or
  74. * transfers need to constrained to the size of the fifo.
  75. *
  76. * This driver restricts the size of the transfer
  77. */
  78. if (transfer_size > 512)
  79. transfer_size = 512;
  80. /* Load the FIFO with data */
  81. if (write) {
  82. reg = lpbfifo.regs + LPBFIFO_REG_FIFO_DATA;
  83. data = req->data + req->pos;
  84. for (i = 0; i < transfer_size; i += 4)
  85. out_be32(reg, *data++);
  86. }
  87. /* Unmask both error and completion irqs */
  88. out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x00000301);
  89. } else {
  90. /* Choose the correct direction
  91. *
  92. * Configure the watermarks so DMA will always complete correctly.
  93. * It may be worth experimenting with the ALARM value to see if
  94. * there is a performance impacit. However, if it is wrong there
  95. * is a risk of DMA not transferring the last chunk of data
  96. */
  97. if (write) {
  98. out_be32(lpbfifo.regs + LPBFIFO_REG_FIFO_ALARM, 0x1e4);
  99. out_8(lpbfifo.regs + LPBFIFO_REG_FIFO_CONTROL, 7);
  100. lpbfifo.bcom_cur_task = lpbfifo.bcom_tx_task;
  101. } else {
  102. out_be32(lpbfifo.regs + LPBFIFO_REG_FIFO_ALARM, 0x1ff);
  103. out_8(lpbfifo.regs + LPBFIFO_REG_FIFO_CONTROL, 0);
  104. lpbfifo.bcom_cur_task = lpbfifo.bcom_rx_task;
  105. if (poll_dma) {
  106. if (lpbfifo.dma_irqs_enabled) {
  107. disable_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task));
  108. lpbfifo.dma_irqs_enabled = 0;
  109. }
  110. } else {
  111. if (!lpbfifo.dma_irqs_enabled) {
  112. enable_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task));
  113. lpbfifo.dma_irqs_enabled = 1;
  114. }
  115. }
  116. }
  117. bd = bcom_prepare_next_buffer(lpbfifo.bcom_cur_task);
  118. bd->status = transfer_size;
  119. if (!write) {
  120. /*
  121. * In the DMA read case, the DMA doesn't complete,
  122. * possibly due to incorrect watermarks in the ALARM
  123. * and CONTROL regs. For now instead of trying to
  124. * determine the right watermarks that will make this
  125. * work, just increase the number of bytes the FIFO is
  126. * expecting.
  127. *
  128. * When submitting another operation, the FIFO will get
  129. * reset, so the condition of the FIFO waiting for a
  130. * non-existent 4 bytes will get cleared.
  131. */
  132. transfer_size += 4; /* BLECH! */
  133. }
  134. bd->data[0] = req->data_phys + req->pos;
  135. bcom_submit_next_buffer(lpbfifo.bcom_cur_task, NULL);
  136. /* error irq & master enabled bit */
  137. bit_fields = 0x00000201;
  138. /* Unmask irqs */
  139. if (write && (!poll_dma))
  140. bit_fields |= 0x00000100; /* completion irq too */
  141. out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, bit_fields);
  142. }
  143. /* Set transfer size, width, chip select and READ mode */
  144. out_be32(lpbfifo.regs + LPBFIFO_REG_START_ADDRESS,
  145. req->offset + req->pos);
  146. out_be32(lpbfifo.regs + LPBFIFO_REG_PACKET_SIZE, transfer_size);
  147. bit_fields = req->cs << 24 | 0x000008;
  148. if (!write)
  149. bit_fields |= 0x010000; /* read mode */
  150. out_be32(lpbfifo.regs + LPBFIFO_REG_CONTROL, bit_fields);
  151. /* Kick it off */
  152. out_8(lpbfifo.regs + LPBFIFO_REG_PACKET_SIZE, 0x01);
  153. if (dma)
  154. bcom_enable(lpbfifo.bcom_cur_task);
  155. }
  156. /**
  157. * mpc52xx_lpbfifo_irq - IRQ handler for LPB FIFO
  158. *
  159. * On transmit, the dma completion irq triggers before the fifo completion
  160. * triggers. Handle the dma completion here instead of the LPB FIFO Bestcomm
  161. * task completion irq becuase everyting is not really done until the LPB FIFO
  162. * completion irq triggers.
  163. *
  164. * In other words:
  165. * For DMA, on receive, the "Fat Lady" is the bestcom completion irq. on
  166. * transmit, the fifo completion irq is the "Fat Lady". The opera (or in this
  167. * case the DMA/FIFO operation) is not finished until the "Fat Lady" sings.
  168. *
  169. * Reasons for entering this routine:
  170. * 1) PIO mode rx and tx completion irq
  171. * 2) DMA interrupt mode tx completion irq
  172. * 3) DMA polled mode tx
  173. *
  174. * Exit conditions:
  175. * 1) Transfer aborted
  176. * 2) FIFO complete without DMA; more data to do
  177. * 3) FIFO complete without DMA; all data transfered
  178. * 4) FIFO complete using DMA
  179. *
  180. * Condition 1 can occur regardless of whether or not DMA is used.
  181. * It requires executing the callback to report the error and exiting
  182. * immediately.
  183. *
  184. * Condition 2 requires programming the FIFO with the next block of data
  185. *
  186. * Condition 3 requires executing the callback to report completion
  187. *
  188. * Condition 4 means the same as 3, except that we also retrieve the bcom
  189. * buffer so DMA doesn't get clogged up.
  190. *
  191. * To make things trickier, the spinlock must be dropped before
  192. * executing the callback, otherwise we could end up with a deadlock
  193. * or nested spinlock condition. The out path is non-trivial, so
  194. * extra fiddling is done to make sure all paths lead to the same
  195. * outbound code.
  196. */
  197. static irqreturn_t mpc52xx_lpbfifo_irq(int irq, void *dev_id)
  198. {
  199. struct mpc52xx_lpbfifo_request *req;
  200. u32 status = in_8(lpbfifo.regs + LPBFIFO_REG_BYTES_DONE_STATUS);
  201. void __iomem *reg;
  202. u32 *data;
  203. int count, i;
  204. int do_callback = 0;
  205. u32 ts;
  206. unsigned long flags;
  207. int dma, write, poll_dma;
  208. spin_lock_irqsave(&lpbfifo.lock, flags);
  209. ts = get_tbl();
  210. req = lpbfifo.req;
  211. if (!req) {
  212. spin_unlock_irqrestore(&lpbfifo.lock, flags);
  213. pr_err("bogus LPBFIFO IRQ\n");
  214. return IRQ_HANDLED;
  215. }
  216. dma = !(req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA);
  217. write = req->flags & MPC52XX_LPBFIFO_FLAG_WRITE;
  218. poll_dma = req->flags & MPC52XX_LPBFIFO_FLAG_POLL_DMA;
  219. if (dma && !write) {
  220. spin_unlock_irqrestore(&lpbfifo.lock, flags);
  221. pr_err("bogus LPBFIFO IRQ (dma and not writting)\n");
  222. return IRQ_HANDLED;
  223. }
  224. if ((status & 0x01) == 0) {
  225. goto out;
  226. }
  227. /* check abort bit */
  228. if (status & 0x10) {
  229. out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
  230. do_callback = 1;
  231. goto out;
  232. }
  233. /* Read result from hardware */
  234. count = in_be32(lpbfifo.regs + LPBFIFO_REG_BYTES_DONE_STATUS);
  235. count &= 0x00ffffff;
  236. if (!dma && !write) {
  237. /* copy the data out of the FIFO */
  238. reg = lpbfifo.regs + LPBFIFO_REG_FIFO_DATA;
  239. data = req->data + req->pos;
  240. for (i = 0; i < count; i += 4)
  241. *data++ = in_be32(reg);
  242. }
  243. /* Update transfer position and count */
  244. req->pos += count;
  245. /* Decide what to do next */
  246. if (req->size - req->pos)
  247. mpc52xx_lpbfifo_kick(req); /* more work to do */
  248. else
  249. do_callback = 1;
  250. out:
  251. /* Clear the IRQ */
  252. out_8(lpbfifo.regs + LPBFIFO_REG_BYTES_DONE_STATUS, 0x01);
  253. if (dma && (status & 0x11)) {
  254. /*
  255. * Count the DMA as complete only when the FIFO completion
  256. * status or abort bits are set.
  257. *
  258. * (status & 0x01) should always be the case except sometimes
  259. * when using polled DMA.
  260. *
  261. * (status & 0x10) {transfer aborted}: This case needs more
  262. * testing.
  263. */
  264. bcom_retrieve_buffer(lpbfifo.bcom_cur_task, &status, NULL);
  265. }
  266. req->last_byte = ((u8 *)req->data)[req->size - 1];
  267. /* When the do_callback flag is set; it means the transfer is finished
  268. * so set the FIFO as idle */
  269. if (do_callback)
  270. lpbfifo.req = NULL;
  271. if (irq != 0) /* don't increment on polled case */
  272. req->irq_count++;
  273. req->irq_ticks += get_tbl() - ts;
  274. spin_unlock_irqrestore(&lpbfifo.lock, flags);
  275. /* Spinlock is released; it is now safe to call the callback */
  276. if (do_callback && req->callback)
  277. req->callback(req);
  278. return IRQ_HANDLED;
  279. }
  280. /**
  281. * mpc52xx_lpbfifo_bcom_irq - IRQ handler for LPB FIFO Bestcomm task
  282. *
  283. * Only used when receiving data.
  284. */
  285. static irqreturn_t mpc52xx_lpbfifo_bcom_irq(int irq, void *dev_id)
  286. {
  287. struct mpc52xx_lpbfifo_request *req;
  288. unsigned long flags;
  289. u32 status;
  290. u32 ts;
  291. spin_lock_irqsave(&lpbfifo.lock, flags);
  292. ts = get_tbl();
  293. req = lpbfifo.req;
  294. if (!req || (req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA)) {
  295. spin_unlock_irqrestore(&lpbfifo.lock, flags);
  296. return IRQ_HANDLED;
  297. }
  298. if (irq != 0) /* don't increment on polled case */
  299. req->irq_count++;
  300. if (!bcom_buffer_done(lpbfifo.bcom_cur_task)) {
  301. spin_unlock_irqrestore(&lpbfifo.lock, flags);
  302. req->buffer_not_done_cnt++;
  303. if ((req->buffer_not_done_cnt % 1000) == 0)
  304. pr_err("transfer stalled\n");
  305. return IRQ_HANDLED;
  306. }
  307. bcom_retrieve_buffer(lpbfifo.bcom_cur_task, &status, NULL);
  308. req->last_byte = ((u8 *)req->data)[req->size - 1];
  309. req->pos = status & 0x00ffffff;
  310. /* Mark the FIFO as idle */
  311. lpbfifo.req = NULL;
  312. /* Release the lock before calling out to the callback. */
  313. req->irq_ticks += get_tbl() - ts;
  314. spin_unlock_irqrestore(&lpbfifo.lock, flags);
  315. if (req->callback)
  316. req->callback(req);
  317. return IRQ_HANDLED;
  318. }
  319. /**
  320. * mpc52xx_lpbfifo_bcom_poll - Poll for DMA completion
  321. */
  322. void mpc52xx_lpbfifo_poll(void)
  323. {
  324. struct mpc52xx_lpbfifo_request *req = lpbfifo.req;
  325. int dma = !(req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA);
  326. int write = req->flags & MPC52XX_LPBFIFO_FLAG_WRITE;
  327. /*
  328. * For more information, see comments on the "Fat Lady"
  329. */
  330. if (dma && write)
  331. mpc52xx_lpbfifo_irq(0, NULL);
  332. else
  333. mpc52xx_lpbfifo_bcom_irq(0, NULL);
  334. }
  335. EXPORT_SYMBOL(mpc52xx_lpbfifo_poll);
  336. /**
  337. * mpc52xx_lpbfifo_submit - Submit an LPB FIFO transfer request.
  338. * @req: Pointer to request structure
  339. */
  340. int mpc52xx_lpbfifo_submit(struct mpc52xx_lpbfifo_request *req)
  341. {
  342. unsigned long flags;
  343. if (!lpbfifo.regs)
  344. return -ENODEV;
  345. spin_lock_irqsave(&lpbfifo.lock, flags);
  346. /* If the req pointer is already set, then a transfer is in progress */
  347. if (lpbfifo.req) {
  348. spin_unlock_irqrestore(&lpbfifo.lock, flags);
  349. return -EBUSY;
  350. }
  351. /* Setup the transfer */
  352. lpbfifo.req = req;
  353. req->irq_count = 0;
  354. req->irq_ticks = 0;
  355. req->buffer_not_done_cnt = 0;
  356. req->pos = 0;
  357. mpc52xx_lpbfifo_kick(req);
  358. spin_unlock_irqrestore(&lpbfifo.lock, flags);
  359. return 0;
  360. }
  361. EXPORT_SYMBOL(mpc52xx_lpbfifo_submit);
  362. void mpc52xx_lpbfifo_abort(struct mpc52xx_lpbfifo_request *req)
  363. {
  364. unsigned long flags;
  365. spin_lock_irqsave(&lpbfifo.lock, flags);
  366. if (lpbfifo.req == req) {
  367. /* Put it into reset and clear the state */
  368. bcom_gen_bd_rx_reset(lpbfifo.bcom_rx_task);
  369. bcom_gen_bd_tx_reset(lpbfifo.bcom_tx_task);
  370. out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
  371. lpbfifo.req = NULL;
  372. }
  373. spin_unlock_irqrestore(&lpbfifo.lock, flags);
  374. }
  375. EXPORT_SYMBOL(mpc52xx_lpbfifo_abort);
  376. static int __devinit
  377. mpc52xx_lpbfifo_probe(struct of_device *op, const struct of_device_id *match)
  378. {
  379. struct resource res;
  380. int rc = -ENOMEM;
  381. if (lpbfifo.dev != NULL)
  382. return -ENOSPC;
  383. lpbfifo.irq = irq_of_parse_and_map(op->node, 0);
  384. if (!lpbfifo.irq)
  385. return -ENODEV;
  386. if (of_address_to_resource(op->node, 0, &res))
  387. return -ENODEV;
  388. lpbfifo.regs_phys = res.start;
  389. lpbfifo.regs = of_iomap(op->node, 0);
  390. if (!lpbfifo.regs)
  391. return -ENOMEM;
  392. spin_lock_init(&lpbfifo.lock);
  393. /* Put FIFO into reset */
  394. out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
  395. /* Register the interrupt handler */
  396. rc = request_irq(lpbfifo.irq, mpc52xx_lpbfifo_irq, 0,
  397. "mpc52xx-lpbfifo", &lpbfifo);
  398. if (rc)
  399. goto err_irq;
  400. /* Request the Bestcomm receive (fifo --> memory) task and IRQ */
  401. lpbfifo.bcom_rx_task =
  402. bcom_gen_bd_rx_init(2, res.start + LPBFIFO_REG_FIFO_DATA,
  403. BCOM_INITIATOR_SCLPC, BCOM_IPR_SCLPC,
  404. 16*1024*1024);
  405. if (!lpbfifo.bcom_rx_task)
  406. goto err_bcom_rx;
  407. rc = request_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task),
  408. mpc52xx_lpbfifo_bcom_irq, 0,
  409. "mpc52xx-lpbfifo-rx", &lpbfifo);
  410. if (rc)
  411. goto err_bcom_rx_irq;
  412. /* Request the Bestcomm transmit (memory --> fifo) task and IRQ */
  413. lpbfifo.bcom_tx_task =
  414. bcom_gen_bd_tx_init(2, res.start + LPBFIFO_REG_FIFO_DATA,
  415. BCOM_INITIATOR_SCLPC, BCOM_IPR_SCLPC);
  416. if (!lpbfifo.bcom_tx_task)
  417. goto err_bcom_tx;
  418. lpbfifo.dev = &op->dev;
  419. return 0;
  420. err_bcom_tx:
  421. free_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task), &lpbfifo);
  422. err_bcom_rx_irq:
  423. bcom_gen_bd_rx_release(lpbfifo.bcom_rx_task);
  424. err_bcom_rx:
  425. err_irq:
  426. iounmap(lpbfifo.regs);
  427. lpbfifo.regs = NULL;
  428. dev_err(&op->dev, "mpc52xx_lpbfifo_probe() failed\n");
  429. return -ENODEV;
  430. }
  431. static int __devexit mpc52xx_lpbfifo_remove(struct of_device *op)
  432. {
  433. if (lpbfifo.dev != &op->dev)
  434. return 0;
  435. /* Put FIFO in reset */
  436. out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
  437. /* Release the bestcomm transmit task */
  438. free_irq(bcom_get_task_irq(lpbfifo.bcom_tx_task), &lpbfifo);
  439. bcom_gen_bd_tx_release(lpbfifo.bcom_tx_task);
  440. /* Release the bestcomm receive task */
  441. free_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task), &lpbfifo);
  442. bcom_gen_bd_rx_release(lpbfifo.bcom_rx_task);
  443. free_irq(lpbfifo.irq, &lpbfifo);
  444. iounmap(lpbfifo.regs);
  445. lpbfifo.regs = NULL;
  446. lpbfifo.dev = NULL;
  447. return 0;
  448. }
  449. static struct of_device_id mpc52xx_lpbfifo_match[] __devinitconst = {
  450. { .compatible = "fsl,mpc5200-lpbfifo", },
  451. {},
  452. };
  453. static struct of_platform_driver mpc52xx_lpbfifo_driver = {
  454. .owner = THIS_MODULE,
  455. .name = "mpc52xx-lpbfifo",
  456. .match_table = mpc52xx_lpbfifo_match,
  457. .probe = mpc52xx_lpbfifo_probe,
  458. .remove = __devexit_p(mpc52xx_lpbfifo_remove),
  459. };
  460. /***********************************************************************
  461. * Module init/exit
  462. */
  463. static int __init mpc52xx_lpbfifo_init(void)
  464. {
  465. pr_debug("Registering LocalPlus bus FIFO driver\n");
  466. return of_register_platform_driver(&mpc52xx_lpbfifo_driver);
  467. }
  468. module_init(mpc52xx_lpbfifo_init);
  469. static void __exit mpc52xx_lpbfifo_exit(void)
  470. {
  471. pr_debug("Unregistering LocalPlus bus FIFO driver\n");
  472. of_unregister_platform_driver(&mpc52xx_lpbfifo_driver);
  473. }
  474. module_exit(mpc52xx_lpbfifo_exit);