fsl_booke_mmu.c 6.2 KB

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  1. /*
  2. * Modifications by Kumar Gala (galak@kernel.crashing.org) to support
  3. * E500 Book E processors.
  4. *
  5. * Copyright 2004 Freescale Semiconductor, Inc
  6. *
  7. * This file contains the routines for initializing the MMU
  8. * on the 4xx series of chips.
  9. * -- paulus
  10. *
  11. * Derived from arch/ppc/mm/init.c:
  12. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  13. *
  14. * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
  15. * and Cort Dougan (PReP) (cort@cs.nmt.edu)
  16. * Copyright (C) 1996 Paul Mackerras
  17. *
  18. * Derived from "arch/i386/mm/init.c"
  19. * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
  20. *
  21. * This program is free software; you can redistribute it and/or
  22. * modify it under the terms of the GNU General Public License
  23. * as published by the Free Software Foundation; either version
  24. * 2 of the License, or (at your option) any later version.
  25. *
  26. */
  27. #include <linux/signal.h>
  28. #include <linux/sched.h>
  29. #include <linux/kernel.h>
  30. #include <linux/errno.h>
  31. #include <linux/string.h>
  32. #include <linux/types.h>
  33. #include <linux/ptrace.h>
  34. #include <linux/mman.h>
  35. #include <linux/mm.h>
  36. #include <linux/swap.h>
  37. #include <linux/stddef.h>
  38. #include <linux/vmalloc.h>
  39. #include <linux/init.h>
  40. #include <linux/delay.h>
  41. #include <linux/highmem.h>
  42. #include <asm/pgalloc.h>
  43. #include <asm/prom.h>
  44. #include <asm/io.h>
  45. #include <asm/mmu_context.h>
  46. #include <asm/pgtable.h>
  47. #include <asm/mmu.h>
  48. #include <asm/uaccess.h>
  49. #include <asm/smp.h>
  50. #include <asm/machdep.h>
  51. #include <asm/setup.h>
  52. #include "mmu_decl.h"
  53. unsigned int tlbcam_index;
  54. #define NUM_TLBCAMS (64)
  55. #if defined(CONFIG_LOWMEM_CAM_NUM_BOOL) && (CONFIG_LOWMEM_CAM_NUM >= NUM_TLBCAMS)
  56. #error "LOWMEM_CAM_NUM must be less than NUM_TLBCAMS"
  57. #endif
  58. struct tlbcam {
  59. u32 MAS0;
  60. u32 MAS1;
  61. unsigned long MAS2;
  62. u32 MAS3;
  63. u32 MAS7;
  64. } TLBCAM[NUM_TLBCAMS];
  65. struct tlbcamrange {
  66. unsigned long start;
  67. unsigned long limit;
  68. phys_addr_t phys;
  69. } tlbcam_addrs[NUM_TLBCAMS];
  70. extern unsigned int tlbcam_index;
  71. unsigned long tlbcam_sz(int idx)
  72. {
  73. return tlbcam_addrs[idx].limit - tlbcam_addrs[idx].start + 1;
  74. }
  75. /*
  76. * Return PA for this VA if it is mapped by a CAM, or 0
  77. */
  78. phys_addr_t v_mapped_by_tlbcam(unsigned long va)
  79. {
  80. int b;
  81. for (b = 0; b < tlbcam_index; ++b)
  82. if (va >= tlbcam_addrs[b].start && va < tlbcam_addrs[b].limit)
  83. return tlbcam_addrs[b].phys + (va - tlbcam_addrs[b].start);
  84. return 0;
  85. }
  86. /*
  87. * Return VA for a given PA or 0 if not mapped
  88. */
  89. unsigned long p_mapped_by_tlbcam(phys_addr_t pa)
  90. {
  91. int b;
  92. for (b = 0; b < tlbcam_index; ++b)
  93. if (pa >= tlbcam_addrs[b].phys
  94. && pa < (tlbcam_addrs[b].limit-tlbcam_addrs[b].start)
  95. +tlbcam_addrs[b].phys)
  96. return tlbcam_addrs[b].start+(pa-tlbcam_addrs[b].phys);
  97. return 0;
  98. }
  99. void loadcam_entry(int idx)
  100. {
  101. mtspr(SPRN_MAS0, TLBCAM[idx].MAS0);
  102. mtspr(SPRN_MAS1, TLBCAM[idx].MAS1);
  103. mtspr(SPRN_MAS2, TLBCAM[idx].MAS2);
  104. mtspr(SPRN_MAS3, TLBCAM[idx].MAS3);
  105. if (cur_cpu_spec->cpu_features & MMU_FTR_BIG_PHYS)
  106. mtspr(SPRN_MAS7, TLBCAM[idx].MAS7);
  107. asm volatile("isync;tlbwe;isync" : : : "memory");
  108. }
  109. /*
  110. * Set up one of the I/D BAT (block address translation) register pairs.
  111. * The parameters are not checked; in particular size must be a power
  112. * of 4 between 4k and 256M.
  113. */
  114. static void settlbcam(int index, unsigned long virt, phys_addr_t phys,
  115. unsigned long size, unsigned long flags, unsigned int pid)
  116. {
  117. unsigned int tsize, lz;
  118. asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (size));
  119. tsize = 21 - lz;
  120. #ifdef CONFIG_SMP
  121. if ((flags & _PAGE_NO_CACHE) == 0)
  122. flags |= _PAGE_COHERENT;
  123. #endif
  124. TLBCAM[index].MAS0 = MAS0_TLBSEL(1) | MAS0_ESEL(index) | MAS0_NV(index+1);
  125. TLBCAM[index].MAS1 = MAS1_VALID | MAS1_IPROT | MAS1_TSIZE(tsize) | MAS1_TID(pid);
  126. TLBCAM[index].MAS2 = virt & PAGE_MASK;
  127. TLBCAM[index].MAS2 |= (flags & _PAGE_WRITETHRU) ? MAS2_W : 0;
  128. TLBCAM[index].MAS2 |= (flags & _PAGE_NO_CACHE) ? MAS2_I : 0;
  129. TLBCAM[index].MAS2 |= (flags & _PAGE_COHERENT) ? MAS2_M : 0;
  130. TLBCAM[index].MAS2 |= (flags & _PAGE_GUARDED) ? MAS2_G : 0;
  131. TLBCAM[index].MAS2 |= (flags & _PAGE_ENDIAN) ? MAS2_E : 0;
  132. TLBCAM[index].MAS3 = (phys & MAS3_RPN) | MAS3_SX | MAS3_SR;
  133. TLBCAM[index].MAS3 |= ((flags & _PAGE_RW) ? MAS3_SW : 0);
  134. if (cur_cpu_spec->cpu_features & MMU_FTR_BIG_PHYS)
  135. TLBCAM[index].MAS7 = (u64)phys >> 32;
  136. #ifndef CONFIG_KGDB /* want user access for breakpoints */
  137. if (flags & _PAGE_USER) {
  138. TLBCAM[index].MAS3 |= MAS3_UX | MAS3_UR;
  139. TLBCAM[index].MAS3 |= ((flags & _PAGE_RW) ? MAS3_UW : 0);
  140. }
  141. #else
  142. TLBCAM[index].MAS3 |= MAS3_UX | MAS3_UR;
  143. TLBCAM[index].MAS3 |= ((flags & _PAGE_RW) ? MAS3_UW : 0);
  144. #endif
  145. tlbcam_addrs[index].start = virt;
  146. tlbcam_addrs[index].limit = virt + size - 1;
  147. tlbcam_addrs[index].phys = phys;
  148. loadcam_entry(index);
  149. }
  150. unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx)
  151. {
  152. int i;
  153. unsigned long virt = PAGE_OFFSET;
  154. phys_addr_t phys = memstart_addr;
  155. unsigned long amount_mapped = 0;
  156. unsigned long max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
  157. /* Convert (4^max) kB to (2^max) bytes */
  158. max_cam = max_cam * 2 + 10;
  159. /* Calculate CAM values */
  160. for (i = 0; ram && i < max_cam_idx; i++) {
  161. unsigned int camsize = __ilog2(ram) & ~1U;
  162. unsigned int align = __ffs(virt | phys) & ~1U;
  163. unsigned long cam_sz;
  164. if (camsize > align)
  165. camsize = align;
  166. if (camsize > max_cam)
  167. camsize = max_cam;
  168. cam_sz = 1UL << camsize;
  169. settlbcam(i, virt, phys, cam_sz, PAGE_KERNEL_X, 0);
  170. ram -= cam_sz;
  171. amount_mapped += cam_sz;
  172. virt += cam_sz;
  173. phys += cam_sz;
  174. }
  175. tlbcam_index = i;
  176. return amount_mapped;
  177. }
  178. unsigned long __init mmu_mapin_ram(unsigned long top)
  179. {
  180. return tlbcam_addrs[tlbcam_index - 1].limit - PAGE_OFFSET + 1;
  181. }
  182. /*
  183. * MMU_init_hw does the chip-specific initialization of the MMU hardware.
  184. */
  185. void __init MMU_init_hw(void)
  186. {
  187. flush_instruction_cache();
  188. }
  189. void __init adjust_total_lowmem(void)
  190. {
  191. unsigned long ram;
  192. int i;
  193. /* adjust lowmem size to __max_low_memory */
  194. ram = min((phys_addr_t)__max_low_memory, (phys_addr_t)total_lowmem);
  195. __max_low_memory = map_mem_in_cams(ram, CONFIG_LOWMEM_CAM_NUM);
  196. pr_info("Memory CAM mapping: ");
  197. for (i = 0; i < tlbcam_index - 1; i++)
  198. pr_cont("%lu/", tlbcam_sz(i) >> 20);
  199. pr_cont("%lu Mb, residual: %dMb\n", tlbcam_sz(tlbcam_index - 1) >> 20,
  200. (unsigned int)((total_lowmem - __max_low_memory) >> 20));
  201. __initial_memory_limit_addr = memstart_addr + __max_low_memory;
  202. }