asic-calliope.c 2.8 KB

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  1. /*
  2. * Locations of devices in the Calliope ASIC.
  3. *
  4. * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. *
  20. * Author: Ken Eppinett
  21. * David Schleef <ds@schleef.org>
  22. *
  23. * Description: Defines the platform resources for the SA settop.
  24. */
  25. #include <asm/mach-powertv/asic.h>
  26. const struct register_map calliope_register_map = {
  27. .eic_slow0_strt_add = 0x800000,
  28. .eic_cfg_bits = 0x800038,
  29. .eic_ready_status = 0x80004c,
  30. .chipver3 = 0xA00800,
  31. .chipver2 = 0xA00804,
  32. .chipver1 = 0xA00808,
  33. .chipver0 = 0xA0080c,
  34. /* The registers of IRBlaster */
  35. .uart1_intstat = 0xA01800,
  36. .uart1_inten = 0xA01804,
  37. .uart1_config1 = 0xA01808,
  38. .uart1_config2 = 0xA0180C,
  39. .uart1_divisorhi = 0xA01810,
  40. .uart1_divisorlo = 0xA01814,
  41. .uart1_data = 0xA01818,
  42. .uart1_status = 0xA0181C,
  43. .int_stat_3 = 0xA02800,
  44. .int_stat_2 = 0xA02804,
  45. .int_stat_1 = 0xA02808,
  46. .int_stat_0 = 0xA0280c,
  47. .int_config = 0xA02810,
  48. .int_int_scan = 0xA02818,
  49. .ien_int_3 = 0xA02830,
  50. .ien_int_2 = 0xA02834,
  51. .ien_int_1 = 0xA02838,
  52. .ien_int_0 = 0xA0283c,
  53. .int_level_3_3 = 0xA02880,
  54. .int_level_3_2 = 0xA02884,
  55. .int_level_3_1 = 0xA02888,
  56. .int_level_3_0 = 0xA0288c,
  57. .int_level_2_3 = 0xA02890,
  58. .int_level_2_2 = 0xA02894,
  59. .int_level_2_1 = 0xA02898,
  60. .int_level_2_0 = 0xA0289c,
  61. .int_level_1_3 = 0xA028a0,
  62. .int_level_1_2 = 0xA028a4,
  63. .int_level_1_1 = 0xA028a8,
  64. .int_level_1_0 = 0xA028ac,
  65. .int_level_0_3 = 0xA028b0,
  66. .int_level_0_2 = 0xA028b4,
  67. .int_level_0_1 = 0xA028b8,
  68. .int_level_0_0 = 0xA028bc,
  69. .int_docsis_en = 0xA028F4,
  70. .mips_pll_setup = 0x980000,
  71. .usb_fs = 0x980030, /* -default 72800028- */
  72. .test_bus = 0x9800CC,
  73. .crt_spare = 0x9800d4,
  74. .usb2_ohci_int_mask = 0x9A000c,
  75. .usb2_strap = 0x9A0014,
  76. .ehci_hcapbase = 0x9BFE00,
  77. .ohci_hc_revision = 0x9BFC00,
  78. .bcm1_bs_lmi_steer = 0x9E0004,
  79. .usb2_control = 0x9E0054,
  80. .usb2_stbus_obc = 0x9BFF00,
  81. .usb2_stbus_mess_size = 0x9BFF04,
  82. .usb2_stbus_chunk_size = 0x9BFF08,
  83. .pcie_regs = 0x000000, /* -doesn't exist- */
  84. .tim_ch = 0xA02C10,
  85. .tim_cl = 0xA02C14,
  86. .gpio_dout = 0xA02c20,
  87. .gpio_din = 0xA02c24,
  88. .gpio_dir = 0xA02c2C,
  89. .watchdog = 0xA02c30,
  90. .front_panel = 0x000000, /* -not used- */
  91. };