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blackfin
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mach-bf548
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include
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defBF549.h

defBF549.h 12 KB
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  1. /*
    2. 

  2.  * Copyright 2007-2008 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the ADI BSD license or the GPL-2 (or later)
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _DEF_BF549_H
    8. 

  8. #define _DEF_BF549_H
    9. 

  9. 

  10. /* Include all Core registers and bit definitions */
    11. 

  11. #include <asm/def_LPBlackfin.h>
    12. 

  12. 

  13. /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
    14. 

  14. 

  15. /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
    16. 

  16. #include "defBF54x_base.h"
    17. 

  17. 

  18. /* The BF549 is like the BF544, but has MXVR */
    19. 

  19. #include "defBF547.h"
    20. 

  20. 

  21. /* MXVR Registers */
    22. 

  22. 

  23. #define                      MXVR_CONFIG  0xffc02700   /* MXVR Configuration Register */
    24. 

  24. #define                     MXVR_STATE_0  0xffc02708   /* MXVR State Register 0 */
    25. 

  25. #define                     MXVR_STATE_1  0xffc0270c   /* MXVR State Register 1 */
    26. 

  26. #define                  MXVR_INT_STAT_0  0xffc02710   /* MXVR Interrupt Status Register 0 */
    27. 

  27. #define                  MXVR_INT_STAT_1  0xffc02714   /* MXVR Interrupt Status Register 1 */
    28. 

  28. #define                    MXVR_INT_EN_0  0xffc02718   /* MXVR Interrupt Enable Register 0 */
    29. 

  29. #define                    MXVR_INT_EN_1  0xffc0271c   /* MXVR Interrupt Enable Register 1 */
    30. 

  30. #define                    MXVR_POSITION  0xffc02720   /* MXVR Node Position Register */
    31. 

  31. #define                MXVR_MAX_POSITION  0xffc02724   /* MXVR Maximum Node Position Register */
    32. 

  32. #define                       MXVR_DELAY  0xffc02728   /* MXVR Node Frame Delay Register */
    33. 

  33. #define                   MXVR_MAX_DELAY  0xffc0272c   /* MXVR Maximum Node Frame Delay Register */
    34. 

  34. #define                       MXVR_LADDR  0xffc02730   /* MXVR Logical Address Register */
    35. 

  35. #define                       MXVR_GADDR  0xffc02734   /* MXVR Group Address Register */
    36. 

  36. #define                       MXVR_AADDR  0xffc02738   /* MXVR Alternate Address Register */
    37. 

  37. 

  38. /* MXVR Allocation Table Registers */
    39. 

  39. 

  40. #define                     MXVR_ALLOC_0  0xffc0273c   /* MXVR Allocation Table Register 0 */
    41. 

  41. #define                     MXVR_ALLOC_1  0xffc02740   /* MXVR Allocation Table Register 1 */
    42. 

  42. #define                     MXVR_ALLOC_2  0xffc02744   /* MXVR Allocation Table Register 2 */
    43. 

  43. #define                     MXVR_ALLOC_3  0xffc02748   /* MXVR Allocation Table Register 3 */
    44. 

  44. #define                     MXVR_ALLOC_4  0xffc0274c   /* MXVR Allocation Table Register 4 */
    45. 

  45. #define                     MXVR_ALLOC_5  0xffc02750   /* MXVR Allocation Table Register 5 */
    46. 

  46. #define                     MXVR_ALLOC_6  0xffc02754   /* MXVR Allocation Table Register 6 */
    47. 

  47. #define                     MXVR_ALLOC_7  0xffc02758   /* MXVR Allocation Table Register 7 */
    48. 

  48. #define                     MXVR_ALLOC_8  0xffc0275c   /* MXVR Allocation Table Register 8 */
    49. 

  49. #define                     MXVR_ALLOC_9  0xffc02760   /* MXVR Allocation Table Register 9 */
    50. 

  50. #define                    MXVR_ALLOC_10  0xffc02764   /* MXVR Allocation Table Register 10 */
    51. 

  51. #define                    MXVR_ALLOC_11  0xffc02768   /* MXVR Allocation Table Register 11 */
    52. 

  52. #define                    MXVR_ALLOC_12  0xffc0276c   /* MXVR Allocation Table Register 12 */
    53. 

  53. #define                    MXVR_ALLOC_13  0xffc02770   /* MXVR Allocation Table Register 13 */
    54. 

  54. #define                    MXVR_ALLOC_14  0xffc02774   /* MXVR Allocation Table Register 14 */
    55. 

  55. 

  56. /* MXVR Channel Assign Registers */
    57. 

  57. 

  58. #define                MXVR_SYNC_LCHAN_0  0xffc02778   /* MXVR Sync Data Logical Channel Assign Register 0 */
    59. 

  59. #define                MXVR_SYNC_LCHAN_1  0xffc0277c   /* MXVR Sync Data Logical Channel Assign Register 1 */
    60. 

  60. #define                MXVR_SYNC_LCHAN_2  0xffc02780   /* MXVR Sync Data Logical Channel Assign Register 2 */
    61. 

  61. #define                MXVR_SYNC_LCHAN_3  0xffc02784   /* MXVR Sync Data Logical Channel Assign Register 3 */
    62. 

  62. #define                MXVR_SYNC_LCHAN_4  0xffc02788   /* MXVR Sync Data Logical Channel Assign Register 4 */
    63. 

  63. #define                MXVR_SYNC_LCHAN_5  0xffc0278c   /* MXVR Sync Data Logical Channel Assign Register 5 */
    64. 

  64. #define                MXVR_SYNC_LCHAN_6  0xffc02790   /* MXVR Sync Data Logical Channel Assign Register 6 */
    65. 

  65. #define                MXVR_SYNC_LCHAN_7  0xffc02794   /* MXVR Sync Data Logical Channel Assign Register 7 */
    66. 

  66. 

  67. /* MXVR DMA0 Registers */
    68. 

  68. 

  69. #define                 MXVR_DMA0_CONFIG  0xffc02798   /* MXVR Sync Data DMA0 Config Register */
    70. 

  70. #define             MXVR_DMA0_START_ADDR  0xffc0279c   /* MXVR Sync Data DMA0 Start Address */
    71. 

  71. #define                  MXVR_DMA0_COUNT  0xffc027a0   /* MXVR Sync Data DMA0 Loop Count Register */
    72. 

  72. #define              MXVR_DMA0_CURR_ADDR  0xffc027a4   /* MXVR Sync Data DMA0 Current Address */
    73. 

  73. #define             MXVR_DMA0_CURR_COUNT  0xffc027a8   /* MXVR Sync Data DMA0 Current Loop Count */
    74. 

  74. 

  75. /* MXVR DMA1 Registers */
    76. 

  76. 

  77. #define                 MXVR_DMA1_CONFIG  0xffc027ac   /* MXVR Sync Data DMA1 Config Register */
    78. 

  78. #define             MXVR_DMA1_START_ADDR  0xffc027b0   /* MXVR Sync Data DMA1 Start Address */
    79. 

  79. #define                  MXVR_DMA1_COUNT  0xffc027b4   /* MXVR Sync Data DMA1 Loop Count Register */
    80. 

  80. #define              MXVR_DMA1_CURR_ADDR  0xffc027b8   /* MXVR Sync Data DMA1 Current Address */
    81. 

  81. #define             MXVR_DMA1_CURR_COUNT  0xffc027bc   /* MXVR Sync Data DMA1 Current Loop Count */
    82. 

  82. 

  83. /* MXVR DMA2 Registers */
    84. 

  84. 

  85. #define                 MXVR_DMA2_CONFIG  0xffc027c0   /* MXVR Sync Data DMA2 Config Register */
    86. 

  86. #define             MXVR_DMA2_START_ADDR  0xffc027c4   /* MXVR Sync Data DMA2 Start Address */
    87. 

  87. #define                  MXVR_DMA2_COUNT  0xffc027c8   /* MXVR Sync Data DMA2 Loop Count Register */
    88. 

  88. #define              MXVR_DMA2_CURR_ADDR  0xffc027cc   /* MXVR Sync Data DMA2 Current Address */
    89. 

  89. #define             MXVR_DMA2_CURR_COUNT  0xffc027d0   /* MXVR Sync Data DMA2 Current Loop Count */
    90. 

  90. 

  91. /* MXVR DMA3 Registers */
    92. 

  92. 

  93. #define                 MXVR_DMA3_CONFIG  0xffc027d4   /* MXVR Sync Data DMA3 Config Register */
    94. 

  94. #define             MXVR_DMA3_START_ADDR  0xffc027d8   /* MXVR Sync Data DMA3 Start Address */
    95. 

  95. #define                  MXVR_DMA3_COUNT  0xffc027dc   /* MXVR Sync Data DMA3 Loop Count Register */
    96. 

  96. #define              MXVR_DMA3_CURR_ADDR  0xffc027e0   /* MXVR Sync Data DMA3 Current Address */
    97. 

  97. #define             MXVR_DMA3_CURR_COUNT  0xffc027e4   /* MXVR Sync Data DMA3 Current Loop Count */
    98. 

  98. 

  99. /* MXVR DMA4 Registers */
    100. 

  100. 

  101. #define                 MXVR_DMA4_CONFIG  0xffc027e8   /* MXVR Sync Data DMA4 Config Register */
    102. 

  102. #define             MXVR_DMA4_START_ADDR  0xffc027ec   /* MXVR Sync Data DMA4 Start Address */
    103. 

  103. #define                  MXVR_DMA4_COUNT  0xffc027f0   /* MXVR Sync Data DMA4 Loop Count Register */
    104. 

  104. #define              MXVR_DMA4_CURR_ADDR  0xffc027f4   /* MXVR Sync Data DMA4 Current Address */
    105. 

  105. #define             MXVR_DMA4_CURR_COUNT  0xffc027f8   /* MXVR Sync Data DMA4 Current Loop Count */
    106. 

  106. 

  107. /* MXVR DMA5 Registers */
    108. 

  108. 

  109. #define                 MXVR_DMA5_CONFIG  0xffc027fc   /* MXVR Sync Data DMA5 Config Register */
    110. 

  110. #define             MXVR_DMA5_START_ADDR  0xffc02800   /* MXVR Sync Data DMA5 Start Address */
    111. 

  111. #define                  MXVR_DMA5_COUNT  0xffc02804   /* MXVR Sync Data DMA5 Loop Count Register */
    112. 

  112. #define              MXVR_DMA5_CURR_ADDR  0xffc02808   /* MXVR Sync Data DMA5 Current Address */
    113. 

  113. #define             MXVR_DMA5_CURR_COUNT  0xffc0280c   /* MXVR Sync Data DMA5 Current Loop Count */
    114. 

  114. 

  115. /* MXVR DMA6 Registers */
    116. 

  116. 

  117. #define                 MXVR_DMA6_CONFIG  0xffc02810   /* MXVR Sync Data DMA6 Config Register */
    118. 

  118. #define             MXVR_DMA6_START_ADDR  0xffc02814   /* MXVR Sync Data DMA6 Start Address */
    119. 

  119. #define                  MXVR_DMA6_COUNT  0xffc02818   /* MXVR Sync Data DMA6 Loop Count Register */
    120. 

  120. #define              MXVR_DMA6_CURR_ADDR  0xffc0281c   /* MXVR Sync Data DMA6 Current Address */
    121. 

  121. #define             MXVR_DMA6_CURR_COUNT  0xffc02820   /* MXVR Sync Data DMA6 Current Loop Count */
    122. 

  122. 

  123. /* MXVR DMA7 Registers */
    124. 

  124. 

  125. #define                 MXVR_DMA7_CONFIG  0xffc02824   /* MXVR Sync Data DMA7 Config Register */
    126. 

  126. #define             MXVR_DMA7_START_ADDR  0xffc02828   /* MXVR Sync Data DMA7 Start Address */
    127. 

  127. #define                  MXVR_DMA7_COUNT  0xffc0282c   /* MXVR Sync Data DMA7 Loop Count Register */
    128. 

  128. #define              MXVR_DMA7_CURR_ADDR  0xffc02830   /* MXVR Sync Data DMA7 Current Address */
    129. 

  129. #define             MXVR_DMA7_CURR_COUNT  0xffc02834   /* MXVR Sync Data DMA7 Current Loop Count */
    130. 

  130. 

  131. /* MXVR Asynch Packet Registers */
    132. 

  132. 

  133. #define                      MXVR_AP_CTL  0xffc02838   /* MXVR Async Packet Control Register */
    134. 

  134. #define             MXVR_APRB_START_ADDR  0xffc0283c   /* MXVR Async Packet RX Buffer Start Addr Register */
    135. 

  135. #define              MXVR_APRB_CURR_ADDR  0xffc02840   /* MXVR Async Packet RX Buffer Current Addr Register */
    136. 

  136. #define             MXVR_APTB_START_ADDR  0xffc02844   /* MXVR Async Packet TX Buffer Start Addr Register */
    137. 

  137. #define              MXVR_APTB_CURR_ADDR  0xffc02848   /* MXVR Async Packet TX Buffer Current Addr Register */
    138. 

  138. 

  139. /* MXVR Control Message Registers */
    140. 

  140. 

  141. #define                      MXVR_CM_CTL  0xffc0284c   /* MXVR Control Message Control Register */
    142. 

  142. #define             MXVR_CMRB_START_ADDR  0xffc02850   /* MXVR Control Message RX Buffer Start Addr Register */
    143. 

  143. #define              MXVR_CMRB_CURR_ADDR  0xffc02854   /* MXVR Control Message RX Buffer Current Address */
    144. 

  144. #define             MXVR_CMTB_START_ADDR  0xffc02858   /* MXVR Control Message TX Buffer Start Addr Register */
    145. 

  145. #define              MXVR_CMTB_CURR_ADDR  0xffc0285c   /* MXVR Control Message TX Buffer Current Address */
    146. 

  146. 

  147. /* MXVR Remote Read Registers */
    148. 

  148. 

  149. #define             MXVR_RRDB_START_ADDR  0xffc02860   /* MXVR Remote Read Buffer Start Addr Register */
    150. 

  150. #define              MXVR_RRDB_CURR_ADDR  0xffc02864   /* MXVR Remote Read Buffer Current Addr Register */
    151. 

  151. 

  152. /* MXVR Pattern Data Registers */
    153. 

  153. 

  154. #define                  MXVR_PAT_DATA_0  0xffc02868   /* MXVR Pattern Data Register 0 */
    155. 

  155. #define                    MXVR_PAT_EN_0  0xffc0286c   /* MXVR Pattern Enable Register 0 */
    156. 

  156. #define                  MXVR_PAT_DATA_1  0xffc02870   /* MXVR Pattern Data Register 1 */
    157. 

  157. #define                    MXVR_PAT_EN_1  0xffc02874   /* MXVR Pattern Enable Register 1 */
    158. 

  158. 

  159. /* MXVR Frame Counter Registers */
    160. 

  160. 

  161. #define                 MXVR_FRAME_CNT_0  0xffc02878   /* MXVR Frame Counter 0 */
    162. 

  162. #define                 MXVR_FRAME_CNT_1  0xffc0287c   /* MXVR Frame Counter 1 */
    163. 

  163. 

  164. /* MXVR Routing Table Registers */
    165. 

  165. 

  166. #define                   MXVR_ROUTING_0  0xffc02880   /* MXVR Routing Table Register 0 */
    167. 

  167. #define                   MXVR_ROUTING_1  0xffc02884   /* MXVR Routing Table Register 1 */
    168. 

  168. #define                   MXVR_ROUTING_2  0xffc02888   /* MXVR Routing Table Register 2 */
    169. 

  169. #define                   MXVR_ROUTING_3  0xffc0288c   /* MXVR Routing Table Register 3 */
    170. 

  170. #define                   MXVR_ROUTING_4  0xffc02890   /* MXVR Routing Table Register 4 */
    171. 

  171. #define                   MXVR_ROUTING_5  0xffc02894   /* MXVR Routing Table Register 5 */
    172. 

  172. #define                   MXVR_ROUTING_6  0xffc02898   /* MXVR Routing Table Register 6 */
    173. 

  173. #define                   MXVR_ROUTING_7  0xffc0289c   /* MXVR Routing Table Register 7 */
    174. 

  174. #define                   MXVR_ROUTING_8  0xffc028a0   /* MXVR Routing Table Register 8 */
    175. 

  175. #define                   MXVR_ROUTING_9  0xffc028a4   /* MXVR Routing Table Register 9 */
    176. 

  176. #define                  MXVR_ROUTING_10  0xffc028a8   /* MXVR Routing Table Register 10 */
    177. 

  177. #define                  MXVR_ROUTING_11  0xffc028ac   /* MXVR Routing Table Register 11 */
    178. 

  178. #define                  MXVR_ROUTING_12  0xffc028b0   /* MXVR Routing Table Register 12 */
    179. 

  179. #define                  MXVR_ROUTING_13  0xffc028b4   /* MXVR Routing Table Register 13 */
    180. 

  180. #define                  MXVR_ROUTING_14  0xffc028b8   /* MXVR Routing Table Register 14 */
    181. 

  181. 

  182. /* MXVR Counter-Clock-Control Registers */
    183. 

  183. 

  184. #define                   MXVR_BLOCK_CNT  0xffc028c0   /* MXVR Block Counter */
    185. 

  185. #define                     MXVR_CLK_CTL  0xffc028d0   /* MXVR Clock Control Register */
    186. 

  186. #define                  MXVR_CDRPLL_CTL  0xffc028d4   /* MXVR Clock/Data Recovery PLL Control Register */
    187. 

  187. #define                   MXVR_FMPLL_CTL  0xffc028d8   /* MXVR Frequency Multiply PLL Control Register */
    188. 

  188. #define                     MXVR_PIN_CTL  0xffc028dc   /* MXVR Pin Control Register */
    189. 

  189. #define                    MXVR_SCLK_CNT  0xffc028e0   /* MXVR System Clock Counter Register */
    190. 

  190. 

  191. #endif /* _DEF_BF549_H */
    192.