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linux-vybrid_pu...
/
arch
/
arm
/
plat-s5pc1xx
/
include
/
plat
/
regs-power.h

regs-power.h 3.5 KB
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  1. /* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
    2. 

  2.  *
    3. 

  3.  * Copyright 2009 Samsung Electronics Co.
    4. 

  4.  *	Jongse Won <jongse.won@samsung.com>
    5. 

  5.  *
    6. 

  6.  * S5PC1XX clock register definitions
    7. 

  7.  *
    8. 

  8.  * This program is free software; you can redistribute it and/or modify
    9. 

  9.  * it under the terms of the GNU General Public License version 2 as
    10. 

  10.  * published by the Free Software Foundation.
    11. 

  11. */
    12. 

  12. 

  13. #ifndef __ASM_ARM_REGS_PWR
    14. 

  14. #define __ASM_ARM_REGS_PWR __FILE__
    15. 

  15. 

  16. #define S5PC1XX_PWRREG(x)			(S5PC1XX_VA_PWR + (x))
    17. 

  17. 

  18. /* s5pc100 (0xE0108000) register for power management */
    19. 

  19. #define S5PC100_PWR_CFG				S5PC1XX_PWRREG(0x0)
    20. 

  20. #define S5PC100_EINT_WAKEUP_MASK		S5PC1XX_PWRREG(0x4)
    21. 

  21. #define S5PC100_NORMAL_CFG			S5PC1XX_PWRREG(0x10)
    22. 

  22. #define S5PC100_STOP_CFG			S5PC1XX_PWRREG(0x14)
    23. 

  23. #define S5PC100_SLEEP_CFG			S5PC1XX_PWRREG(0x18)
    24. 

  24. #define S5PC100_STOP_MEM_CFG			S5PC1XX_PWRREG(0x1C)
    25. 

  25. #define S5PC100_OSC_FREQ			S5PC1XX_PWRREG(0x100)
    26. 

  26. #define S5PC100_OSC_STABLE			S5PC1XX_PWRREG(0x104)
    27. 

  27. #define S5PC100_PWR_STABLE			S5PC1XX_PWRREG(0x108)
    28. 

  28. #define S5PC100_MTC_STABLE			S5PC1XX_PWRREG(0x110)
    29. 

  29. #define S5PC100_CLAMP_STABLE			S5PC1XX_PWRREG(0x114)
    30. 

  30. #define S5PC100_OTHERS				S5PC1XX_PWRREG(0x200)
    31. 

  31. #define S5PC100_RST_STAT			S5PC1XX_PWRREG(0x300)
    32. 

  32. #define S5PC100_WAKEUP_STAT			S5PC1XX_PWRREG(0x304)
    33. 

  33. #define S5PC100_BLK_PWR_STAT			S5PC1XX_PWRREG(0x308)
    34. 

  34. #define S5PC100_INFORM0				S5PC1XX_PWRREG(0x400)
    35. 

  35. #define S5PC100_INFORM1				S5PC1XX_PWRREG(0x404)
    36. 

  36. #define S5PC100_INFORM2				S5PC1XX_PWRREG(0x408)
    37. 

  37. #define S5PC100_INFORM3				S5PC1XX_PWRREG(0x40C)
    38. 

  38. #define S5PC100_INFORM4				S5PC1XX_PWRREG(0x410)
    39. 

  39. #define S5PC100_INFORM5				S5PC1XX_PWRREG(0x414)
    40. 

  40. #define S5PC100_INFORM6				S5PC1XX_PWRREG(0x418)
    41. 

  41. #define S5PC100_INFORM7				S5PC1XX_PWRREG(0x41C)
    42. 

  42. #define S5PC100_DCGIDX_MAP0			S5PC1XX_PWRREG(0x500)
    43. 

  43. #define S5PC100_DCGIDX_MAP1			S5PC1XX_PWRREG(0x504)
    44. 

  44. #define S5PC100_DCGIDX_MAP2			S5PC1XX_PWRREG(0x508)
    45. 

  45. #define S5PC100_DCGPERF_MAP0			S5PC1XX_PWRREG(0x50C)
    46. 

  46. #define S5PC100_DCGPERF_MAP1			S5PC1XX_PWRREG(0x510)
    47. 

  47. #define S5PC100_DVCIDX_MAP			S5PC1XX_PWRREG(0x514)
    48. 

  48. #define S5PC100_FREQ_CPU			S5PC1XX_PWRREG(0x518)
    49. 

  49. #define S5PC100_FREQ_DPM			S5PC1XX_PWRREG(0x51C)
    50. 

  50. #define S5PC100_DVSEMCLK_EN			S5PC1XX_PWRREG(0x520)
    51. 

  51. #define S5PC100_APLL_CON_L8			S5PC1XX_PWRREG(0x600)
    52. 

  52. #define S5PC100_APLL_CON_L7			S5PC1XX_PWRREG(0x604)
    53. 

  53. #define S5PC100_APLL_CON_L6			S5PC1XX_PWRREG(0x608)
    54. 

  54. #define S5PC100_APLL_CON_L5			S5PC1XX_PWRREG(0x60C)
    55. 

  55. #define S5PC100_APLL_CON_L4			S5PC1XX_PWRREG(0x610)
    56. 

  56. #define S5PC100_APLL_CON_L3			S5PC1XX_PWRREG(0x614)
    57. 

  57. #define S5PC100_APLL_CON_L2			S5PC1XX_PWRREG(0x618)
    58. 

  58. #define S5PC100_APLL_CON_L1			S5PC1XX_PWRREG(0x61C)
    59. 

  59. #define S5PC100_IEM_CONTROL			S5PC1XX_PWRREG(0x620)
    60. 

  60. #define S5PC100_CLKDIV_IEM_L8			S5PC1XX_PWRREG(0x700)
    61. 

  61. #define S5PC100_CLKDIV_IEM_L7			S5PC1XX_PWRREG(0x704)
    62. 

  62. #define S5PC100_CLKDIV_IEM_L6			S5PC1XX_PWRREG(0x708)
    63. 

  63. #define S5PC100_CLKDIV_IEM_L5			S5PC1XX_PWRREG(0x70C)
    64. 

  64. #define S5PC100_CLKDIV_IEM_L4			S5PC1XX_PWRREG(0x710)
    65. 

  65. #define S5PC100_CLKDIV_IEM_L3			S5PC1XX_PWRREG(0x714)
    66. 

  66. #define S5PC100_CLKDIV_IEM_L2			S5PC1XX_PWRREG(0x718)
    67. 

  67. #define S5PC100_CLKDIV_IEM_L1			S5PC1XX_PWRREG(0x71C)
    68. 

  68. #define S5PC100_IEM_HPMCLK_DIV			S5PC1XX_PWRREG(0x724)
    69. 

  69. 

  70. /* PWR_CFG */
    71. 

  71. #define S5PC100_PWRCFG_CFG_DEEP_IDLE		(1 << 31)
    72. 

  72. #define S5PC100_PWRCFG_CFG_WFI_MASK		(3 << 5)
    73. 

  73. #define S5PC100_PWRCFG_CFG_WFI_IDLE		(0 << 5)
    74. 

  74. #define S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE	(1 << 5)
    75. 

  75. #define S5PC100_PWRCFG_CFG_WFI_STOP		(2 << 5)
    76. 

  76. #define S5PC100_PWRCFG_CFG_WFI_SLEEP		(3 << 5)
    77. 

  77. 

  78. /* SLEEP_CFG */
    79. 

  79. #define S5PC100_SLEEP_OSC_EN_SLEEP		(1 << 0)
    80. 

  80. 

  81. /* OTHERS */
    82. 

  82. #define S5PC100_PMU_INT_DISABLE			(1 << 24)
    83. 

  83. 

  84. #endif /* __ASM_ARM_REGS_PWR */
    85.