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linux-vybrid_pu...
/
arch
/
arm
/
plat-s5pc1xx
/
include
/
plat
/
regs-gpio.h

regs-gpio.h 2.8 KB
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  1. /* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
    2. 

  2.  *
    3. 

  3.  * Copyright 2009 Samsung Electronics Co.
    4. 

  4.  *      Byungho Min <bhmin@samsung.com>
    5. 

  5.  *
    6. 

  6.  * S5PC1XX - GPIO register definitions
    7. 

  7.  */
    8. 

  8. 

  9. #ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H
    10. 

  10. #define __ASM_PLAT_S5PC1XX_REGS_GPIO_H __FILE__
    11. 

  11. 

  12. #include <mach/map.h>
    13. 

  13. 

  14. /* S5PC100 */
    15. 

  15. #define S5PC100_GPIO_BASE	S5PC1XX_VA_GPIO
    16. 

  16. #define S5PC100_GPA0_BASE	(S5PC100_GPIO_BASE + 0x0000)
    17. 

  17. #define S5PC100_GPA1_BASE	(S5PC100_GPIO_BASE + 0x0020)
    18. 

  18. #define S5PC100_GPB_BASE	(S5PC100_GPIO_BASE + 0x0040)
    19. 

  19. #define S5PC100_GPC_BASE	(S5PC100_GPIO_BASE + 0x0060)
    20. 

  20. #define S5PC100_GPD_BASE	(S5PC100_GPIO_BASE + 0x0080)
    21. 

  21. #define S5PC100_GPE0_BASE	(S5PC100_GPIO_BASE + 0x00A0)
    22. 

  22. #define S5PC100_GPE1_BASE	(S5PC100_GPIO_BASE + 0x00C0)
    23. 

  23. #define S5PC100_GPF0_BASE	(S5PC100_GPIO_BASE + 0x00E0)
    24. 

  24. #define S5PC100_GPF1_BASE	(S5PC100_GPIO_BASE + 0x0100)
    25. 

  25. #define S5PC100_GPF2_BASE	(S5PC100_GPIO_BASE + 0x0120)
    26. 

  26. #define S5PC100_GPF3_BASE	(S5PC100_GPIO_BASE + 0x0140)
    27. 

  27. #define S5PC100_GPG0_BASE	(S5PC100_GPIO_BASE + 0x0160)
    28. 

  28. #define S5PC100_GPG1_BASE	(S5PC100_GPIO_BASE + 0x0180)
    29. 

  29. #define S5PC100_GPG2_BASE	(S5PC100_GPIO_BASE + 0x01A0)
    30. 

  30. #define S5PC100_GPG3_BASE	(S5PC100_GPIO_BASE + 0x01C0)
    31. 

  31. #define S5PC100_GPH0_BASE	(S5PC100_GPIO_BASE + 0x0C00)
    32. 

  32. #define S5PC100_GPH1_BASE	(S5PC100_GPIO_BASE + 0x0C20)
    33. 

  33. #define S5PC100_GPH2_BASE	(S5PC100_GPIO_BASE + 0x0C40)
    34. 

  34. #define S5PC100_GPH3_BASE	(S5PC100_GPIO_BASE + 0x0C60)
    35. 

  35. #define S5PC100_GPI_BASE	(S5PC100_GPIO_BASE + 0x01E0)
    36. 

  36. #define S5PC100_GPJ0_BASE	(S5PC100_GPIO_BASE + 0x0200)
    37. 

  37. #define S5PC100_GPJ1_BASE	(S5PC100_GPIO_BASE + 0x0220)
    38. 

  38. #define S5PC100_GPJ2_BASE	(S5PC100_GPIO_BASE + 0x0240)
    39. 

  39. #define S5PC100_GPJ3_BASE	(S5PC100_GPIO_BASE + 0x0260)
    40. 

  40. #define S5PC100_GPJ4_BASE	(S5PC100_GPIO_BASE + 0x0280)
    41. 

  41. #define S5PC100_GPK0_BASE	(S5PC100_GPIO_BASE + 0x02A0)
    42. 

  42. #define S5PC100_GPK1_BASE	(S5PC100_GPIO_BASE + 0x02C0)
    43. 

  43. #define S5PC100_GPK2_BASE	(S5PC100_GPIO_BASE + 0x02E0)
    44. 

  44. #define S5PC100_GPK3_BASE	(S5PC100_GPIO_BASE + 0x0300)
    45. 

  45. #define S5PC100_GPL0_BASE	(S5PC100_GPIO_BASE + 0x0320)
    46. 

  46. #define S5PC100_GPL1_BASE	(S5PC100_GPIO_BASE + 0x0340)
    47. 

  47. #define S5PC100_GPL2_BASE	(S5PC100_GPIO_BASE + 0x0360)
    48. 

  48. #define S5PC100_GPL3_BASE	(S5PC100_GPIO_BASE + 0x0380)
    49. 

  49. #define S5PC100_GPL4_BASE	(S5PC100_GPIO_BASE + 0x03A0)
    50. 

  50. #define S5PC100_EINT_BASE	(S5PC100_GPIO_BASE + 0x0E00)
    51. 

  51. 

  52. #define S5PC100_UHOST		(S5PC100_GPIO_BASE + 0x0B68)
    53. 

  53. #define S5PC100_PDNEN		(S5PC100_GPIO_BASE + 0x0F80)
    54. 

  54. 

  55. /* PDNEN */
    56. 

  56. #define S5PC100_PDNEN_CFG_PDNEN	(1 << 1)
    57. 

  57. #define S5PC100_PDNEN_CFG_AUTO	(0 << 1)
    58. 

  58. #define S5PC100_PDNEN_POWERDOWN	(1 << 0)
    59. 

  59. #define S5PC100_PDNEN_NORMAL	(0 << 0)
    60. 

  60. 

  61. /* Common part */
    62. 

  62. /* External interrupt base is same at both s5pc100 and s5pc110 */
    63. 

  63. #define S5PC1XX_EINT_BASE	(S5PC100_EINT_BASE)
    64. 

  64. 

  65. #define S5PC100_GPx_INPUT(__gpio)	(0x0 << ((__gpio) * 4))
    66. 

  66. #define S5PC100_GPx_OUTPUT(__gpio)	(0x1 << ((__gpio) * 4))
    67. 

  67. #define S5PC100_GPx_CONMASK(__gpio)	(0xf << ((__gpio) * 4))
    68. 

  68. 

  69. #endif /* __ASM_PLAT_S5PC1XX_REGS_GPIO_H */
    70. 

  70.