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linux-vybrid_pu...
/
arch
/
arm
/
plat-mxc
/
include
/
mach
/
board-mx31ads.h

board-mx31ads.h 3.6 KB
文件歷史 原始文件

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  1. /*
    2. 

  2.  * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
    3. 

  3.  */
    4. 

  4. 

  5. /*
    6. 

  6.  * This program is free software; you can redistribute it and/or modify
    7. 

  7.  * it under the terms of the GNU General Public License version 2 as
    8. 

  8.  * published by the Free Software Foundation.
    9. 

  9.  */
    10. 

  10. 

  11. #ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
    12. 

  12. #define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
    13. 

  13. 

  14. #include <mach/hardware.h>
    15. 

  15. 

  16. /* Base address of PBC controller */
    17. 

  17. #define PBC_BASE_ADDRESS        IO_ADDRESS(CS4_BASE_ADDR)
    18. 

  18. /* Offsets for the PBC Controller register */
    19. 

  19. 

  20. /* PBC Board status register offset */
    21. 

  21. #define PBC_BSTAT               0x000002
    22. 

  22. 

  23. /* PBC Board control register 1 set address */
    24. 

  24. #define PBC_BCTRL1_SET          0x000004
    25. 

  25. 

  26. /* PBC Board control register 1 clear address */
    27. 

  27. #define PBC_BCTRL1_CLEAR        0x000006
    28. 

  28. 

  29. /* PBC Board control register 2 set address */
    30. 

  30. #define PBC_BCTRL2_SET          0x000008
    31. 

  31. 

  32. /* PBC Board control register 2 clear address */
    33. 

  33. #define PBC_BCTRL2_CLEAR        0x00000A
    34. 

  34. 

  35. /* PBC Board control register 3 set address */
    36. 

  36. #define PBC_BCTRL3_SET          0x00000C
    37. 

  37. 

  38. /* PBC Board control register 3 clear address */
    39. 

  39. #define PBC_BCTRL3_CLEAR        0x00000E
    40. 

  40. 

  41. /* PBC Board control register 4 set address */
    42. 

  42. #define PBC_BCTRL4_SET          0x000010
    43. 

  43. 

  44. /* PBC Board control register 4 clear address */
    45. 

  45. #define PBC_BCTRL4_CLEAR        0x000012
    46. 

  46. 

  47. /* PBC Board status register 1 */
    48. 

  48. #define PBC_BSTAT1              0x000014
    49. 

  49. 

  50. /* PBC Board interrupt status register */
    51. 

  51. #define PBC_INTSTATUS           0x000016
    52. 

  52. 

  53. /* PBC Board interrupt current status register */
    54. 

  54. #define PBC_INTCURR_STATUS      0x000018
    55. 

  55. 

  56. /* PBC Interrupt mask register set address */
    57. 

  57. #define PBC_INTMASK_SET         0x00001A
    58. 

  58. 

  59. /* PBC Interrupt mask register clear address */
    60. 

  60. #define PBC_INTMASK_CLEAR       0x00001C
    61. 

  61. 

  62. /* External UART A */
    63. 

  63. #define PBC_SC16C652_UARTA      0x010000
    64. 

  64. 

  65. /* External UART B */
    66. 

  66. #define PBC_SC16C652_UARTB      0x010010
    67. 

  67. 

  68. /* Ethernet Controller IO base address */
    69. 

  69. #define PBC_CS8900A_IOBASE      0x020000
    70. 

  70. 

  71. /* Ethernet Controller Memory base address */
    72. 

  72. #define PBC_CS8900A_MEMBASE     0x021000
    73. 

  73. 

  74. /* Ethernet Controller DMA base address */
    75. 

  75. #define PBC_CS8900A_DMABASE     0x022000
    76. 

  76. 

  77. /* External chip select 0 */
    78. 

  78. #define PBC_XCS0                0x040000
    79. 

  79. 

  80. /* LCD Display enable */
    81. 

  81. #define PBC_LCD_EN_B            0x060000
    82. 

  82. 

  83. /* Code test debug enable */
    84. 

  84. #define PBC_CODE_B              0x070000
    85. 

  85. 

  86. /* PSRAM memory select */
    87. 

  87. #define PBC_PSRAM_B             0x5000000
    88. 

  88. 

  89. #define PBC_INTSTATUS_REG	(PBC_INTSTATUS + PBC_BASE_ADDRESS)
    90. 

  90. #define PBC_INTCURR_STATUS_REG	(PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
    91. 

  91. #define PBC_INTMASK_SET_REG	(PBC_INTMASK_SET + PBC_BASE_ADDRESS)
    92. 

  92. #define PBC_INTMASK_CLEAR_REG	(PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
    93. 

  93. #define EXPIO_PARENT_INT	IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
    94. 

  94. 

  95. #define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
    96. 

  96. #define MXC_IRQ_TO_EXPIO(irq)	((irq) - MXC_EXP_IO_BASE)
    97. 

  97. 

  98. #define EXPIO_INT_LOW_BAT	(MXC_EXP_IO_BASE + 0)
    99. 

  99. #define EXPIO_INT_PB_IRQ	(MXC_EXP_IO_BASE + 1)
    100. 

  100. #define EXPIO_INT_OTG_FS_OVR	(MXC_EXP_IO_BASE + 2)
    101. 

  101. #define EXPIO_INT_FSH_OVR	(MXC_EXP_IO_BASE + 3)
    102. 

  102. #define EXPIO_INT_RES4		(MXC_EXP_IO_BASE + 4)
    103. 

  103. #define EXPIO_INT_RES5		(MXC_EXP_IO_BASE + 5)
    104. 

  104. #define EXPIO_INT_RES6		(MXC_EXP_IO_BASE + 6)
    105. 

  105. #define EXPIO_INT_RES7		(MXC_EXP_IO_BASE + 7)
    106. 

  106. #define EXPIO_INT_ENET_INT	(MXC_EXP_IO_BASE + 8)
    107. 

  107. #define EXPIO_INT_OTG_FS_INT	(MXC_EXP_IO_BASE + 9)
    108. 

  108. #define EXPIO_INT_XUART_INTA	(MXC_EXP_IO_BASE + 10)
    109. 

  109. #define EXPIO_INT_XUART_INTB	(MXC_EXP_IO_BASE + 11)
    110. 

  110. #define EXPIO_INT_SYNTH_IRQ	(MXC_EXP_IO_BASE + 12)
    111. 

  111. #define EXPIO_INT_CE_INT1	(MXC_EXP_IO_BASE + 13)
    112. 

  112. #define EXPIO_INT_CE_INT2	(MXC_EXP_IO_BASE + 14)
    113. 

  113. #define EXPIO_INT_RES15		(MXC_EXP_IO_BASE + 15)
    114. 

  114. 

  115. #define MXC_MAX_EXP_IO_LINES	16
    116. 

  116. 

  117. #endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
    118.