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arm
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mach-mmp
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mach
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regs-apbc.h

regs-apbc.h 2.7 KB
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  1. /*
    2. 

  2.  * linux/arch/arm/mach-mmp/include/mach/regs-apbc.h
    3. 

  3.  *
    4. 

  4.  *   Application Peripheral Bus Clock Unit
    5. 

  5.  *
    6. 

  6.  * This program is free software; you can redistribute it and/or modify
    7. 

  7.  * it under the terms of the GNU General Public License version 2 as
    8. 

  8.  * published by the Free Software Foundation.
    9. 

  9.  */
    10. 

  10. 

  11. #ifndef __ASM_MACH_REGS_APBC_H
    12. 

  12. #define __ASM_MACH_REGS_APBC_H
    13. 

  13. 

  14. #include <mach/addr-map.h>
    15. 

  15. 

  16. #define APBC_VIRT_BASE	(APB_VIRT_BASE + 0x015000)
    17. 

  17. #define APBC_REG(x)	(APBC_VIRT_BASE + (x))
    18. 

  18. 

  19. /*
    20. 

  20.  * APB clock register offsets for PXA168
    21. 

  21.  */
    22. 

  22. #define APBC_PXA168_UART1	APBC_REG(0x000)
    23. 

  23. #define APBC_PXA168_UART2	APBC_REG(0x004)
    24. 

  24. #define APBC_PXA168_GPIO	APBC_REG(0x008)
    25. 

  25. #define APBC_PXA168_PWM1	APBC_REG(0x00c)
    26. 

  26. #define APBC_PXA168_PWM2	APBC_REG(0x010)
    27. 

  27. #define APBC_PXA168_PWM3	APBC_REG(0x014)
    28. 

  28. #define APBC_PXA168_PWM4	APBC_REG(0x018)
    29. 

  29. #define APBC_PXA168_SSP1	APBC_REG(0x01c)
    30. 

  30. #define APBC_PXA168_SSP2	APBC_REG(0x020)
    31. 

  31. #define APBC_PXA168_RTC		APBC_REG(0x028)
    32. 

  32. #define APBC_PXA168_TWSI0	APBC_REG(0x02c)
    33. 

  33. #define APBC_PXA168_KPC		APBC_REG(0x030)
    34. 

  34. #define APBC_PXA168_TIMERS	APBC_REG(0x034)
    35. 

  35. #define APBC_PXA168_AIB		APBC_REG(0x03c)
    36. 

  36. #define APBC_PXA168_SW_JTAG	APBC_REG(0x040)
    37. 

  37. #define APBC_PXA168_ONEWIRE	APBC_REG(0x048)
    38. 

  38. #define APBC_PXA168_SSP3	APBC_REG(0x04c)
    39. 

  39. #define APBC_PXA168_ASFAR	APBC_REG(0x050)
    40. 

  40. #define APBC_PXA168_ASSAR	APBC_REG(0x054)
    41. 

  41. #define APBC_PXA168_SSP4	APBC_REG(0x058)
    42. 

  42. #define APBC_PXA168_SSP5	APBC_REG(0x05c)
    43. 

  43. #define APBC_PXA168_TWSI1	APBC_REG(0x06c)
    44. 

  44. #define APBC_PXA168_UART3	APBC_REG(0x070)
    45. 

  45. #define APBC_PXA168_AC97	APBC_REG(0x084)
    46. 

  46. 

  47. /*
    48. 

  48.  * APB Clock register offsets for PXA910
    49. 

  49.  */
    50. 

  50. #define APBC_PXA910_UART0	APBC_REG(0x000)
    51. 

  51. #define APBC_PXA910_UART1	APBC_REG(0x004)
    52. 

  52. #define APBC_PXA910_GPIO	APBC_REG(0x008)
    53. 

  53. #define APBC_PXA910_PWM1	APBC_REG(0x00c)
    54. 

  54. #define APBC_PXA910_PWM2	APBC_REG(0x010)
    55. 

  55. #define APBC_PXA910_PWM3	APBC_REG(0x014)
    56. 

  56. #define APBC_PXA910_PWM4	APBC_REG(0x018)
    57. 

  57. #define APBC_PXA910_SSP1	APBC_REG(0x01c)
    58. 

  58. #define APBC_PXA910_SSP2	APBC_REG(0x020)
    59. 

  59. #define APBC_PXA910_IPC		APBC_REG(0x024)
    60. 

  60. #define APBC_PXA910_TWSI0	APBC_REG(0x02c)
    61. 

  61. #define APBC_PXA910_KPC		APBC_REG(0x030)
    62. 

  62. #define APBC_PXA910_TIMERS	APBC_REG(0x034)
    63. 

  63. #define APBC_PXA910_TBROT	APBC_REG(0x038)
    64. 

  64. #define APBC_PXA910_AIB		APBC_REG(0x03c)
    65. 

  65. #define APBC_PXA910_SW_JTAG	APBC_REG(0x040)
    66. 

  66. #define APBC_PXA910_TIMERS1	APBC_REG(0x044)
    67. 

  67. #define APBC_PXA910_ONEWIRE	APBC_REG(0x048)
    68. 

  68. #define APBC_PXA910_SSP3	APBC_REG(0x04c)
    69. 

  69. #define APBC_PXA910_ASFAR	APBC_REG(0x050)
    70. 

  70. #define APBC_PXA910_ASSAR	APBC_REG(0x054)
    71. 

  71. 

  72. /* Common APB clock register bit definitions */
    73. 

  73. #define APBC_APBCLK	(1 << 0)  /* APB Bus Clock Enable */
    74. 

  74. #define APBC_FNCLK	(1 << 1)  /* Functional Clock Enable */
    75. 

  75. #define APBC_RST	(1 << 2)  /* Reset Generation */
    76. 

  76. 

  77. /* Functional Clock Selection Mask */
    78. 

  78. #define APBC_FNCLKSEL(x)	(((x) & 0xf) << 4)
    79. 

  79. 

  80. #endif /* __ASM_MACH_REGS_APBC_H */
    81.