board-dm646x-evm.c 16 KB

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  1. /*
  2. * TI DaVinci DM646X EVM board
  3. *
  4. * Derived from: arch/arm/mach-davinci/board-evm.c
  5. * Copyright (C) 2006 Texas Instruments.
  6. *
  7. * (C) 2007-2008, MontaVista Software, Inc.
  8. *
  9. * This file is licensed under the terms of the GNU General Public License
  10. * version 2. This program is licensed "as is" without any warranty of any
  11. * kind, whether express or implied.
  12. *
  13. */
  14. /**************************************************************************
  15. * Included Files
  16. **************************************************************************/
  17. #include <linux/kernel.h>
  18. #include <linux/init.h>
  19. #include <linux/leds.h>
  20. #include <linux/gpio.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/i2c.h>
  23. #include <linux/i2c/at24.h>
  24. #include <linux/i2c/pcf857x.h>
  25. #include <media/tvp514x.h>
  26. #include <linux/mtd/mtd.h>
  27. #include <linux/mtd/nand.h>
  28. #include <linux/mtd/partitions.h>
  29. #include <asm/mach-types.h>
  30. #include <asm/mach/arch.h>
  31. #include <mach/dm646x.h>
  32. #include <mach/common.h>
  33. #include <mach/serial.h>
  34. #include <mach/i2c.h>
  35. #include <mach/nand.h>
  36. #if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
  37. defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
  38. #define HAS_ATA 1
  39. #else
  40. #define HAS_ATA 0
  41. #endif
  42. #define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x20008000
  43. #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
  44. #define NAND_BLOCK_SIZE SZ_128K
  45. /* CPLD Register 0 bits to control ATA */
  46. #define DM646X_EVM_ATA_RST BIT(0)
  47. #define DM646X_EVM_ATA_PWD BIT(1)
  48. #define DM646X_EVM_PHY_MASK (0x2)
  49. #define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
  50. #define VIDCLKCTL_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
  51. #define VSCLKDIS_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
  52. #define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
  53. #define VCH2CLK_SYSCLK8 (BIT(9))
  54. #define VCH2CLK_AUXCLK (BIT(9) | BIT(8))
  55. #define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
  56. #define VCH3CLK_SYSCLK8 (BIT(13))
  57. #define VCH3CLK_AUXCLK (BIT(14) | BIT(13))
  58. #define VIDCH2CLK (BIT(10))
  59. #define VIDCH3CLK (BIT(11))
  60. #define VIDCH1CLK (BIT(4))
  61. #define TVP7002_INPUT (BIT(4))
  62. #define TVP5147_INPUT (~BIT(4))
  63. #define VPIF_INPUT_ONE_CHANNEL (BIT(5))
  64. #define VPIF_INPUT_TWO_CHANNEL (~BIT(5))
  65. #define TVP5147_CH0 "tvp514x-0"
  66. #define TVP5147_CH1 "tvp514x-1"
  67. static void __iomem *vpif_vidclkctl_reg;
  68. static void __iomem *vpif_vsclkdis_reg;
  69. /* spin lock for updating above registers */
  70. static spinlock_t vpif_reg_lock;
  71. static struct davinci_uart_config uart_config __initdata = {
  72. .enabled_uarts = (1 << 0),
  73. };
  74. /* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot
  75. * and U-Boot environment this avoids dependency on any particular combination
  76. * of UBL, U-Boot or flashing tools etc.
  77. */
  78. static struct mtd_partition davinci_nand_partitions[] = {
  79. {
  80. /* UBL, U-Boot with environment */
  81. .name = "bootloader",
  82. .offset = MTDPART_OFS_APPEND,
  83. .size = 16 * NAND_BLOCK_SIZE,
  84. .mask_flags = MTD_WRITEABLE, /* force read-only */
  85. }, {
  86. .name = "kernel",
  87. .offset = MTDPART_OFS_APPEND,
  88. .size = SZ_4M,
  89. .mask_flags = 0,
  90. }, {
  91. .name = "filesystem",
  92. .offset = MTDPART_OFS_APPEND,
  93. .size = MTDPART_SIZ_FULL,
  94. .mask_flags = 0,
  95. }
  96. };
  97. static struct davinci_nand_pdata davinci_nand_data = {
  98. .mask_cle = 0x80000,
  99. .mask_ale = 0x40000,
  100. .parts = davinci_nand_partitions,
  101. .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
  102. .ecc_mode = NAND_ECC_HW,
  103. .options = 0,
  104. };
  105. static struct resource davinci_nand_resources[] = {
  106. {
  107. .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
  108. .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
  109. .flags = IORESOURCE_MEM,
  110. }, {
  111. .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
  112. .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
  113. .flags = IORESOURCE_MEM,
  114. },
  115. };
  116. static struct platform_device davinci_nand_device = {
  117. .name = "davinci_nand",
  118. .id = 0,
  119. .num_resources = ARRAY_SIZE(davinci_nand_resources),
  120. .resource = davinci_nand_resources,
  121. .dev = {
  122. .platform_data = &davinci_nand_data,
  123. },
  124. };
  125. /* CPLD Register 0 Client: used for I/O Control */
  126. static int cpld_reg0_probe(struct i2c_client *client,
  127. const struct i2c_device_id *id)
  128. {
  129. if (HAS_ATA) {
  130. u8 data;
  131. struct i2c_msg msg[2] = {
  132. {
  133. .addr = client->addr,
  134. .flags = I2C_M_RD,
  135. .len = 1,
  136. .buf = &data,
  137. },
  138. {
  139. .addr = client->addr,
  140. .flags = 0,
  141. .len = 1,
  142. .buf = &data,
  143. },
  144. };
  145. /* Clear ATA_RSTn and ATA_PWD bits to enable ATA operation. */
  146. i2c_transfer(client->adapter, msg, 1);
  147. data &= ~(DM646X_EVM_ATA_RST | DM646X_EVM_ATA_PWD);
  148. i2c_transfer(client->adapter, msg + 1, 1);
  149. }
  150. return 0;
  151. }
  152. static const struct i2c_device_id cpld_reg_ids[] = {
  153. { "cpld_reg0", 0, },
  154. { },
  155. };
  156. static struct i2c_driver dm6467evm_cpld_driver = {
  157. .driver.name = "cpld_reg0",
  158. .id_table = cpld_reg_ids,
  159. .probe = cpld_reg0_probe,
  160. };
  161. /* LEDS */
  162. static struct gpio_led evm_leds[] = {
  163. { .name = "DS1", .active_low = 1, },
  164. { .name = "DS2", .active_low = 1, },
  165. { .name = "DS3", .active_low = 1, },
  166. { .name = "DS4", .active_low = 1, },
  167. };
  168. static const struct gpio_led_platform_data evm_led_data = {
  169. .num_leds = ARRAY_SIZE(evm_leds),
  170. .leds = evm_leds,
  171. };
  172. static struct platform_device *evm_led_dev;
  173. static int evm_led_setup(struct i2c_client *client, int gpio,
  174. unsigned int ngpio, void *c)
  175. {
  176. struct gpio_led *leds = evm_leds;
  177. int status;
  178. while (ngpio--) {
  179. leds->gpio = gpio++;
  180. leds++;
  181. };
  182. evm_led_dev = platform_device_alloc("leds-gpio", 0);
  183. platform_device_add_data(evm_led_dev, &evm_led_data,
  184. sizeof(evm_led_data));
  185. evm_led_dev->dev.parent = &client->dev;
  186. status = platform_device_add(evm_led_dev);
  187. if (status < 0) {
  188. platform_device_put(evm_led_dev);
  189. evm_led_dev = NULL;
  190. }
  191. return status;
  192. }
  193. static int evm_led_teardown(struct i2c_client *client, int gpio,
  194. unsigned ngpio, void *c)
  195. {
  196. if (evm_led_dev) {
  197. platform_device_unregister(evm_led_dev);
  198. evm_led_dev = NULL;
  199. }
  200. return 0;
  201. }
  202. static int evm_sw_gpio[4] = { -EINVAL, -EINVAL, -EINVAL, -EINVAL };
  203. static int evm_sw_setup(struct i2c_client *client, int gpio,
  204. unsigned ngpio, void *c)
  205. {
  206. int status;
  207. int i;
  208. char label[10];
  209. for (i = 0; i < 4; ++i) {
  210. snprintf(label, 10, "user_sw%d", i);
  211. status = gpio_request(gpio, label);
  212. if (status)
  213. goto out_free;
  214. evm_sw_gpio[i] = gpio++;
  215. status = gpio_direction_input(evm_sw_gpio[i]);
  216. if (status) {
  217. gpio_free(evm_sw_gpio[i]);
  218. evm_sw_gpio[i] = -EINVAL;
  219. goto out_free;
  220. }
  221. status = gpio_export(evm_sw_gpio[i], 0);
  222. if (status) {
  223. gpio_free(evm_sw_gpio[i]);
  224. evm_sw_gpio[i] = -EINVAL;
  225. goto out_free;
  226. }
  227. }
  228. return status;
  229. out_free:
  230. for (i = 0; i < 4; ++i) {
  231. if (evm_sw_gpio[i] != -EINVAL) {
  232. gpio_free(evm_sw_gpio[i]);
  233. evm_sw_gpio[i] = -EINVAL;
  234. }
  235. }
  236. return status;
  237. }
  238. static int evm_sw_teardown(struct i2c_client *client, int gpio,
  239. unsigned ngpio, void *c)
  240. {
  241. int i;
  242. for (i = 0; i < 4; ++i) {
  243. if (evm_sw_gpio[i] != -EINVAL) {
  244. gpio_unexport(evm_sw_gpio[i]);
  245. gpio_free(evm_sw_gpio[i]);
  246. evm_sw_gpio[i] = -EINVAL;
  247. }
  248. }
  249. return 0;
  250. }
  251. static int evm_pcf_setup(struct i2c_client *client, int gpio,
  252. unsigned int ngpio, void *c)
  253. {
  254. int status;
  255. if (ngpio < 8)
  256. return -EINVAL;
  257. status = evm_sw_setup(client, gpio, 4, c);
  258. if (status)
  259. return status;
  260. return evm_led_setup(client, gpio+4, 4, c);
  261. }
  262. static int evm_pcf_teardown(struct i2c_client *client, int gpio,
  263. unsigned int ngpio, void *c)
  264. {
  265. BUG_ON(ngpio < 8);
  266. evm_sw_teardown(client, gpio, 4, c);
  267. evm_led_teardown(client, gpio+4, 4, c);
  268. return 0;
  269. }
  270. static struct pcf857x_platform_data pcf_data = {
  271. .gpio_base = DAVINCI_N_GPIO+1,
  272. .setup = evm_pcf_setup,
  273. .teardown = evm_pcf_teardown,
  274. };
  275. /* Most of this EEPROM is unused, but U-Boot uses some data:
  276. * - 0x7f00, 6 bytes Ethernet Address
  277. * - ... newer boards may have more
  278. */
  279. static struct at24_platform_data eeprom_info = {
  280. .byte_len = (256*1024) / 8,
  281. .page_size = 64,
  282. .flags = AT24_FLAG_ADDR16,
  283. .setup = davinci_get_mac_addr,
  284. .context = (void *)0x7f00,
  285. };
  286. static u8 dm646x_iis_serializer_direction[] = {
  287. TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE,
  288. };
  289. static u8 dm646x_dit_serializer_direction[] = {
  290. TX_MODE,
  291. };
  292. static struct snd_platform_data dm646x_evm_snd_data[] = {
  293. {
  294. .tx_dma_offset = 0x400,
  295. .rx_dma_offset = 0x400,
  296. .op_mode = DAVINCI_MCASP_IIS_MODE,
  297. .num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction),
  298. .tdm_slots = 2,
  299. .serial_dir = dm646x_iis_serializer_direction,
  300. .eventq_no = EVENTQ_0,
  301. },
  302. {
  303. .tx_dma_offset = 0x400,
  304. .rx_dma_offset = 0,
  305. .op_mode = DAVINCI_MCASP_DIT_MODE,
  306. .num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction),
  307. .tdm_slots = 32,
  308. .serial_dir = dm646x_dit_serializer_direction,
  309. .eventq_no = EVENTQ_0,
  310. },
  311. };
  312. static struct i2c_client *cpld_client;
  313. static int cpld_video_probe(struct i2c_client *client,
  314. const struct i2c_device_id *id)
  315. {
  316. cpld_client = client;
  317. return 0;
  318. }
  319. static int __devexit cpld_video_remove(struct i2c_client *client)
  320. {
  321. cpld_client = NULL;
  322. return 0;
  323. }
  324. static const struct i2c_device_id cpld_video_id[] = {
  325. { "cpld_video", 0 },
  326. { }
  327. };
  328. static struct i2c_driver cpld_video_driver = {
  329. .driver = {
  330. .name = "cpld_video",
  331. },
  332. .probe = cpld_video_probe,
  333. .remove = cpld_video_remove,
  334. .id_table = cpld_video_id,
  335. };
  336. static void evm_init_cpld(void)
  337. {
  338. i2c_add_driver(&cpld_video_driver);
  339. }
  340. static struct i2c_board_info __initdata i2c_info[] = {
  341. {
  342. I2C_BOARD_INFO("24c256", 0x50),
  343. .platform_data = &eeprom_info,
  344. },
  345. {
  346. I2C_BOARD_INFO("pcf8574a", 0x38),
  347. .platform_data = &pcf_data,
  348. },
  349. {
  350. I2C_BOARD_INFO("cpld_reg0", 0x3a),
  351. },
  352. {
  353. I2C_BOARD_INFO("tlv320aic33", 0x18),
  354. },
  355. {
  356. I2C_BOARD_INFO("cpld_video", 0x3b),
  357. },
  358. };
  359. static struct davinci_i2c_platform_data i2c_pdata = {
  360. .bus_freq = 100 /* kHz */,
  361. .bus_delay = 0 /* usec */,
  362. };
  363. static int set_vpif_clock(int mux_mode, int hd)
  364. {
  365. unsigned long flags;
  366. unsigned int value;
  367. int val = 0;
  368. int err = 0;
  369. if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg || !cpld_client)
  370. return -ENXIO;
  371. /* disable the clock */
  372. spin_lock_irqsave(&vpif_reg_lock, flags);
  373. value = __raw_readl(vpif_vsclkdis_reg);
  374. value |= (VIDCH3CLK | VIDCH2CLK);
  375. __raw_writel(value, vpif_vsclkdis_reg);
  376. spin_unlock_irqrestore(&vpif_reg_lock, flags);
  377. val = i2c_smbus_read_byte(cpld_client);
  378. if (val < 0)
  379. return val;
  380. if (mux_mode == 1)
  381. val &= ~0x40;
  382. else
  383. val |= 0x40;
  384. err = i2c_smbus_write_byte(cpld_client, val);
  385. if (err)
  386. return err;
  387. value = __raw_readl(vpif_vidclkctl_reg);
  388. value &= ~(VCH2CLK_MASK);
  389. value &= ~(VCH3CLK_MASK);
  390. if (hd >= 1)
  391. value |= (VCH2CLK_SYSCLK8 | VCH3CLK_SYSCLK8);
  392. else
  393. value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK);
  394. __raw_writel(value, vpif_vidclkctl_reg);
  395. spin_lock_irqsave(&vpif_reg_lock, flags);
  396. value = __raw_readl(vpif_vsclkdis_reg);
  397. /* enable the clock */
  398. value &= ~(VIDCH3CLK | VIDCH2CLK);
  399. __raw_writel(value, vpif_vsclkdis_reg);
  400. spin_unlock_irqrestore(&vpif_reg_lock, flags);
  401. return 0;
  402. }
  403. static struct vpif_subdev_info dm646x_vpif_subdev[] = {
  404. {
  405. .name = "adv7343",
  406. .board_info = {
  407. I2C_BOARD_INFO("adv7343", 0x2a),
  408. },
  409. },
  410. {
  411. .name = "ths7303",
  412. .board_info = {
  413. I2C_BOARD_INFO("ths7303", 0x2c),
  414. },
  415. },
  416. };
  417. static const char *output[] = {
  418. "Composite",
  419. "Component",
  420. "S-Video",
  421. };
  422. static struct vpif_display_config dm646x_vpif_display_config = {
  423. .set_clock = set_vpif_clock,
  424. .subdevinfo = dm646x_vpif_subdev,
  425. .subdev_count = ARRAY_SIZE(dm646x_vpif_subdev),
  426. .output = output,
  427. .output_count = ARRAY_SIZE(output),
  428. .card_name = "DM646x EVM",
  429. };
  430. /**
  431. * setup_vpif_input_path()
  432. * @channel: channel id (0 - CH0, 1 - CH1)
  433. * @sub_dev_name: ptr sub device name
  434. *
  435. * This will set vpif input to capture data from tvp514x or
  436. * tvp7002.
  437. */
  438. static int setup_vpif_input_path(int channel, const char *sub_dev_name)
  439. {
  440. int err = 0;
  441. int val;
  442. /* for channel 1, we don't do anything */
  443. if (channel != 0)
  444. return 0;
  445. if (!cpld_client)
  446. return -ENXIO;
  447. val = i2c_smbus_read_byte(cpld_client);
  448. if (val < 0)
  449. return val;
  450. if (!strcmp(sub_dev_name, TVP5147_CH0) ||
  451. !strcmp(sub_dev_name, TVP5147_CH1))
  452. val &= TVP5147_INPUT;
  453. else
  454. val |= TVP7002_INPUT;
  455. err = i2c_smbus_write_byte(cpld_client, val);
  456. if (err)
  457. return err;
  458. return 0;
  459. }
  460. /**
  461. * setup_vpif_input_channel_mode()
  462. * @mux_mode: mux mode. 0 - 1 channel or (1) - 2 channel
  463. *
  464. * This will setup input mode to one channel (TVP7002) or 2 channel (TVP5147)
  465. */
  466. static int setup_vpif_input_channel_mode(int mux_mode)
  467. {
  468. unsigned long flags;
  469. int err = 0;
  470. int val;
  471. u32 value;
  472. if (!vpif_vsclkdis_reg || !cpld_client)
  473. return -ENXIO;
  474. val = i2c_smbus_read_byte(cpld_client);
  475. if (val < 0)
  476. return val;
  477. spin_lock_irqsave(&vpif_reg_lock, flags);
  478. value = __raw_readl(vpif_vsclkdis_reg);
  479. if (mux_mode) {
  480. val &= VPIF_INPUT_TWO_CHANNEL;
  481. value |= VIDCH1CLK;
  482. } else {
  483. val |= VPIF_INPUT_ONE_CHANNEL;
  484. value &= ~VIDCH1CLK;
  485. }
  486. __raw_writel(value, vpif_vsclkdis_reg);
  487. spin_unlock_irqrestore(&vpif_reg_lock, flags);
  488. err = i2c_smbus_write_byte(cpld_client, val);
  489. if (err)
  490. return err;
  491. return 0;
  492. }
  493. static struct tvp514x_platform_data tvp5146_pdata = {
  494. .clk_polarity = 0,
  495. .hs_polarity = 1,
  496. .vs_polarity = 1
  497. };
  498. #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
  499. static struct vpif_subdev_info vpif_capture_sdev_info[] = {
  500. {
  501. .name = TVP5147_CH0,
  502. .board_info = {
  503. I2C_BOARD_INFO("tvp5146", 0x5d),
  504. .platform_data = &tvp5146_pdata,
  505. },
  506. .input = INPUT_CVBS_VI2B,
  507. .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
  508. .can_route = 1,
  509. .vpif_if = {
  510. .if_type = VPIF_IF_BT656,
  511. .hd_pol = 1,
  512. .vd_pol = 1,
  513. .fid_pol = 0,
  514. },
  515. },
  516. {
  517. .name = TVP5147_CH1,
  518. .board_info = {
  519. I2C_BOARD_INFO("tvp5146", 0x5c),
  520. .platform_data = &tvp5146_pdata,
  521. },
  522. .input = INPUT_SVIDEO_VI2C_VI1C,
  523. .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
  524. .can_route = 1,
  525. .vpif_if = {
  526. .if_type = VPIF_IF_BT656,
  527. .hd_pol = 1,
  528. .vd_pol = 1,
  529. .fid_pol = 0,
  530. },
  531. },
  532. };
  533. static const struct vpif_input dm6467_ch0_inputs[] = {
  534. {
  535. .input = {
  536. .index = 0,
  537. .name = "Composite",
  538. .type = V4L2_INPUT_TYPE_CAMERA,
  539. .std = TVP514X_STD_ALL,
  540. },
  541. .subdev_name = TVP5147_CH0,
  542. },
  543. };
  544. static const struct vpif_input dm6467_ch1_inputs[] = {
  545. {
  546. .input = {
  547. .index = 0,
  548. .name = "S-Video",
  549. .type = V4L2_INPUT_TYPE_CAMERA,
  550. .std = TVP514X_STD_ALL,
  551. },
  552. .subdev_name = TVP5147_CH1,
  553. },
  554. };
  555. static struct vpif_capture_config dm646x_vpif_capture_cfg = {
  556. .setup_input_path = setup_vpif_input_path,
  557. .setup_input_channel_mode = setup_vpif_input_channel_mode,
  558. .subdev_info = vpif_capture_sdev_info,
  559. .subdev_count = ARRAY_SIZE(vpif_capture_sdev_info),
  560. .chan_config[0] = {
  561. .inputs = dm6467_ch0_inputs,
  562. .input_count = ARRAY_SIZE(dm6467_ch0_inputs),
  563. },
  564. .chan_config[1] = {
  565. .inputs = dm6467_ch1_inputs,
  566. .input_count = ARRAY_SIZE(dm6467_ch1_inputs),
  567. },
  568. };
  569. static void __init evm_init_video(void)
  570. {
  571. vpif_vidclkctl_reg = ioremap(VIDCLKCTL_OFFSET, 4);
  572. vpif_vsclkdis_reg = ioremap(VSCLKDIS_OFFSET, 4);
  573. if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg) {
  574. pr_err("Can't map VPIF VIDCLKCTL or VSCLKDIS registers\n");
  575. return;
  576. }
  577. spin_lock_init(&vpif_reg_lock);
  578. dm646x_setup_vpif(&dm646x_vpif_display_config,
  579. &dm646x_vpif_capture_cfg);
  580. }
  581. static void __init evm_init_i2c(void)
  582. {
  583. davinci_init_i2c(&i2c_pdata);
  584. i2c_add_driver(&dm6467evm_cpld_driver);
  585. i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
  586. evm_init_cpld();
  587. evm_init_video();
  588. }
  589. static void __init davinci_map_io(void)
  590. {
  591. dm646x_init();
  592. }
  593. static __init void evm_init(void)
  594. {
  595. struct davinci_soc_info *soc_info = &davinci_soc_info;
  596. evm_init_i2c();
  597. davinci_serial_init(&uart_config);
  598. dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
  599. dm646x_init_mcasp1(&dm646x_evm_snd_data[1]);
  600. platform_device_register(&davinci_nand_device);
  601. if (HAS_ATA)
  602. dm646x_init_ide();
  603. soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK;
  604. soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY;
  605. }
  606. static __init void davinci_dm646x_evm_irq_init(void)
  607. {
  608. davinci_irq_init();
  609. }
  610. MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
  611. .phys_io = IO_PHYS,
  612. .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
  613. .boot_params = (0x80000100),
  614. .map_io = davinci_map_io,
  615. .init_irq = davinci_dm646x_evm_irq_init,
  616. .timer = &davinci_timer,
  617. .init_machine = evm_init,
  618. MACHINE_END