board.txt 1.5 KB

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  1. * Board Control and Status (BCSR)
  2. Required properties:
  3. - compatible : Should be "fsl,<board>-bcsr"
  4. - reg : Offset and length of the register set for the device
  5. Example:
  6. bcsr@f8000000 {
  7. compatible = "fsl,mpc8360mds-bcsr";
  8. reg = <f8000000 8000>;
  9. };
  10. * Freescale on board FPGA
  11. This is the memory-mapped registers for on board FPGA.
  12. Required properities:
  13. - compatible : should be "fsl,fpga-pixis".
  14. - reg : should contain the address and the length of the FPPGA register
  15. set.
  16. - interrupt-parent: should specify phandle for the interrupt controller.
  17. - interrupts : should specify event (wakeup) IRQ.
  18. Example (MPC8610HPCD):
  19. board-control@e8000000 {
  20. compatible = "fsl,fpga-pixis";
  21. reg = <0xe8000000 32>;
  22. interrupt-parent = <&mpic>;
  23. interrupts = <8 8>;
  24. };
  25. * Freescale BCSR GPIO banks
  26. Some BCSR registers act as simple GPIO controllers, each such
  27. register can be represented by the gpio-controller node.
  28. Required properities:
  29. - compatible : Should be "fsl,<board>-bcsr-gpio".
  30. - reg : Should contain the address and the length of the GPIO bank
  31. register.
  32. - #gpio-cells : Should be two. The first cell is the pin number and the
  33. second cell is used to specify optional parameters (currently unused).
  34. - gpio-controller : Marks the port as GPIO controller.
  35. Example:
  36. bcsr@1,0 {
  37. #address-cells = <1>;
  38. #size-cells = <1>;
  39. compatible = "fsl,mpc8360mds-bcsr";
  40. reg = <1 0 0x8000>;
  41. ranges = <0 1 0 0x8000>;
  42. bcsr13: gpio-controller@d {
  43. #gpio-cells = <2>;
  44. compatible = "fsl,mpc8360mds-bcsr-gpio";
  45. reg = <0xd 1>;
  46. gpio-controller;
  47. };
  48. };