r8a66597-udc.h 6.2 KB

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  1. /*
  2. * R8A66597 UDC
  3. *
  4. * Copyright (C) 2007-2009 Renesas Solutions Corp.
  5. *
  6. * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20. *
  21. */
  22. #ifndef __R8A66597_H__
  23. #define __R8A66597_H__
  24. #ifdef CONFIG_HAVE_CLK
  25. #include <linux/clk.h>
  26. #endif
  27. #include <linux/usb/r8a66597.h>
  28. #define R8A66597_MAX_SAMPLING 10
  29. #define R8A66597_MAX_NUM_PIPE 8
  30. #define R8A66597_MAX_NUM_BULK 3
  31. #define R8A66597_MAX_NUM_ISOC 2
  32. #define R8A66597_MAX_NUM_INT 2
  33. #define R8A66597_BASE_PIPENUM_BULK 3
  34. #define R8A66597_BASE_PIPENUM_ISOC 1
  35. #define R8A66597_BASE_PIPENUM_INT 6
  36. #define R8A66597_BASE_BUFNUM 6
  37. #define R8A66597_MAX_BUFNUM 0x4F
  38. #define is_bulk_pipe(pipenum) \
  39. ((pipenum >= R8A66597_BASE_PIPENUM_BULK) && \
  40. (pipenum < (R8A66597_BASE_PIPENUM_BULK + R8A66597_MAX_NUM_BULK)))
  41. #define is_interrupt_pipe(pipenum) \
  42. ((pipenum >= R8A66597_BASE_PIPENUM_INT) && \
  43. (pipenum < (R8A66597_BASE_PIPENUM_INT + R8A66597_MAX_NUM_INT)))
  44. #define is_isoc_pipe(pipenum) \
  45. ((pipenum >= R8A66597_BASE_PIPENUM_ISOC) && \
  46. (pipenum < (R8A66597_BASE_PIPENUM_ISOC + R8A66597_MAX_NUM_ISOC)))
  47. struct r8a66597_pipe_info {
  48. u16 pipe;
  49. u16 epnum;
  50. u16 maxpacket;
  51. u16 type;
  52. u16 interval;
  53. u16 dir_in;
  54. };
  55. struct r8a66597_request {
  56. struct usb_request req;
  57. struct list_head queue;
  58. };
  59. struct r8a66597_ep {
  60. struct usb_ep ep;
  61. struct r8a66597 *r8a66597;
  62. struct list_head queue;
  63. unsigned busy:1;
  64. unsigned wedge:1;
  65. unsigned internal_ccpl:1; /* use only control */
  66. /* this member can able to after r8a66597_enable */
  67. unsigned use_dma:1;
  68. u16 pipenum;
  69. u16 type;
  70. const struct usb_endpoint_descriptor *desc;
  71. /* register address */
  72. unsigned char fifoaddr;
  73. unsigned char fifosel;
  74. unsigned char fifoctr;
  75. unsigned char fifotrn;
  76. unsigned char pipectr;
  77. };
  78. struct r8a66597 {
  79. spinlock_t lock;
  80. unsigned long reg;
  81. #ifdef CONFIG_HAVE_CLK
  82. struct clk *clk;
  83. #endif
  84. struct r8a66597_platdata *pdata;
  85. struct usb_gadget gadget;
  86. struct usb_gadget_driver *driver;
  87. struct r8a66597_ep ep[R8A66597_MAX_NUM_PIPE];
  88. struct r8a66597_ep *pipenum2ep[R8A66597_MAX_NUM_PIPE];
  89. struct r8a66597_ep *epaddr2ep[16];
  90. struct timer_list timer;
  91. struct usb_request *ep0_req; /* for internal request */
  92. u16 ep0_data; /* for internal request */
  93. u16 old_vbus;
  94. u16 scount;
  95. u16 old_dvsq;
  96. /* pipe config */
  97. unsigned char bulk;
  98. unsigned char interrupt;
  99. unsigned char isochronous;
  100. unsigned char num_dma;
  101. unsigned irq_sense_low:1;
  102. };
  103. #define gadget_to_r8a66597(_gadget) \
  104. container_of(_gadget, struct r8a66597, gadget)
  105. #define r8a66597_to_gadget(r8a66597) (&r8a66597->gadget)
  106. static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
  107. {
  108. return inw(r8a66597->reg + offset);
  109. }
  110. static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
  111. unsigned long offset, u16 *buf,
  112. int len)
  113. {
  114. if (r8a66597->pdata->on_chip) {
  115. unsigned long fifoaddr = r8a66597->reg + offset;
  116. unsigned long count;
  117. union {
  118. unsigned long dword;
  119. unsigned char byte[4];
  120. } data;
  121. unsigned char *pb;
  122. int i;
  123. count = len / 4;
  124. insl(fifoaddr, buf, count);
  125. if (len & 0x00000003) {
  126. data.dword = inl(fifoaddr);
  127. pb = (unsigned char *)buf + count * 4;
  128. for (i = 0; i < (len & 0x00000003); i++)
  129. pb[i] = data.byte[i];
  130. }
  131. } else {
  132. len = (len + 1) / 2;
  133. insw(r8a66597->reg + offset, buf, len);
  134. }
  135. }
  136. static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
  137. unsigned long offset)
  138. {
  139. outw(val, r8a66597->reg + offset);
  140. }
  141. static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
  142. unsigned long offset, u16 *buf,
  143. int len)
  144. {
  145. unsigned long fifoaddr = r8a66597->reg + offset;
  146. if (r8a66597->pdata->on_chip) {
  147. unsigned long count;
  148. unsigned char *pb;
  149. int i;
  150. count = len / 4;
  151. outsl(fifoaddr, buf, count);
  152. if (len & 0x00000003) {
  153. pb = (unsigned char *)buf + count * 4;
  154. for (i = 0; i < (len & 0x00000003); i++) {
  155. if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
  156. outb(pb[i], fifoaddr + i);
  157. else
  158. outb(pb[i], fifoaddr + 3 - i);
  159. }
  160. }
  161. } else {
  162. int odd = len & 0x0001;
  163. len = len / 2;
  164. outsw(fifoaddr, buf, len);
  165. if (unlikely(odd)) {
  166. buf = &buf[len];
  167. outb((unsigned char)*buf, fifoaddr);
  168. }
  169. }
  170. }
  171. static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
  172. u16 val, u16 pat, unsigned long offset)
  173. {
  174. u16 tmp;
  175. tmp = r8a66597_read(r8a66597, offset);
  176. tmp = tmp & (~pat);
  177. tmp = tmp | val;
  178. r8a66597_write(r8a66597, tmp, offset);
  179. }
  180. static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
  181. {
  182. u16 clock = 0;
  183. switch (pdata->xtal) {
  184. case R8A66597_PLATDATA_XTAL_12MHZ:
  185. clock = XTAL12;
  186. break;
  187. case R8A66597_PLATDATA_XTAL_24MHZ:
  188. clock = XTAL24;
  189. break;
  190. case R8A66597_PLATDATA_XTAL_48MHZ:
  191. clock = XTAL48;
  192. break;
  193. default:
  194. printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
  195. break;
  196. }
  197. return clock;
  198. }
  199. #define r8a66597_bclr(r8a66597, val, offset) \
  200. r8a66597_mdfy(r8a66597, 0, val, offset)
  201. #define r8a66597_bset(r8a66597, val, offset) \
  202. r8a66597_mdfy(r8a66597, val, 0, offset)
  203. #define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
  204. #define enable_irq_ready(r8a66597, pipenum) \
  205. enable_pipe_irq(r8a66597, pipenum, BRDYENB)
  206. #define disable_irq_ready(r8a66597, pipenum) \
  207. disable_pipe_irq(r8a66597, pipenum, BRDYENB)
  208. #define enable_irq_empty(r8a66597, pipenum) \
  209. enable_pipe_irq(r8a66597, pipenum, BEMPENB)
  210. #define disable_irq_empty(r8a66597, pipenum) \
  211. disable_pipe_irq(r8a66597, pipenum, BEMPENB)
  212. #define enable_irq_nrdy(r8a66597, pipenum) \
  213. enable_pipe_irq(r8a66597, pipenum, NRDYENB)
  214. #define disable_irq_nrdy(r8a66597, pipenum) \
  215. disable_pipe_irq(r8a66597, pipenum, NRDYENB)
  216. #endif /* __R8A66597_H__ */