aer_inject.c 10 KB

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  1. /*
  2. * PCIE AER software error injection support.
  3. *
  4. * Debuging PCIE AER code is quite difficult because it is hard to
  5. * trigger various real hardware errors. Software based error
  6. * injection can fake almost all kinds of errors with the help of a
  7. * user space helper tool aer-inject, which can be gotten from:
  8. * http://www.kernel.org/pub/linux/utils/pci/aer-inject/
  9. *
  10. * Copyright 2009 Intel Corporation.
  11. * Huang Ying <ying.huang@intel.com>
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License
  15. * as published by the Free Software Foundation; version 2
  16. * of the License.
  17. *
  18. */
  19. #include <linux/module.h>
  20. #include <linux/init.h>
  21. #include <linux/miscdevice.h>
  22. #include <linux/pci.h>
  23. #include <linux/fs.h>
  24. #include <linux/uaccess.h>
  25. #include "aerdrv.h"
  26. struct aer_error_inj {
  27. u8 bus;
  28. u8 dev;
  29. u8 fn;
  30. u32 uncor_status;
  31. u32 cor_status;
  32. u32 header_log0;
  33. u32 header_log1;
  34. u32 header_log2;
  35. u32 header_log3;
  36. };
  37. struct aer_error {
  38. struct list_head list;
  39. unsigned int bus;
  40. unsigned int devfn;
  41. int pos_cap_err;
  42. u32 uncor_status;
  43. u32 cor_status;
  44. u32 header_log0;
  45. u32 header_log1;
  46. u32 header_log2;
  47. u32 header_log3;
  48. u32 root_status;
  49. u32 source_id;
  50. };
  51. struct pci_bus_ops {
  52. struct list_head list;
  53. struct pci_bus *bus;
  54. struct pci_ops *ops;
  55. };
  56. static LIST_HEAD(einjected);
  57. static LIST_HEAD(pci_bus_ops_list);
  58. /* Protect einjected and pci_bus_ops_list */
  59. static DEFINE_SPINLOCK(inject_lock);
  60. static void aer_error_init(struct aer_error *err, unsigned int bus,
  61. unsigned int devfn, int pos_cap_err)
  62. {
  63. INIT_LIST_HEAD(&err->list);
  64. err->bus = bus;
  65. err->devfn = devfn;
  66. err->pos_cap_err = pos_cap_err;
  67. }
  68. /* inject_lock must be held before calling */
  69. static struct aer_error *__find_aer_error(unsigned int bus, unsigned int devfn)
  70. {
  71. struct aer_error *err;
  72. list_for_each_entry(err, &einjected, list) {
  73. if (bus == err->bus && devfn == err->devfn)
  74. return err;
  75. }
  76. return NULL;
  77. }
  78. /* inject_lock must be held before calling */
  79. static struct aer_error *__find_aer_error_by_dev(struct pci_dev *dev)
  80. {
  81. return __find_aer_error(dev->bus->number, dev->devfn);
  82. }
  83. /* inject_lock must be held before calling */
  84. static struct pci_ops *__find_pci_bus_ops(struct pci_bus *bus)
  85. {
  86. struct pci_bus_ops *bus_ops;
  87. list_for_each_entry(bus_ops, &pci_bus_ops_list, list) {
  88. if (bus_ops->bus == bus)
  89. return bus_ops->ops;
  90. }
  91. return NULL;
  92. }
  93. static struct pci_bus_ops *pci_bus_ops_pop(void)
  94. {
  95. unsigned long flags;
  96. struct pci_bus_ops *bus_ops = NULL;
  97. spin_lock_irqsave(&inject_lock, flags);
  98. if (list_empty(&pci_bus_ops_list))
  99. bus_ops = NULL;
  100. else {
  101. struct list_head *lh = pci_bus_ops_list.next;
  102. list_del(lh);
  103. bus_ops = list_entry(lh, struct pci_bus_ops, list);
  104. }
  105. spin_unlock_irqrestore(&inject_lock, flags);
  106. return bus_ops;
  107. }
  108. static u32 *find_pci_config_dword(struct aer_error *err, int where,
  109. int *prw1cs)
  110. {
  111. int rw1cs = 0;
  112. u32 *target = NULL;
  113. if (err->pos_cap_err == -1)
  114. return NULL;
  115. switch (where - err->pos_cap_err) {
  116. case PCI_ERR_UNCOR_STATUS:
  117. target = &err->uncor_status;
  118. rw1cs = 1;
  119. break;
  120. case PCI_ERR_COR_STATUS:
  121. target = &err->cor_status;
  122. rw1cs = 1;
  123. break;
  124. case PCI_ERR_HEADER_LOG:
  125. target = &err->header_log0;
  126. break;
  127. case PCI_ERR_HEADER_LOG+4:
  128. target = &err->header_log1;
  129. break;
  130. case PCI_ERR_HEADER_LOG+8:
  131. target = &err->header_log2;
  132. break;
  133. case PCI_ERR_HEADER_LOG+12:
  134. target = &err->header_log3;
  135. break;
  136. case PCI_ERR_ROOT_STATUS:
  137. target = &err->root_status;
  138. rw1cs = 1;
  139. break;
  140. case PCI_ERR_ROOT_COR_SRC:
  141. target = &err->source_id;
  142. break;
  143. }
  144. if (prw1cs)
  145. *prw1cs = rw1cs;
  146. return target;
  147. }
  148. static int pci_read_aer(struct pci_bus *bus, unsigned int devfn, int where,
  149. int size, u32 *val)
  150. {
  151. u32 *sim;
  152. struct aer_error *err;
  153. unsigned long flags;
  154. struct pci_ops *ops;
  155. spin_lock_irqsave(&inject_lock, flags);
  156. if (size != sizeof(u32))
  157. goto out;
  158. err = __find_aer_error(bus->number, devfn);
  159. if (!err)
  160. goto out;
  161. sim = find_pci_config_dword(err, where, NULL);
  162. if (sim) {
  163. *val = *sim;
  164. spin_unlock_irqrestore(&inject_lock, flags);
  165. return 0;
  166. }
  167. out:
  168. ops = __find_pci_bus_ops(bus);
  169. spin_unlock_irqrestore(&inject_lock, flags);
  170. return ops->read(bus, devfn, where, size, val);
  171. }
  172. int pci_write_aer(struct pci_bus *bus, unsigned int devfn, int where, int size,
  173. u32 val)
  174. {
  175. u32 *sim;
  176. struct aer_error *err;
  177. unsigned long flags;
  178. int rw1cs;
  179. struct pci_ops *ops;
  180. spin_lock_irqsave(&inject_lock, flags);
  181. if (size != sizeof(u32))
  182. goto out;
  183. err = __find_aer_error(bus->number, devfn);
  184. if (!err)
  185. goto out;
  186. sim = find_pci_config_dword(err, where, &rw1cs);
  187. if (sim) {
  188. if (rw1cs)
  189. *sim ^= val;
  190. else
  191. *sim = val;
  192. spin_unlock_irqrestore(&inject_lock, flags);
  193. return 0;
  194. }
  195. out:
  196. ops = __find_pci_bus_ops(bus);
  197. spin_unlock_irqrestore(&inject_lock, flags);
  198. return ops->write(bus, devfn, where, size, val);
  199. }
  200. static struct pci_ops pci_ops_aer = {
  201. .read = pci_read_aer,
  202. .write = pci_write_aer,
  203. };
  204. static void pci_bus_ops_init(struct pci_bus_ops *bus_ops,
  205. struct pci_bus *bus,
  206. struct pci_ops *ops)
  207. {
  208. INIT_LIST_HEAD(&bus_ops->list);
  209. bus_ops->bus = bus;
  210. bus_ops->ops = ops;
  211. }
  212. static int pci_bus_set_aer_ops(struct pci_bus *bus)
  213. {
  214. struct pci_ops *ops;
  215. struct pci_bus_ops *bus_ops;
  216. unsigned long flags;
  217. bus_ops = kmalloc(sizeof(*bus_ops), GFP_KERNEL);
  218. if (!bus_ops)
  219. return -ENOMEM;
  220. ops = pci_bus_set_ops(bus, &pci_ops_aer);
  221. spin_lock_irqsave(&inject_lock, flags);
  222. if (ops == &pci_ops_aer)
  223. goto out;
  224. pci_bus_ops_init(bus_ops, bus, ops);
  225. list_add(&bus_ops->list, &pci_bus_ops_list);
  226. bus_ops = NULL;
  227. out:
  228. spin_unlock_irqrestore(&inject_lock, flags);
  229. kfree(bus_ops);
  230. return 0;
  231. }
  232. static struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
  233. {
  234. while (1) {
  235. if (!dev->is_pcie)
  236. break;
  237. if (dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT)
  238. return dev;
  239. if (!dev->bus->self)
  240. break;
  241. dev = dev->bus->self;
  242. }
  243. return NULL;
  244. }
  245. static int find_aer_device_iter(struct device *device, void *data)
  246. {
  247. struct pcie_device **result = data;
  248. struct pcie_device *pcie_dev;
  249. if (device->bus == &pcie_port_bus_type) {
  250. pcie_dev = to_pcie_device(device);
  251. if (pcie_dev->service & PCIE_PORT_SERVICE_AER) {
  252. *result = pcie_dev;
  253. return 1;
  254. }
  255. }
  256. return 0;
  257. }
  258. static int find_aer_device(struct pci_dev *dev, struct pcie_device **result)
  259. {
  260. return device_for_each_child(&dev->dev, result, find_aer_device_iter);
  261. }
  262. static int aer_inject(struct aer_error_inj *einj)
  263. {
  264. struct aer_error *err, *rperr;
  265. struct aer_error *err_alloc = NULL, *rperr_alloc = NULL;
  266. struct pci_dev *dev, *rpdev;
  267. struct pcie_device *edev;
  268. unsigned long flags;
  269. unsigned int devfn = PCI_DEVFN(einj->dev, einj->fn);
  270. int pos_cap_err, rp_pos_cap_err;
  271. u32 sever;
  272. int ret = 0;
  273. dev = pci_get_bus_and_slot(einj->bus, devfn);
  274. if (!dev)
  275. return -EINVAL;
  276. rpdev = pcie_find_root_port(dev);
  277. if (!rpdev) {
  278. ret = -EINVAL;
  279. goto out_put;
  280. }
  281. pos_cap_err = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
  282. if (!pos_cap_err) {
  283. ret = -EIO;
  284. goto out_put;
  285. }
  286. pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_SEVER, &sever);
  287. rp_pos_cap_err = pci_find_ext_capability(rpdev, PCI_EXT_CAP_ID_ERR);
  288. if (!rp_pos_cap_err) {
  289. ret = -EIO;
  290. goto out_put;
  291. }
  292. err_alloc = kzalloc(sizeof(struct aer_error), GFP_KERNEL);
  293. if (!err_alloc) {
  294. ret = -ENOMEM;
  295. goto out_put;
  296. }
  297. rperr_alloc = kzalloc(sizeof(struct aer_error), GFP_KERNEL);
  298. if (!rperr_alloc) {
  299. ret = -ENOMEM;
  300. goto out_put;
  301. }
  302. spin_lock_irqsave(&inject_lock, flags);
  303. err = __find_aer_error_by_dev(dev);
  304. if (!err) {
  305. err = err_alloc;
  306. err_alloc = NULL;
  307. aer_error_init(err, einj->bus, devfn, pos_cap_err);
  308. list_add(&err->list, &einjected);
  309. }
  310. err->uncor_status |= einj->uncor_status;
  311. err->cor_status |= einj->cor_status;
  312. err->header_log0 = einj->header_log0;
  313. err->header_log1 = einj->header_log1;
  314. err->header_log2 = einj->header_log2;
  315. err->header_log3 = einj->header_log3;
  316. rperr = __find_aer_error_by_dev(rpdev);
  317. if (!rperr) {
  318. rperr = rperr_alloc;
  319. rperr_alloc = NULL;
  320. aer_error_init(rperr, rpdev->bus->number, rpdev->devfn,
  321. rp_pos_cap_err);
  322. list_add(&rperr->list, &einjected);
  323. }
  324. if (einj->cor_status) {
  325. if (rperr->root_status & PCI_ERR_ROOT_COR_RCV)
  326. rperr->root_status |= PCI_ERR_ROOT_MULTI_COR_RCV;
  327. else
  328. rperr->root_status |= PCI_ERR_ROOT_COR_RCV;
  329. rperr->source_id &= 0xffff0000;
  330. rperr->source_id |= (einj->bus << 8) | devfn;
  331. }
  332. if (einj->uncor_status) {
  333. if (rperr->root_status & PCI_ERR_ROOT_UNCOR_RCV)
  334. rperr->root_status |= PCI_ERR_ROOT_MULTI_UNCOR_RCV;
  335. if (sever & einj->uncor_status) {
  336. rperr->root_status |= PCI_ERR_ROOT_FATAL_RCV;
  337. if (!(rperr->root_status & PCI_ERR_ROOT_UNCOR_RCV))
  338. rperr->root_status |= PCI_ERR_ROOT_FIRST_FATAL;
  339. } else
  340. rperr->root_status |= PCI_ERR_ROOT_NONFATAL_RCV;
  341. rperr->root_status |= PCI_ERR_ROOT_UNCOR_RCV;
  342. rperr->source_id &= 0x0000ffff;
  343. rperr->source_id |= ((einj->bus << 8) | devfn) << 16;
  344. }
  345. spin_unlock_irqrestore(&inject_lock, flags);
  346. ret = pci_bus_set_aer_ops(dev->bus);
  347. if (ret)
  348. goto out_put;
  349. ret = pci_bus_set_aer_ops(rpdev->bus);
  350. if (ret)
  351. goto out_put;
  352. if (find_aer_device(rpdev, &edev))
  353. aer_irq(-1, edev);
  354. else
  355. ret = -EINVAL;
  356. out_put:
  357. kfree(err_alloc);
  358. kfree(rperr_alloc);
  359. pci_dev_put(dev);
  360. return ret;
  361. }
  362. static ssize_t aer_inject_write(struct file *filp, const char __user *ubuf,
  363. size_t usize, loff_t *off)
  364. {
  365. struct aer_error_inj einj;
  366. int ret;
  367. if (!capable(CAP_SYS_ADMIN))
  368. return -EPERM;
  369. if (usize != sizeof(struct aer_error_inj))
  370. return -EINVAL;
  371. if (copy_from_user(&einj, ubuf, usize))
  372. return -EFAULT;
  373. ret = aer_inject(&einj);
  374. return ret ? ret : usize;
  375. }
  376. static const struct file_operations aer_inject_fops = {
  377. .write = aer_inject_write,
  378. .owner = THIS_MODULE,
  379. };
  380. static struct miscdevice aer_inject_device = {
  381. .minor = MISC_DYNAMIC_MINOR,
  382. .name = "aer_inject",
  383. .fops = &aer_inject_fops,
  384. };
  385. static int __init aer_inject_init(void)
  386. {
  387. return misc_register(&aer_inject_device);
  388. }
  389. static void __exit aer_inject_exit(void)
  390. {
  391. struct aer_error *err, *err_next;
  392. unsigned long flags;
  393. struct pci_bus_ops *bus_ops;
  394. misc_deregister(&aer_inject_device);
  395. while ((bus_ops = pci_bus_ops_pop())) {
  396. pci_bus_set_ops(bus_ops->bus, bus_ops->ops);
  397. kfree(bus_ops);
  398. }
  399. spin_lock_irqsave(&inject_lock, flags);
  400. list_for_each_entry_safe(err, err_next, &pci_bus_ops_list, list) {
  401. list_del(&err->list);
  402. kfree(err);
  403. }
  404. spin_unlock_irqrestore(&inject_lock, flags);
  405. }
  406. module_init(aer_inject_init);
  407. module_exit(aer_inject_exit);
  408. MODULE_DESCRIPTION("PCIE AER software error injector");
  409. MODULE_LICENSE("GPL");