iwl-core.c 91 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258
  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *****************************************************************************/
  28. #include <linux/kernel.h>
  29. #include <linux/module.h>
  30. #include <linux/etherdevice.h>
  31. #include <net/mac80211.h>
  32. #include "iwl-eeprom.h"
  33. #include "iwl-dev.h" /* FIXME: remove */
  34. #include "iwl-debug.h"
  35. #include "iwl-core.h"
  36. #include "iwl-io.h"
  37. #include "iwl-power.h"
  38. #include "iwl-sta.h"
  39. #include "iwl-helpers.h"
  40. MODULE_DESCRIPTION("iwl core");
  41. MODULE_VERSION(IWLWIFI_VERSION);
  42. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  43. MODULE_LICENSE("GPL");
  44. #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
  45. [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
  46. IWL_RATE_SISO_##s##M_PLCP, \
  47. IWL_RATE_MIMO2_##s##M_PLCP,\
  48. IWL_RATE_MIMO3_##s##M_PLCP,\
  49. IWL_RATE_##r##M_IEEE, \
  50. IWL_RATE_##ip##M_INDEX, \
  51. IWL_RATE_##in##M_INDEX, \
  52. IWL_RATE_##rp##M_INDEX, \
  53. IWL_RATE_##rn##M_INDEX, \
  54. IWL_RATE_##pp##M_INDEX, \
  55. IWL_RATE_##np##M_INDEX }
  56. u32 iwl_debug_level;
  57. EXPORT_SYMBOL(iwl_debug_level);
  58. static irqreturn_t iwl_isr(int irq, void *data);
  59. /*
  60. * Parameter order:
  61. * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  62. *
  63. * If there isn't a valid next or previous rate then INV is used which
  64. * maps to IWL_RATE_INVALID
  65. *
  66. */
  67. const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
  68. IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
  69. IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
  70. IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
  71. IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
  72. IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
  73. IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
  74. IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
  75. IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
  76. IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
  77. IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
  78. IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
  79. IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  80. IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  81. /* FIXME:RS: ^^ should be INV (legacy) */
  82. };
  83. EXPORT_SYMBOL(iwl_rates);
  84. /**
  85. * translate ucode response to mac80211 tx status control values
  86. */
  87. void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  88. struct ieee80211_tx_info *info)
  89. {
  90. struct ieee80211_tx_rate *r = &info->control.rates[0];
  91. info->antenna_sel_tx =
  92. ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
  93. if (rate_n_flags & RATE_MCS_HT_MSK)
  94. r->flags |= IEEE80211_TX_RC_MCS;
  95. if (rate_n_flags & RATE_MCS_GF_MSK)
  96. r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
  97. if (rate_n_flags & RATE_MCS_HT40_MSK)
  98. r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
  99. if (rate_n_flags & RATE_MCS_DUP_MSK)
  100. r->flags |= IEEE80211_TX_RC_DUP_DATA;
  101. if (rate_n_flags & RATE_MCS_SGI_MSK)
  102. r->flags |= IEEE80211_TX_RC_SHORT_GI;
  103. r->idx = iwl_hwrate_to_mac80211_idx(rate_n_flags, info->band);
  104. }
  105. EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
  106. int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
  107. {
  108. int idx = 0;
  109. /* HT rate format */
  110. if (rate_n_flags & RATE_MCS_HT_MSK) {
  111. idx = (rate_n_flags & 0xff);
  112. if (idx >= IWL_RATE_MIMO3_6M_PLCP)
  113. idx = idx - IWL_RATE_MIMO3_6M_PLCP;
  114. else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
  115. idx = idx - IWL_RATE_MIMO2_6M_PLCP;
  116. idx += IWL_FIRST_OFDM_RATE;
  117. /* skip 9M not supported in ht*/
  118. if (idx >= IWL_RATE_9M_INDEX)
  119. idx += 1;
  120. if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
  121. return idx;
  122. /* legacy rate format, search for match in table */
  123. } else {
  124. for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
  125. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  126. return idx;
  127. }
  128. return -1;
  129. }
  130. EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
  131. int iwl_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
  132. {
  133. int idx = 0;
  134. int band_offset = 0;
  135. /* HT rate format: mac80211 wants an MCS number, which is just LSB */
  136. if (rate_n_flags & RATE_MCS_HT_MSK) {
  137. idx = (rate_n_flags & 0xff);
  138. return idx;
  139. /* Legacy rate format, search for match in table */
  140. } else {
  141. if (band == IEEE80211_BAND_5GHZ)
  142. band_offset = IWL_FIRST_OFDM_RATE;
  143. for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
  144. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  145. return idx - band_offset;
  146. }
  147. return -1;
  148. }
  149. u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
  150. {
  151. int i;
  152. u8 ind = ant;
  153. for (i = 0; i < RATE_ANT_NUM - 1; i++) {
  154. ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
  155. if (priv->hw_params.valid_tx_ant & BIT(ind))
  156. return ind;
  157. }
  158. return ant;
  159. }
  160. const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  161. EXPORT_SYMBOL(iwl_bcast_addr);
  162. /* This function both allocates and initializes hw and priv. */
  163. struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
  164. struct ieee80211_ops *hw_ops)
  165. {
  166. struct iwl_priv *priv;
  167. /* mac80211 allocates memory for this device instance, including
  168. * space for this driver's private structure */
  169. struct ieee80211_hw *hw =
  170. ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
  171. if (hw == NULL) {
  172. printk(KERN_ERR "%s: Can not allocate network device\n",
  173. cfg->name);
  174. goto out;
  175. }
  176. priv = hw->priv;
  177. priv->hw = hw;
  178. out:
  179. return hw;
  180. }
  181. EXPORT_SYMBOL(iwl_alloc_all);
  182. void iwl_hw_detect(struct iwl_priv *priv)
  183. {
  184. priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
  185. priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
  186. pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
  187. }
  188. EXPORT_SYMBOL(iwl_hw_detect);
  189. int iwl_hw_nic_init(struct iwl_priv *priv)
  190. {
  191. unsigned long flags;
  192. struct iwl_rx_queue *rxq = &priv->rxq;
  193. int ret;
  194. /* nic_init */
  195. spin_lock_irqsave(&priv->lock, flags);
  196. priv->cfg->ops->lib->apm_ops.init(priv);
  197. iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
  198. spin_unlock_irqrestore(&priv->lock, flags);
  199. ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
  200. priv->cfg->ops->lib->apm_ops.config(priv);
  201. /* Allocate the RX queue, or reset if it is already allocated */
  202. if (!rxq->bd) {
  203. ret = iwl_rx_queue_alloc(priv);
  204. if (ret) {
  205. IWL_ERR(priv, "Unable to initialize Rx queue\n");
  206. return -ENOMEM;
  207. }
  208. } else
  209. iwl_rx_queue_reset(priv, rxq);
  210. iwl_rx_replenish(priv);
  211. iwl_rx_init(priv, rxq);
  212. spin_lock_irqsave(&priv->lock, flags);
  213. rxq->need_update = 1;
  214. iwl_rx_queue_update_write_ptr(priv, rxq);
  215. spin_unlock_irqrestore(&priv->lock, flags);
  216. /* Allocate and init all Tx and Command queues */
  217. ret = iwl_txq_ctx_reset(priv);
  218. if (ret)
  219. return ret;
  220. set_bit(STATUS_INIT, &priv->status);
  221. return 0;
  222. }
  223. EXPORT_SYMBOL(iwl_hw_nic_init);
  224. /*
  225. * QoS support
  226. */
  227. void iwl_activate_qos(struct iwl_priv *priv, u8 force)
  228. {
  229. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  230. return;
  231. priv->qos_data.def_qos_parm.qos_flags = 0;
  232. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  233. !priv->qos_data.qos_cap.q_AP.txop_request)
  234. priv->qos_data.def_qos_parm.qos_flags |=
  235. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  236. if (priv->qos_data.qos_active)
  237. priv->qos_data.def_qos_parm.qos_flags |=
  238. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  239. if (priv->current_ht_config.is_ht)
  240. priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
  241. if (force || iwl_is_associated(priv)) {
  242. IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
  243. priv->qos_data.qos_active,
  244. priv->qos_data.def_qos_parm.qos_flags);
  245. iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
  246. sizeof(struct iwl_qosparam_cmd),
  247. &priv->qos_data.def_qos_parm, NULL);
  248. }
  249. }
  250. EXPORT_SYMBOL(iwl_activate_qos);
  251. /*
  252. * AC CWmin CW max AIFSN TXOP Limit TXOP Limit
  253. * (802.11b) (802.11a/g)
  254. * AC_BK 15 1023 7 0 0
  255. * AC_BE 15 1023 3 0 0
  256. * AC_VI 7 15 2 6.016ms 3.008ms
  257. * AC_VO 3 7 2 3.264ms 1.504ms
  258. */
  259. void iwl_reset_qos(struct iwl_priv *priv)
  260. {
  261. u16 cw_min = 15;
  262. u16 cw_max = 1023;
  263. u8 aifs = 2;
  264. bool is_legacy = false;
  265. unsigned long flags;
  266. int i;
  267. spin_lock_irqsave(&priv->lock, flags);
  268. /* QoS always active in AP and ADHOC mode
  269. * In STA mode wait for association
  270. */
  271. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  272. priv->iw_mode == NL80211_IFTYPE_AP)
  273. priv->qos_data.qos_active = 1;
  274. else
  275. priv->qos_data.qos_active = 0;
  276. /* check for legacy mode */
  277. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  278. (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
  279. (priv->iw_mode == NL80211_IFTYPE_STATION &&
  280. (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
  281. cw_min = 31;
  282. is_legacy = 1;
  283. }
  284. if (priv->qos_data.qos_active)
  285. aifs = 3;
  286. /* AC_BE */
  287. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  288. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  289. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  290. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  291. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  292. if (priv->qos_data.qos_active) {
  293. /* AC_BK */
  294. i = 1;
  295. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  296. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  297. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  298. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  299. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  300. /* AC_VI */
  301. i = 2;
  302. priv->qos_data.def_qos_parm.ac[i].cw_min =
  303. cpu_to_le16((cw_min + 1) / 2 - 1);
  304. priv->qos_data.def_qos_parm.ac[i].cw_max =
  305. cpu_to_le16(cw_min);
  306. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  307. if (is_legacy)
  308. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  309. cpu_to_le16(6016);
  310. else
  311. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  312. cpu_to_le16(3008);
  313. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  314. /* AC_VO */
  315. i = 3;
  316. priv->qos_data.def_qos_parm.ac[i].cw_min =
  317. cpu_to_le16((cw_min + 1) / 4 - 1);
  318. priv->qos_data.def_qos_parm.ac[i].cw_max =
  319. cpu_to_le16((cw_min + 1) / 2 - 1);
  320. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  321. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  322. if (is_legacy)
  323. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  324. cpu_to_le16(3264);
  325. else
  326. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  327. cpu_to_le16(1504);
  328. } else {
  329. for (i = 1; i < 4; i++) {
  330. priv->qos_data.def_qos_parm.ac[i].cw_min =
  331. cpu_to_le16(cw_min);
  332. priv->qos_data.def_qos_parm.ac[i].cw_max =
  333. cpu_to_le16(cw_max);
  334. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  335. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  336. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  337. }
  338. }
  339. IWL_DEBUG_QOS(priv, "set QoS to default \n");
  340. spin_unlock_irqrestore(&priv->lock, flags);
  341. }
  342. EXPORT_SYMBOL(iwl_reset_qos);
  343. #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
  344. #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
  345. static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
  346. struct ieee80211_sta_ht_cap *ht_info,
  347. enum ieee80211_band band)
  348. {
  349. u16 max_bit_rate = 0;
  350. u8 rx_chains_num = priv->hw_params.rx_chains_num;
  351. u8 tx_chains_num = priv->hw_params.tx_chains_num;
  352. ht_info->cap = 0;
  353. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  354. ht_info->ht_supported = true;
  355. if (priv->cfg->ht_greenfield_support)
  356. ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
  357. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  358. ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
  359. (WLAN_HT_CAP_SM_PS_DISABLED << 2));
  360. max_bit_rate = MAX_BIT_RATE_20_MHZ;
  361. if (priv->hw_params.ht40_channel & BIT(band)) {
  362. ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  363. ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
  364. ht_info->mcs.rx_mask[4] = 0x01;
  365. max_bit_rate = MAX_BIT_RATE_40_MHZ;
  366. }
  367. if (priv->cfg->mod_params->amsdu_size_8K)
  368. ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  369. ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  370. ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
  371. ht_info->mcs.rx_mask[0] = 0xFF;
  372. if (rx_chains_num >= 2)
  373. ht_info->mcs.rx_mask[1] = 0xFF;
  374. if (rx_chains_num >= 3)
  375. ht_info->mcs.rx_mask[2] = 0xFF;
  376. /* Highest supported Rx data rate */
  377. max_bit_rate *= rx_chains_num;
  378. WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
  379. ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
  380. /* Tx MCS capabilities */
  381. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  382. if (tx_chains_num != rx_chains_num) {
  383. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  384. ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
  385. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  386. }
  387. }
  388. static void iwlcore_init_hw_rates(struct iwl_priv *priv,
  389. struct ieee80211_rate *rates)
  390. {
  391. int i;
  392. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  393. rates[i].bitrate = iwl_rates[i].ieee * 5;
  394. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  395. rates[i].hw_value_short = i;
  396. rates[i].flags = 0;
  397. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  398. /*
  399. * If CCK != 1M then set short preamble rate flag.
  400. */
  401. rates[i].flags |=
  402. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  403. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  404. }
  405. }
  406. }
  407. /**
  408. * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
  409. */
  410. int iwlcore_init_geos(struct iwl_priv *priv)
  411. {
  412. struct iwl_channel_info *ch;
  413. struct ieee80211_supported_band *sband;
  414. struct ieee80211_channel *channels;
  415. struct ieee80211_channel *geo_ch;
  416. struct ieee80211_rate *rates;
  417. int i = 0;
  418. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  419. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  420. IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
  421. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  422. return 0;
  423. }
  424. channels = kzalloc(sizeof(struct ieee80211_channel) *
  425. priv->channel_count, GFP_KERNEL);
  426. if (!channels)
  427. return -ENOMEM;
  428. rates = kzalloc((sizeof(struct ieee80211_rate) * IWL_RATE_COUNT_LEGACY),
  429. GFP_KERNEL);
  430. if (!rates) {
  431. kfree(channels);
  432. return -ENOMEM;
  433. }
  434. /* 5.2GHz channels start after the 2.4GHz channels */
  435. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  436. sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
  437. /* just OFDM */
  438. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  439. sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE;
  440. if (priv->cfg->sku & IWL_SKU_N)
  441. iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
  442. IEEE80211_BAND_5GHZ);
  443. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  444. sband->channels = channels;
  445. /* OFDM & CCK */
  446. sband->bitrates = rates;
  447. sband->n_bitrates = IWL_RATE_COUNT_LEGACY;
  448. if (priv->cfg->sku & IWL_SKU_N)
  449. iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
  450. IEEE80211_BAND_2GHZ);
  451. priv->ieee_channels = channels;
  452. priv->ieee_rates = rates;
  453. for (i = 0; i < priv->channel_count; i++) {
  454. ch = &priv->channel_info[i];
  455. /* FIXME: might be removed if scan is OK */
  456. if (!is_channel_valid(ch))
  457. continue;
  458. if (is_channel_a_band(ch))
  459. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  460. else
  461. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  462. geo_ch = &sband->channels[sband->n_channels++];
  463. geo_ch->center_freq =
  464. ieee80211_channel_to_frequency(ch->channel);
  465. geo_ch->max_power = ch->max_power_avg;
  466. geo_ch->max_antenna_gain = 0xff;
  467. geo_ch->hw_value = ch->channel;
  468. if (is_channel_valid(ch)) {
  469. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  470. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  471. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  472. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  473. if (ch->flags & EEPROM_CHANNEL_RADAR)
  474. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  475. geo_ch->flags |= ch->ht40_extension_channel;
  476. if (ch->max_power_avg > priv->tx_power_device_lmt)
  477. priv->tx_power_device_lmt = ch->max_power_avg;
  478. } else {
  479. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  480. }
  481. IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
  482. ch->channel, geo_ch->center_freq,
  483. is_channel_a_band(ch) ? "5.2" : "2.4",
  484. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  485. "restricted" : "valid",
  486. geo_ch->flags);
  487. }
  488. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  489. priv->cfg->sku & IWL_SKU_A) {
  490. IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
  491. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  492. priv->pci_dev->device,
  493. priv->pci_dev->subsystem_device);
  494. priv->cfg->sku &= ~IWL_SKU_A;
  495. }
  496. IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  497. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  498. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  499. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  500. return 0;
  501. }
  502. EXPORT_SYMBOL(iwlcore_init_geos);
  503. /*
  504. * iwlcore_free_geos - undo allocations in iwlcore_init_geos
  505. */
  506. void iwlcore_free_geos(struct iwl_priv *priv)
  507. {
  508. kfree(priv->ieee_channels);
  509. kfree(priv->ieee_rates);
  510. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  511. }
  512. EXPORT_SYMBOL(iwlcore_free_geos);
  513. static bool is_single_rx_stream(struct iwl_priv *priv)
  514. {
  515. return !priv->current_ht_config.is_ht ||
  516. ((priv->current_ht_config.mcs.rx_mask[1] == 0) &&
  517. (priv->current_ht_config.mcs.rx_mask[2] == 0));
  518. }
  519. static u8 iwl_is_channel_extension(struct iwl_priv *priv,
  520. enum ieee80211_band band,
  521. u16 channel, u8 extension_chan_offset)
  522. {
  523. const struct iwl_channel_info *ch_info;
  524. ch_info = iwl_get_channel_info(priv, band, channel);
  525. if (!is_channel_valid(ch_info))
  526. return 0;
  527. if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
  528. return !(ch_info->ht40_extension_channel &
  529. IEEE80211_CHAN_NO_HT40PLUS);
  530. else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
  531. return !(ch_info->ht40_extension_channel &
  532. IEEE80211_CHAN_NO_HT40MINUS);
  533. return 0;
  534. }
  535. u8 iwl_is_ht40_tx_allowed(struct iwl_priv *priv,
  536. struct ieee80211_sta_ht_cap *sta_ht_inf)
  537. {
  538. struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
  539. if ((!iwl_ht_conf->is_ht) ||
  540. (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ))
  541. return 0;
  542. /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
  543. * the bit will not set if it is pure 40MHz case
  544. */
  545. if (sta_ht_inf) {
  546. if (!sta_ht_inf->ht_supported)
  547. return 0;
  548. }
  549. #ifdef CONFIG_IWLWIFI_DEBUG
  550. if (priv->disable_ht40)
  551. return 0;
  552. #endif
  553. return iwl_is_channel_extension(priv, priv->band,
  554. le16_to_cpu(priv->staging_rxon.channel),
  555. iwl_ht_conf->extension_chan_offset);
  556. }
  557. EXPORT_SYMBOL(iwl_is_ht40_tx_allowed);
  558. static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
  559. {
  560. u16 new_val = 0;
  561. u16 beacon_factor = 0;
  562. beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
  563. new_val = beacon_val / beacon_factor;
  564. if (!new_val)
  565. new_val = max_beacon_val;
  566. return new_val;
  567. }
  568. void iwl_setup_rxon_timing(struct iwl_priv *priv)
  569. {
  570. u64 tsf;
  571. s32 interval_tm, rem;
  572. unsigned long flags;
  573. struct ieee80211_conf *conf = NULL;
  574. u16 beacon_int;
  575. conf = ieee80211_get_hw_conf(priv->hw);
  576. spin_lock_irqsave(&priv->lock, flags);
  577. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  578. priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
  579. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  580. beacon_int = priv->beacon_int;
  581. priv->rxon_timing.atim_window = 0;
  582. } else {
  583. beacon_int = priv->vif->bss_conf.beacon_int;
  584. /* TODO: we need to get atim_window from upper stack
  585. * for now we set to 0 */
  586. priv->rxon_timing.atim_window = 0;
  587. }
  588. beacon_int = iwl_adjust_beacon_interval(beacon_int,
  589. priv->hw_params.max_beacon_itrvl * 1024);
  590. priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
  591. tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
  592. interval_tm = beacon_int * 1024;
  593. rem = do_div(tsf, interval_tm);
  594. priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
  595. spin_unlock_irqrestore(&priv->lock, flags);
  596. IWL_DEBUG_ASSOC(priv,
  597. "beacon interval %d beacon timer %d beacon tim %d\n",
  598. le16_to_cpu(priv->rxon_timing.beacon_interval),
  599. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  600. le16_to_cpu(priv->rxon_timing.atim_window));
  601. }
  602. EXPORT_SYMBOL(iwl_setup_rxon_timing);
  603. void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
  604. {
  605. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  606. if (hw_decrypt)
  607. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  608. else
  609. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  610. }
  611. EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
  612. /**
  613. * iwl_check_rxon_cmd - validate RXON structure is valid
  614. *
  615. * NOTE: This is really only useful during development and can eventually
  616. * be #ifdef'd out once the driver is stable and folks aren't actively
  617. * making changes
  618. */
  619. int iwl_check_rxon_cmd(struct iwl_priv *priv)
  620. {
  621. int error = 0;
  622. int counter = 1;
  623. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  624. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  625. error |= le32_to_cpu(rxon->flags &
  626. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  627. RXON_FLG_RADAR_DETECT_MSK));
  628. if (error)
  629. IWL_WARN(priv, "check 24G fields %d | %d\n",
  630. counter++, error);
  631. } else {
  632. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  633. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  634. if (error)
  635. IWL_WARN(priv, "check 52 fields %d | %d\n",
  636. counter++, error);
  637. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  638. if (error)
  639. IWL_WARN(priv, "check 52 CCK %d | %d\n",
  640. counter++, error);
  641. }
  642. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  643. if (error)
  644. IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
  645. /* make sure basic rates 6Mbps and 1Mbps are supported */
  646. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  647. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  648. if (error)
  649. IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
  650. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  651. if (error)
  652. IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
  653. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  654. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  655. if (error)
  656. IWL_WARN(priv, "check CCK and short slot %d | %d\n",
  657. counter++, error);
  658. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  659. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  660. if (error)
  661. IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
  662. counter++, error);
  663. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  664. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  665. if (error)
  666. IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
  667. counter++, error);
  668. if (error)
  669. IWL_WARN(priv, "Tuning to channel %d\n",
  670. le16_to_cpu(rxon->channel));
  671. if (error) {
  672. IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
  673. return -1;
  674. }
  675. return 0;
  676. }
  677. EXPORT_SYMBOL(iwl_check_rxon_cmd);
  678. /**
  679. * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  680. * @priv: staging_rxon is compared to active_rxon
  681. *
  682. * If the RXON structure is changing enough to require a new tune,
  683. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  684. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  685. */
  686. int iwl_full_rxon_required(struct iwl_priv *priv)
  687. {
  688. /* These items are only settable from the full RXON command */
  689. if (!(iwl_is_associated(priv)) ||
  690. compare_ether_addr(priv->staging_rxon.bssid_addr,
  691. priv->active_rxon.bssid_addr) ||
  692. compare_ether_addr(priv->staging_rxon.node_addr,
  693. priv->active_rxon.node_addr) ||
  694. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  695. priv->active_rxon.wlap_bssid_addr) ||
  696. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  697. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  698. (priv->staging_rxon.air_propagation !=
  699. priv->active_rxon.air_propagation) ||
  700. (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
  701. priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
  702. (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
  703. priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
  704. (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates !=
  705. priv->active_rxon.ofdm_ht_triple_stream_basic_rates) ||
  706. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  707. return 1;
  708. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  709. * be updated with the RXON_ASSOC command -- however only some
  710. * flag transitions are allowed using RXON_ASSOC */
  711. /* Check if we are not switching bands */
  712. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  713. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  714. return 1;
  715. /* Check if we are switching association toggle */
  716. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  717. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  718. return 1;
  719. return 0;
  720. }
  721. EXPORT_SYMBOL(iwl_full_rxon_required);
  722. u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
  723. {
  724. int i;
  725. int rate_mask;
  726. /* Set rate mask*/
  727. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  728. rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
  729. else
  730. rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
  731. /* Find lowest valid rate */
  732. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  733. i = iwl_rates[i].next_ieee) {
  734. if (rate_mask & (1 << i))
  735. return iwl_rates[i].plcp;
  736. }
  737. /* No valid rate was found. Assign the lowest one */
  738. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  739. return IWL_RATE_1M_PLCP;
  740. else
  741. return IWL_RATE_6M_PLCP;
  742. }
  743. EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
  744. void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
  745. {
  746. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  747. if (!ht_info->is_ht) {
  748. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
  749. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
  750. RXON_FLG_HT40_PROT_MSK |
  751. RXON_FLG_HT_PROT_MSK);
  752. return;
  753. }
  754. /* FIXME: if the definition of ht_protection changed, the "translation"
  755. * will be needed for rxon->flags
  756. */
  757. rxon->flags |= cpu_to_le32(ht_info->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS);
  758. /* Set up channel bandwidth:
  759. * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
  760. /* clear the HT channel mode before set the mode */
  761. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
  762. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  763. if (iwl_is_ht40_tx_allowed(priv, NULL)) {
  764. /* pure ht40 */
  765. if (ht_info->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
  766. rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
  767. /* Note: control channel is opposite of extension channel */
  768. switch (ht_info->extension_chan_offset) {
  769. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  770. rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  771. break;
  772. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  773. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  774. break;
  775. }
  776. } else {
  777. /* Note: control channel is opposite of extension channel */
  778. switch (ht_info->extension_chan_offset) {
  779. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  780. rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  781. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  782. break;
  783. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  784. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  785. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  786. break;
  787. case IEEE80211_HT_PARAM_CHA_SEC_NONE:
  788. default:
  789. /* channel location only valid if in Mixed mode */
  790. IWL_ERR(priv, "invalid extension channel offset\n");
  791. break;
  792. }
  793. }
  794. } else {
  795. rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
  796. }
  797. if (priv->cfg->ops->hcmd->set_rxon_chain)
  798. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  799. IWL_DEBUG_ASSOC(priv, "supported HT rate 0x%X 0x%X 0x%X "
  800. "rxon flags 0x%X operation mode :0x%X "
  801. "extension channel offset 0x%x\n",
  802. ht_info->mcs.rx_mask[0],
  803. ht_info->mcs.rx_mask[1],
  804. ht_info->mcs.rx_mask[2],
  805. le32_to_cpu(rxon->flags), ht_info->ht_protection,
  806. ht_info->extension_chan_offset);
  807. return;
  808. }
  809. EXPORT_SYMBOL(iwl_set_rxon_ht);
  810. #define IWL_NUM_RX_CHAINS_MULTIPLE 3
  811. #define IWL_NUM_RX_CHAINS_SINGLE 2
  812. #define IWL_NUM_IDLE_CHAINS_DUAL 2
  813. #define IWL_NUM_IDLE_CHAINS_SINGLE 1
  814. /* Determine how many receiver/antenna chains to use.
  815. * More provides better reception via diversity. Fewer saves power.
  816. * MIMO (dual stream) requires at least 2, but works better with 3.
  817. * This does not determine *which* chains to use, just how many.
  818. */
  819. static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
  820. {
  821. bool is_single = is_single_rx_stream(priv);
  822. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  823. /* # of Rx chains to use when expecting MIMO. */
  824. if (is_single || (!is_cam && (priv->current_ht_config.sm_ps ==
  825. WLAN_HT_CAP_SM_PS_STATIC)))
  826. return IWL_NUM_RX_CHAINS_SINGLE;
  827. else
  828. return IWL_NUM_RX_CHAINS_MULTIPLE;
  829. }
  830. static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
  831. {
  832. int idle_cnt;
  833. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  834. /* # Rx chains when idling and maybe trying to save power */
  835. switch (priv->current_ht_config.sm_ps) {
  836. case WLAN_HT_CAP_SM_PS_STATIC:
  837. case WLAN_HT_CAP_SM_PS_DYNAMIC:
  838. idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
  839. IWL_NUM_IDLE_CHAINS_SINGLE;
  840. break;
  841. case WLAN_HT_CAP_SM_PS_DISABLED:
  842. idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE;
  843. break;
  844. case WLAN_HT_CAP_SM_PS_INVALID:
  845. default:
  846. IWL_ERR(priv, "invalid mimo ps mode %d\n",
  847. priv->current_ht_config.sm_ps);
  848. WARN_ON(1);
  849. idle_cnt = -1;
  850. break;
  851. }
  852. return idle_cnt;
  853. }
  854. /* up to 4 chains */
  855. static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
  856. {
  857. u8 res;
  858. res = (chain_bitmap & BIT(0)) >> 0;
  859. res += (chain_bitmap & BIT(1)) >> 1;
  860. res += (chain_bitmap & BIT(2)) >> 2;
  861. res += (chain_bitmap & BIT(4)) >> 4;
  862. return res;
  863. }
  864. /**
  865. * iwl_is_monitor_mode - Determine if interface in monitor mode
  866. *
  867. * priv->iw_mode is set in add_interface, but add_interface is
  868. * never called for monitor mode. The only way mac80211 informs us about
  869. * monitor mode is through configuring filters (call to configure_filter).
  870. */
  871. bool iwl_is_monitor_mode(struct iwl_priv *priv)
  872. {
  873. return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
  874. }
  875. EXPORT_SYMBOL(iwl_is_monitor_mode);
  876. /**
  877. * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
  878. *
  879. * Selects how many and which Rx receivers/antennas/chains to use.
  880. * This should not be used for scan command ... it puts data in wrong place.
  881. */
  882. void iwl_set_rxon_chain(struct iwl_priv *priv)
  883. {
  884. bool is_single = is_single_rx_stream(priv);
  885. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  886. u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
  887. u32 active_chains;
  888. u16 rx_chain;
  889. /* Tell uCode which antennas are actually connected.
  890. * Before first association, we assume all antennas are connected.
  891. * Just after first association, iwl_chain_noise_calibration()
  892. * checks which antennas actually *are* connected. */
  893. if (priv->chain_noise_data.active_chains)
  894. active_chains = priv->chain_noise_data.active_chains;
  895. else
  896. active_chains = priv->hw_params.valid_rx_ant;
  897. rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
  898. /* How many receivers should we use? */
  899. active_rx_cnt = iwl_get_active_rx_chain_count(priv);
  900. idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
  901. /* correct rx chain count according hw settings
  902. * and chain noise calibration
  903. */
  904. valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
  905. if (valid_rx_cnt < active_rx_cnt)
  906. active_rx_cnt = valid_rx_cnt;
  907. if (valid_rx_cnt < idle_rx_cnt)
  908. idle_rx_cnt = valid_rx_cnt;
  909. rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
  910. rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
  911. /* copied from 'iwl_bg_request_scan()' */
  912. /* Force use of chains B and C (0x6) for Rx for 4965
  913. * Avoid A (0x1) because of its off-channel reception on A-band.
  914. * MIMO is not used here, but value is required */
  915. if (iwl_is_monitor_mode(priv) &&
  916. !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
  917. ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
  918. rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS;
  919. rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS;
  920. rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
  921. rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
  922. }
  923. priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
  924. if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
  925. priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
  926. else
  927. priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
  928. IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
  929. priv->staging_rxon.rx_chain,
  930. active_rx_cnt, idle_rx_cnt);
  931. WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
  932. active_rx_cnt < idle_rx_cnt);
  933. }
  934. EXPORT_SYMBOL(iwl_set_rxon_chain);
  935. /**
  936. * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
  937. * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
  938. * @channel: Any channel valid for the requested phymode
  939. * In addition to setting the staging RXON, priv->phymode is also set.
  940. *
  941. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  942. * in the staging RXON flag structure based on the phymode
  943. */
  944. int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
  945. {
  946. enum ieee80211_band band = ch->band;
  947. u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
  948. if (!iwl_get_channel_info(priv, band, channel)) {
  949. IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
  950. channel, band);
  951. return -EINVAL;
  952. }
  953. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  954. (priv->band == band))
  955. return 0;
  956. priv->staging_rxon.channel = cpu_to_le16(channel);
  957. if (band == IEEE80211_BAND_5GHZ)
  958. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  959. else
  960. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  961. priv->band = band;
  962. IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
  963. return 0;
  964. }
  965. EXPORT_SYMBOL(iwl_set_rxon_channel);
  966. void iwl_set_flags_for_band(struct iwl_priv *priv,
  967. enum ieee80211_band band)
  968. {
  969. if (band == IEEE80211_BAND_5GHZ) {
  970. priv->staging_rxon.flags &=
  971. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  972. | RXON_FLG_CCK_MSK);
  973. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  974. } else {
  975. /* Copied from iwl_post_associate() */
  976. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  977. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  978. else
  979. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  980. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  981. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  982. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  983. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  984. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  985. }
  986. }
  987. /*
  988. * initialize rxon structure with default values from eeprom
  989. */
  990. void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
  991. {
  992. const struct iwl_channel_info *ch_info;
  993. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  994. switch (mode) {
  995. case NL80211_IFTYPE_AP:
  996. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  997. break;
  998. case NL80211_IFTYPE_STATION:
  999. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1000. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1001. break;
  1002. case NL80211_IFTYPE_ADHOC:
  1003. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1004. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1005. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1006. RXON_FILTER_ACCEPT_GRP_MSK;
  1007. break;
  1008. default:
  1009. IWL_ERR(priv, "Unsupported interface type %d\n", mode);
  1010. break;
  1011. }
  1012. #if 0
  1013. /* TODO: Figure out when short_preamble would be set and cache from
  1014. * that */
  1015. if (!hw_to_local(priv->hw)->short_preamble)
  1016. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1017. else
  1018. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1019. #endif
  1020. ch_info = iwl_get_channel_info(priv, priv->band,
  1021. le16_to_cpu(priv->active_rxon.channel));
  1022. if (!ch_info)
  1023. ch_info = &priv->channel_info[0];
  1024. /*
  1025. * in some case A channels are all non IBSS
  1026. * in this case force B/G channel
  1027. */
  1028. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
  1029. !(is_channel_ibss(ch_info)))
  1030. ch_info = &priv->channel_info[0];
  1031. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  1032. priv->band = ch_info->band;
  1033. iwl_set_flags_for_band(priv, priv->band);
  1034. priv->staging_rxon.ofdm_basic_rates =
  1035. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1036. priv->staging_rxon.cck_basic_rates =
  1037. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1038. /* clear both MIX and PURE40 mode flag */
  1039. priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
  1040. RXON_FLG_CHANNEL_MODE_PURE_40);
  1041. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1042. memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
  1043. priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
  1044. priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
  1045. priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff;
  1046. }
  1047. EXPORT_SYMBOL(iwl_connection_init_rx_config);
  1048. static void iwl_set_rate(struct iwl_priv *priv)
  1049. {
  1050. const struct ieee80211_supported_band *hw = NULL;
  1051. struct ieee80211_rate *rate;
  1052. int i;
  1053. hw = iwl_get_hw_mode(priv, priv->band);
  1054. if (!hw) {
  1055. IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
  1056. return;
  1057. }
  1058. priv->active_rate = 0;
  1059. priv->active_rate_basic = 0;
  1060. for (i = 0; i < hw->n_bitrates; i++) {
  1061. rate = &(hw->bitrates[i]);
  1062. if (rate->hw_value < IWL_RATE_COUNT_LEGACY)
  1063. priv->active_rate |= (1 << rate->hw_value);
  1064. }
  1065. IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
  1066. priv->active_rate, priv->active_rate_basic);
  1067. /*
  1068. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  1069. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  1070. * OFDM
  1071. */
  1072. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  1073. priv->staging_rxon.cck_basic_rates =
  1074. ((priv->active_rate_basic &
  1075. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  1076. else
  1077. priv->staging_rxon.cck_basic_rates =
  1078. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1079. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  1080. priv->staging_rxon.ofdm_basic_rates =
  1081. ((priv->active_rate_basic &
  1082. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  1083. IWL_FIRST_OFDM_RATE) & 0xFF;
  1084. else
  1085. priv->staging_rxon.ofdm_basic_rates =
  1086. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1087. }
  1088. void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  1089. {
  1090. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1091. struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
  1092. struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
  1093. IWL_DEBUG_11H(priv, "CSA notif: channel %d, status %d\n",
  1094. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  1095. rxon->channel = csa->channel;
  1096. priv->staging_rxon.channel = csa->channel;
  1097. }
  1098. EXPORT_SYMBOL(iwl_rx_csa);
  1099. #ifdef CONFIG_IWLWIFI_DEBUG
  1100. static void iwl_print_rx_config_cmd(struct iwl_priv *priv)
  1101. {
  1102. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  1103. IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
  1104. iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  1105. IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  1106. IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  1107. IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
  1108. le32_to_cpu(rxon->filter_flags));
  1109. IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
  1110. IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
  1111. rxon->ofdm_basic_rates);
  1112. IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  1113. IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
  1114. IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  1115. IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  1116. }
  1117. static const char *desc_lookup_text[] = {
  1118. "OK",
  1119. "FAIL",
  1120. "BAD_PARAM",
  1121. "BAD_CHECKSUM",
  1122. "NMI_INTERRUPT_WDG",
  1123. "SYSASSERT",
  1124. "FATAL_ERROR",
  1125. "BAD_COMMAND",
  1126. "HW_ERROR_TUNE_LOCK",
  1127. "HW_ERROR_TEMPERATURE",
  1128. "ILLEGAL_CHAN_FREQ",
  1129. "VCC_NOT_STABLE",
  1130. "FH_ERROR",
  1131. "NMI_INTERRUPT_HOST",
  1132. "NMI_INTERRUPT_ACTION_PT",
  1133. "NMI_INTERRUPT_UNKNOWN",
  1134. "UCODE_VERSION_MISMATCH",
  1135. "HW_ERROR_ABS_LOCK",
  1136. "HW_ERROR_CAL_LOCK_FAIL",
  1137. "NMI_INTERRUPT_INST_ACTION_PT",
  1138. "NMI_INTERRUPT_DATA_ACTION_PT",
  1139. "NMI_TRM_HW_ER",
  1140. "NMI_INTERRUPT_TRM",
  1141. "NMI_INTERRUPT_BREAK_POINT"
  1142. "DEBUG_0",
  1143. "DEBUG_1",
  1144. "DEBUG_2",
  1145. "DEBUG_3",
  1146. "UNKNOWN"
  1147. };
  1148. static const char *desc_lookup(int i)
  1149. {
  1150. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1151. if (i < 0 || i > max)
  1152. i = max;
  1153. return desc_lookup_text[i];
  1154. }
  1155. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1156. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1157. static void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1158. {
  1159. u32 data2, line;
  1160. u32 desc, time, count, base, data1;
  1161. u32 blink1, blink2, ilink1, ilink2;
  1162. if (priv->ucode_type == UCODE_INIT)
  1163. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1164. else
  1165. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1166. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1167. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  1168. return;
  1169. }
  1170. count = iwl_read_targ_mem(priv, base);
  1171. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1172. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1173. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1174. priv->status, count);
  1175. }
  1176. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1177. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1178. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1179. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1180. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1181. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1182. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1183. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1184. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1185. IWL_ERR(priv, "Desc Time "
  1186. "data1 data2 line\n");
  1187. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1188. desc_lookup(desc), desc, time, data1, data2, line);
  1189. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1190. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1191. ilink1, ilink2);
  1192. }
  1193. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1194. /**
  1195. * iwl_print_event_log - Dump error event log to syslog
  1196. *
  1197. */
  1198. static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1199. u32 num_events, u32 mode)
  1200. {
  1201. u32 i;
  1202. u32 base; /* SRAM byte address of event log header */
  1203. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1204. u32 ptr; /* SRAM byte address of log data */
  1205. u32 ev, time, data; /* event log data */
  1206. if (num_events == 0)
  1207. return;
  1208. if (priv->ucode_type == UCODE_INIT)
  1209. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1210. else
  1211. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1212. if (mode == 0)
  1213. event_size = 2 * sizeof(u32);
  1214. else
  1215. event_size = 3 * sizeof(u32);
  1216. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1217. /* "time" is actually "data" for mode 0 (no timestamp).
  1218. * place event id # at far right for easier visual parsing. */
  1219. for (i = 0; i < num_events; i++) {
  1220. ev = iwl_read_targ_mem(priv, ptr);
  1221. ptr += sizeof(u32);
  1222. time = iwl_read_targ_mem(priv, ptr);
  1223. ptr += sizeof(u32);
  1224. if (mode == 0) {
  1225. /* data, ev */
  1226. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
  1227. } else {
  1228. data = iwl_read_targ_mem(priv, ptr);
  1229. ptr += sizeof(u32);
  1230. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1231. time, data, ev);
  1232. }
  1233. }
  1234. }
  1235. void iwl_dump_nic_event_log(struct iwl_priv *priv)
  1236. {
  1237. u32 base; /* SRAM byte address of event log header */
  1238. u32 capacity; /* event log capacity in # entries */
  1239. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1240. u32 num_wraps; /* # times uCode wrapped to top of log */
  1241. u32 next_entry; /* index of next entry to be written by uCode */
  1242. u32 size; /* # entries that we'll print */
  1243. if (priv->ucode_type == UCODE_INIT)
  1244. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1245. else
  1246. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1247. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1248. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  1249. return;
  1250. }
  1251. /* event log header */
  1252. capacity = iwl_read_targ_mem(priv, base);
  1253. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1254. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1255. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1256. size = num_wraps ? capacity : next_entry;
  1257. /* bail out if nothing in log */
  1258. if (size == 0) {
  1259. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1260. return;
  1261. }
  1262. IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
  1263. size, num_wraps);
  1264. /* if uCode has wrapped back to top of log, start at the oldest entry,
  1265. * i.e the next one that uCode would fill. */
  1266. if (num_wraps)
  1267. iwl_print_event_log(priv, next_entry,
  1268. capacity - next_entry, mode);
  1269. /* (then/else) start at top of log */
  1270. iwl_print_event_log(priv, 0, next_entry, mode);
  1271. }
  1272. #endif
  1273. /**
  1274. * iwl_irq_handle_error - called for HW or SW error interrupt from card
  1275. */
  1276. void iwl_irq_handle_error(struct iwl_priv *priv)
  1277. {
  1278. /* Set the FW error flag -- cleared on iwl_down */
  1279. set_bit(STATUS_FW_ERROR, &priv->status);
  1280. /* Cancel currently queued command. */
  1281. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  1282. #ifdef CONFIG_IWLWIFI_DEBUG
  1283. if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) {
  1284. iwl_dump_nic_error_log(priv);
  1285. iwl_dump_nic_event_log(priv);
  1286. iwl_print_rx_config_cmd(priv);
  1287. }
  1288. #endif
  1289. wake_up_interruptible(&priv->wait_command_queue);
  1290. /* Keep the restart process from trying to send host
  1291. * commands by clearing the INIT status bit */
  1292. clear_bit(STATUS_READY, &priv->status);
  1293. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1294. IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
  1295. "Restarting adapter due to uCode error.\n");
  1296. if (priv->cfg->mod_params->restart_fw)
  1297. queue_work(priv->workqueue, &priv->restart);
  1298. }
  1299. }
  1300. EXPORT_SYMBOL(iwl_irq_handle_error);
  1301. void iwl_configure_filter(struct ieee80211_hw *hw,
  1302. unsigned int changed_flags,
  1303. unsigned int *total_flags,
  1304. u64 multicast)
  1305. {
  1306. struct iwl_priv *priv = hw->priv;
  1307. __le32 *filter_flags = &priv->staging_rxon.filter_flags;
  1308. IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
  1309. changed_flags, *total_flags);
  1310. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  1311. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  1312. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  1313. else
  1314. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  1315. }
  1316. if (changed_flags & FIF_ALLMULTI) {
  1317. if (*total_flags & FIF_ALLMULTI)
  1318. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  1319. else
  1320. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  1321. }
  1322. if (changed_flags & FIF_CONTROL) {
  1323. if (*total_flags & FIF_CONTROL)
  1324. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  1325. else
  1326. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  1327. }
  1328. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  1329. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  1330. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  1331. else
  1332. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  1333. }
  1334. /* We avoid iwl_commit_rxon here to commit the new filter flags
  1335. * since mac80211 will call ieee80211_hw_config immediately.
  1336. * (mc_list is not supported at this time). Otherwise, we need to
  1337. * queue a background iwl_commit_rxon work.
  1338. */
  1339. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  1340. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  1341. }
  1342. EXPORT_SYMBOL(iwl_configure_filter);
  1343. int iwl_setup_mac(struct iwl_priv *priv)
  1344. {
  1345. int ret;
  1346. struct ieee80211_hw *hw = priv->hw;
  1347. hw->rate_control_algorithm = "iwl-agn-rs";
  1348. /* Tell mac80211 our characteristics */
  1349. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  1350. IEEE80211_HW_NOISE_DBM |
  1351. IEEE80211_HW_AMPDU_AGGREGATION |
  1352. IEEE80211_HW_SPECTRUM_MGMT;
  1353. if (!priv->cfg->broken_powersave)
  1354. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  1355. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  1356. hw->wiphy->interface_modes =
  1357. BIT(NL80211_IFTYPE_STATION) |
  1358. BIT(NL80211_IFTYPE_ADHOC);
  1359. hw->wiphy->custom_regulatory = true;
  1360. /* Firmware does not support this */
  1361. hw->wiphy->disable_beacon_hints = true;
  1362. /*
  1363. * For now, disable PS by default because it affects
  1364. * RX performance significantly.
  1365. */
  1366. hw->wiphy->ps_default = false;
  1367. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  1368. /* we create the 802.11 header and a zero-length SSID element */
  1369. hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
  1370. /* Default value; 4 EDCA QOS priorities */
  1371. hw->queues = 4;
  1372. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  1373. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  1374. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  1375. &priv->bands[IEEE80211_BAND_2GHZ];
  1376. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  1377. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  1378. &priv->bands[IEEE80211_BAND_5GHZ];
  1379. ret = ieee80211_register_hw(priv->hw);
  1380. if (ret) {
  1381. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  1382. return ret;
  1383. }
  1384. priv->mac80211_registered = 1;
  1385. return 0;
  1386. }
  1387. EXPORT_SYMBOL(iwl_setup_mac);
  1388. int iwl_set_hw_params(struct iwl_priv *priv)
  1389. {
  1390. priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  1391. priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  1392. if (priv->cfg->mod_params->amsdu_size_8K)
  1393. priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
  1394. else
  1395. priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
  1396. priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
  1397. priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
  1398. if (priv->cfg->mod_params->disable_11n)
  1399. priv->cfg->sku &= ~IWL_SKU_N;
  1400. /* Device-specific setup */
  1401. return priv->cfg->ops->lib->set_hw_params(priv);
  1402. }
  1403. EXPORT_SYMBOL(iwl_set_hw_params);
  1404. int iwl_init_drv(struct iwl_priv *priv)
  1405. {
  1406. int ret;
  1407. priv->ibss_beacon = NULL;
  1408. spin_lock_init(&priv->lock);
  1409. spin_lock_init(&priv->sta_lock);
  1410. spin_lock_init(&priv->hcmd_lock);
  1411. INIT_LIST_HEAD(&priv->free_frames);
  1412. mutex_init(&priv->mutex);
  1413. /* Clear the driver's (not device's) station table */
  1414. iwl_clear_stations_table(priv);
  1415. priv->data_retry_limit = -1;
  1416. priv->ieee_channels = NULL;
  1417. priv->ieee_rates = NULL;
  1418. priv->band = IEEE80211_BAND_2GHZ;
  1419. priv->iw_mode = NL80211_IFTYPE_STATION;
  1420. priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
  1421. /* Choose which receivers/antennas to use */
  1422. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1423. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1424. iwl_init_scan_params(priv);
  1425. iwl_reset_qos(priv);
  1426. priv->qos_data.qos_active = 0;
  1427. priv->qos_data.qos_cap.val = 0;
  1428. priv->rates_mask = IWL_RATES_MASK;
  1429. /* Set the tx_power_user_lmt to the lowest power level
  1430. * this value will get overwritten by channel max power avg
  1431. * from eeprom */
  1432. priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
  1433. ret = iwl_init_channel_map(priv);
  1434. if (ret) {
  1435. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  1436. goto err;
  1437. }
  1438. ret = iwlcore_init_geos(priv);
  1439. if (ret) {
  1440. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  1441. goto err_free_channel_map;
  1442. }
  1443. iwlcore_init_hw_rates(priv, priv->ieee_rates);
  1444. return 0;
  1445. err_free_channel_map:
  1446. iwl_free_channel_map(priv);
  1447. err:
  1448. return ret;
  1449. }
  1450. EXPORT_SYMBOL(iwl_init_drv);
  1451. int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
  1452. {
  1453. int ret = 0;
  1454. s8 prev_tx_power = priv->tx_power_user_lmt;
  1455. if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
  1456. IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
  1457. tx_power,
  1458. IWL_TX_POWER_TARGET_POWER_MIN);
  1459. return -EINVAL;
  1460. }
  1461. if (tx_power > priv->tx_power_device_lmt) {
  1462. IWL_WARN(priv,
  1463. "Requested user TXPOWER %d above upper limit %d.\n",
  1464. tx_power, priv->tx_power_device_lmt);
  1465. return -EINVAL;
  1466. }
  1467. if (priv->tx_power_user_lmt != tx_power)
  1468. force = true;
  1469. /* if nic is not up don't send command */
  1470. if (iwl_is_ready_rf(priv)) {
  1471. priv->tx_power_user_lmt = tx_power;
  1472. if (force && priv->cfg->ops->lib->send_tx_power)
  1473. ret = priv->cfg->ops->lib->send_tx_power(priv);
  1474. else if (!priv->cfg->ops->lib->send_tx_power)
  1475. ret = -EOPNOTSUPP;
  1476. /*
  1477. * if fail to set tx_power, restore the orig. tx power
  1478. */
  1479. if (ret)
  1480. priv->tx_power_user_lmt = prev_tx_power;
  1481. }
  1482. /*
  1483. * Even this is an async host command, the command
  1484. * will always report success from uCode
  1485. * So once driver can placing the command into the queue
  1486. * successfully, driver can use priv->tx_power_user_lmt
  1487. * to reflect the current tx power
  1488. */
  1489. return ret;
  1490. }
  1491. EXPORT_SYMBOL(iwl_set_tx_power);
  1492. void iwl_uninit_drv(struct iwl_priv *priv)
  1493. {
  1494. iwl_calib_free_results(priv);
  1495. iwlcore_free_geos(priv);
  1496. iwl_free_channel_map(priv);
  1497. kfree(priv->scan);
  1498. }
  1499. EXPORT_SYMBOL(iwl_uninit_drv);
  1500. #define ICT_COUNT (PAGE_SIZE/sizeof(u32))
  1501. /* Free dram table */
  1502. void iwl_free_isr_ict(struct iwl_priv *priv)
  1503. {
  1504. if (priv->ict_tbl_vir) {
  1505. pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) +
  1506. PAGE_SIZE, priv->ict_tbl_vir,
  1507. priv->ict_tbl_dma);
  1508. priv->ict_tbl_vir = NULL;
  1509. }
  1510. }
  1511. EXPORT_SYMBOL(iwl_free_isr_ict);
  1512. /* allocate dram shared table it is a PAGE_SIZE aligned
  1513. * also reset all data related to ICT table interrupt.
  1514. */
  1515. int iwl_alloc_isr_ict(struct iwl_priv *priv)
  1516. {
  1517. if (priv->cfg->use_isr_legacy)
  1518. return 0;
  1519. /* allocate shrared data table */
  1520. priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) *
  1521. ICT_COUNT) + PAGE_SIZE,
  1522. &priv->ict_tbl_dma);
  1523. if (!priv->ict_tbl_vir)
  1524. return -ENOMEM;
  1525. /* align table to PAGE_SIZE boundry */
  1526. priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
  1527. IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
  1528. (unsigned long long)priv->ict_tbl_dma,
  1529. (unsigned long long)priv->aligned_ict_tbl_dma,
  1530. (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
  1531. priv->ict_tbl = priv->ict_tbl_vir +
  1532. (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma);
  1533. IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
  1534. priv->ict_tbl, priv->ict_tbl_vir,
  1535. (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
  1536. /* reset table and index to all 0 */
  1537. memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
  1538. priv->ict_index = 0;
  1539. /* add periodic RX interrupt */
  1540. priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
  1541. return 0;
  1542. }
  1543. EXPORT_SYMBOL(iwl_alloc_isr_ict);
  1544. /* Device is going up inform it about using ICT interrupt table,
  1545. * also we need to tell the driver to start using ICT interrupt.
  1546. */
  1547. int iwl_reset_ict(struct iwl_priv *priv)
  1548. {
  1549. u32 val;
  1550. unsigned long flags;
  1551. if (!priv->ict_tbl_vir)
  1552. return 0;
  1553. spin_lock_irqsave(&priv->lock, flags);
  1554. iwl_disable_interrupts(priv);
  1555. memset(&priv->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
  1556. val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
  1557. val |= CSR_DRAM_INT_TBL_ENABLE;
  1558. val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
  1559. IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
  1560. "aligned dma address %Lx\n",
  1561. val, (unsigned long long)priv->aligned_ict_tbl_dma);
  1562. iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
  1563. priv->use_ict = true;
  1564. priv->ict_index = 0;
  1565. iwl_write32(priv, CSR_INT, priv->inta_mask);
  1566. iwl_enable_interrupts(priv);
  1567. spin_unlock_irqrestore(&priv->lock, flags);
  1568. return 0;
  1569. }
  1570. EXPORT_SYMBOL(iwl_reset_ict);
  1571. /* Device is going down disable ict interrupt usage */
  1572. void iwl_disable_ict(struct iwl_priv *priv)
  1573. {
  1574. unsigned long flags;
  1575. spin_lock_irqsave(&priv->lock, flags);
  1576. priv->use_ict = false;
  1577. spin_unlock_irqrestore(&priv->lock, flags);
  1578. }
  1579. EXPORT_SYMBOL(iwl_disable_ict);
  1580. /* interrupt handler using ict table, with this interrupt driver will
  1581. * stop using INTA register to get device's interrupt, reading this register
  1582. * is expensive, device will write interrupts in ICT dram table, increment
  1583. * index then will fire interrupt to driver, driver will OR all ICT table
  1584. * entries from current index up to table entry with 0 value. the result is
  1585. * the interrupt we need to service, driver will set the entries back to 0 and
  1586. * set index.
  1587. */
  1588. irqreturn_t iwl_isr_ict(int irq, void *data)
  1589. {
  1590. struct iwl_priv *priv = data;
  1591. u32 inta, inta_mask;
  1592. u32 val = 0;
  1593. if (!priv)
  1594. return IRQ_NONE;
  1595. /* dram interrupt table not set yet,
  1596. * use legacy interrupt.
  1597. */
  1598. if (!priv->use_ict)
  1599. return iwl_isr(irq, data);
  1600. spin_lock(&priv->lock);
  1601. /* Disable (but don't clear!) interrupts here to avoid
  1602. * back-to-back ISRs and sporadic interrupts from our NIC.
  1603. * If we have something to service, the tasklet will re-enable ints.
  1604. * If we *don't* have something, we'll re-enable before leaving here.
  1605. */
  1606. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1607. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1608. /* Ignore interrupt if there's nothing in NIC to service.
  1609. * This may be due to IRQ shared with another device,
  1610. * or due to sporadic interrupts thrown from our NIC. */
  1611. if (!priv->ict_tbl[priv->ict_index]) {
  1612. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
  1613. goto none;
  1614. }
  1615. /* read all entries that not 0 start with ict_index */
  1616. while (priv->ict_tbl[priv->ict_index]) {
  1617. val |= le32_to_cpu(priv->ict_tbl[priv->ict_index]);
  1618. IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
  1619. priv->ict_index,
  1620. le32_to_cpu(priv->ict_tbl[priv->ict_index]));
  1621. priv->ict_tbl[priv->ict_index] = 0;
  1622. priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
  1623. ICT_COUNT);
  1624. }
  1625. /* We should not get this value, just ignore it. */
  1626. if (val == 0xffffffff)
  1627. val = 0;
  1628. inta = (0xff & val) | ((0xff00 & val) << 16);
  1629. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
  1630. inta, inta_mask, val);
  1631. inta &= priv->inta_mask;
  1632. priv->inta |= inta;
  1633. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1634. if (likely(inta))
  1635. tasklet_schedule(&priv->irq_tasklet);
  1636. else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) {
  1637. /* Allow interrupt if was disabled by this handler and
  1638. * no tasklet was schedules, We should not enable interrupt,
  1639. * tasklet will enable it.
  1640. */
  1641. iwl_enable_interrupts(priv);
  1642. }
  1643. spin_unlock(&priv->lock);
  1644. return IRQ_HANDLED;
  1645. none:
  1646. /* re-enable interrupts here since we don't have anything to service.
  1647. * only Re-enable if disabled by irq.
  1648. */
  1649. if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1650. iwl_enable_interrupts(priv);
  1651. spin_unlock(&priv->lock);
  1652. return IRQ_NONE;
  1653. }
  1654. EXPORT_SYMBOL(iwl_isr_ict);
  1655. static irqreturn_t iwl_isr(int irq, void *data)
  1656. {
  1657. struct iwl_priv *priv = data;
  1658. u32 inta, inta_mask;
  1659. #ifdef CONFIG_IWLWIFI_DEBUG
  1660. u32 inta_fh;
  1661. #endif
  1662. if (!priv)
  1663. return IRQ_NONE;
  1664. spin_lock(&priv->lock);
  1665. /* Disable (but don't clear!) interrupts here to avoid
  1666. * back-to-back ISRs and sporadic interrupts from our NIC.
  1667. * If we have something to service, the tasklet will re-enable ints.
  1668. * If we *don't* have something, we'll re-enable before leaving here. */
  1669. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1670. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1671. /* Discover which interrupts are active/pending */
  1672. inta = iwl_read32(priv, CSR_INT);
  1673. /* Ignore interrupt if there's nothing in NIC to service.
  1674. * This may be due to IRQ shared with another device,
  1675. * or due to sporadic interrupts thrown from our NIC. */
  1676. if (!inta) {
  1677. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
  1678. goto none;
  1679. }
  1680. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  1681. /* Hardware disappeared. It might have already raised
  1682. * an interrupt */
  1683. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  1684. goto unplugged;
  1685. }
  1686. #ifdef CONFIG_IWLWIFI_DEBUG
  1687. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1688. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1689. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
  1690. "fh 0x%08x\n", inta, inta_mask, inta_fh);
  1691. }
  1692. #endif
  1693. priv->inta |= inta;
  1694. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1695. if (likely(inta))
  1696. tasklet_schedule(&priv->irq_tasklet);
  1697. else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1698. iwl_enable_interrupts(priv);
  1699. unplugged:
  1700. spin_unlock(&priv->lock);
  1701. return IRQ_HANDLED;
  1702. none:
  1703. /* re-enable interrupts here since we don't have anything to service. */
  1704. /* only Re-enable if diabled by irq and no schedules tasklet. */
  1705. if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1706. iwl_enable_interrupts(priv);
  1707. spin_unlock(&priv->lock);
  1708. return IRQ_NONE;
  1709. }
  1710. irqreturn_t iwl_isr_legacy(int irq, void *data)
  1711. {
  1712. struct iwl_priv *priv = data;
  1713. u32 inta, inta_mask;
  1714. u32 inta_fh;
  1715. if (!priv)
  1716. return IRQ_NONE;
  1717. spin_lock(&priv->lock);
  1718. /* Disable (but don't clear!) interrupts here to avoid
  1719. * back-to-back ISRs and sporadic interrupts from our NIC.
  1720. * If we have something to service, the tasklet will re-enable ints.
  1721. * If we *don't* have something, we'll re-enable before leaving here. */
  1722. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1723. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1724. /* Discover which interrupts are active/pending */
  1725. inta = iwl_read32(priv, CSR_INT);
  1726. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1727. /* Ignore interrupt if there's nothing in NIC to service.
  1728. * This may be due to IRQ shared with another device,
  1729. * or due to sporadic interrupts thrown from our NIC. */
  1730. if (!inta && !inta_fh) {
  1731. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
  1732. goto none;
  1733. }
  1734. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  1735. /* Hardware disappeared. It might have already raised
  1736. * an interrupt */
  1737. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  1738. goto unplugged;
  1739. }
  1740. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  1741. inta, inta_mask, inta_fh);
  1742. inta &= ~CSR_INT_BIT_SCD;
  1743. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1744. if (likely(inta || inta_fh))
  1745. tasklet_schedule(&priv->irq_tasklet);
  1746. unplugged:
  1747. spin_unlock(&priv->lock);
  1748. return IRQ_HANDLED;
  1749. none:
  1750. /* re-enable interrupts here since we don't have anything to service. */
  1751. /* only Re-enable if diabled by irq */
  1752. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1753. iwl_enable_interrupts(priv);
  1754. spin_unlock(&priv->lock);
  1755. return IRQ_NONE;
  1756. }
  1757. EXPORT_SYMBOL(iwl_isr_legacy);
  1758. int iwl_send_bt_config(struct iwl_priv *priv)
  1759. {
  1760. struct iwl_bt_cmd bt_cmd = {
  1761. .flags = 3,
  1762. .lead_time = 0xAA,
  1763. .max_kill = 1,
  1764. .kill_ack_mask = 0,
  1765. .kill_cts_mask = 0,
  1766. };
  1767. return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  1768. sizeof(struct iwl_bt_cmd), &bt_cmd);
  1769. }
  1770. EXPORT_SYMBOL(iwl_send_bt_config);
  1771. int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
  1772. {
  1773. u32 stat_flags = 0;
  1774. struct iwl_host_cmd cmd = {
  1775. .id = REPLY_STATISTICS_CMD,
  1776. .flags = flags,
  1777. .len = sizeof(stat_flags),
  1778. .data = (u8 *) &stat_flags,
  1779. };
  1780. return iwl_send_cmd(priv, &cmd);
  1781. }
  1782. EXPORT_SYMBOL(iwl_send_statistics_request);
  1783. /**
  1784. * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
  1785. * using sample data 100 bytes apart. If these sample points are good,
  1786. * it's a pretty good bet that everything between them is good, too.
  1787. */
  1788. static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  1789. {
  1790. u32 val;
  1791. int ret = 0;
  1792. u32 errcnt = 0;
  1793. u32 i;
  1794. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1795. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  1796. /* read data comes through single port, auto-incr addr */
  1797. /* NOTE: Use the debugless read so we don't flood kernel log
  1798. * if IWL_DL_IO is set */
  1799. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1800. i + IWL49_RTC_INST_LOWER_BOUND);
  1801. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1802. if (val != le32_to_cpu(*image)) {
  1803. ret = -EIO;
  1804. errcnt++;
  1805. if (errcnt >= 3)
  1806. break;
  1807. }
  1808. }
  1809. return ret;
  1810. }
  1811. /**
  1812. * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
  1813. * looking at all data.
  1814. */
  1815. static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
  1816. u32 len)
  1817. {
  1818. u32 val;
  1819. u32 save_len = len;
  1820. int ret = 0;
  1821. u32 errcnt;
  1822. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1823. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1824. IWL49_RTC_INST_LOWER_BOUND);
  1825. errcnt = 0;
  1826. for (; len > 0; len -= sizeof(u32), image++) {
  1827. /* read data comes through single port, auto-incr addr */
  1828. /* NOTE: Use the debugless read so we don't flood kernel log
  1829. * if IWL_DL_IO is set */
  1830. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1831. if (val != le32_to_cpu(*image)) {
  1832. IWL_ERR(priv, "uCode INST section is invalid at "
  1833. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1834. save_len - len, val, le32_to_cpu(*image));
  1835. ret = -EIO;
  1836. errcnt++;
  1837. if (errcnt >= 20)
  1838. break;
  1839. }
  1840. }
  1841. if (!errcnt)
  1842. IWL_DEBUG_INFO(priv,
  1843. "ucode image in INSTRUCTION memory is good\n");
  1844. return ret;
  1845. }
  1846. /**
  1847. * iwl_verify_ucode - determine which instruction image is in SRAM,
  1848. * and verify its contents
  1849. */
  1850. int iwl_verify_ucode(struct iwl_priv *priv)
  1851. {
  1852. __le32 *image;
  1853. u32 len;
  1854. int ret;
  1855. /* Try bootstrap */
  1856. image = (__le32 *)priv->ucode_boot.v_addr;
  1857. len = priv->ucode_boot.len;
  1858. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1859. if (!ret) {
  1860. IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
  1861. return 0;
  1862. }
  1863. /* Try initialize */
  1864. image = (__le32 *)priv->ucode_init.v_addr;
  1865. len = priv->ucode_init.len;
  1866. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1867. if (!ret) {
  1868. IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
  1869. return 0;
  1870. }
  1871. /* Try runtime/protocol */
  1872. image = (__le32 *)priv->ucode_code.v_addr;
  1873. len = priv->ucode_code.len;
  1874. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1875. if (!ret) {
  1876. IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
  1877. return 0;
  1878. }
  1879. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  1880. /* Since nothing seems to match, show first several data entries in
  1881. * instruction SRAM, so maybe visual inspection will give a clue.
  1882. * Selection of bootstrap image (vs. other images) is arbitrary. */
  1883. image = (__le32 *)priv->ucode_boot.v_addr;
  1884. len = priv->ucode_boot.len;
  1885. ret = iwl_verify_inst_full(priv, image, len);
  1886. return ret;
  1887. }
  1888. EXPORT_SYMBOL(iwl_verify_ucode);
  1889. void iwl_rf_kill_ct_config(struct iwl_priv *priv)
  1890. {
  1891. struct iwl_ct_kill_config cmd;
  1892. struct iwl_ct_kill_throttling_config adv_cmd;
  1893. unsigned long flags;
  1894. int ret = 0;
  1895. spin_lock_irqsave(&priv->lock, flags);
  1896. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1897. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  1898. spin_unlock_irqrestore(&priv->lock, flags);
  1899. priv->thermal_throttle.ct_kill_toggle = false;
  1900. switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
  1901. case CSR_HW_REV_TYPE_1000:
  1902. case CSR_HW_REV_TYPE_6x00:
  1903. case CSR_HW_REV_TYPE_6x50:
  1904. adv_cmd.critical_temperature_enter =
  1905. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1906. adv_cmd.critical_temperature_exit =
  1907. cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
  1908. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1909. sizeof(adv_cmd), &adv_cmd);
  1910. if (ret)
  1911. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1912. else
  1913. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  1914. "succeeded, "
  1915. "critical temperature enter is %d,"
  1916. "exit is %d\n",
  1917. priv->hw_params.ct_kill_threshold,
  1918. priv->hw_params.ct_kill_exit_threshold);
  1919. break;
  1920. default:
  1921. cmd.critical_temperature_R =
  1922. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1923. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1924. sizeof(cmd), &cmd);
  1925. if (ret)
  1926. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1927. else
  1928. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  1929. "succeeded, "
  1930. "critical temperature is %d\n",
  1931. priv->hw_params.ct_kill_threshold);
  1932. break;
  1933. }
  1934. }
  1935. EXPORT_SYMBOL(iwl_rf_kill_ct_config);
  1936. /*
  1937. * CARD_STATE_CMD
  1938. *
  1939. * Use: Sets the device's internal card state to enable, disable, or halt
  1940. *
  1941. * When in the 'enable' state the card operates as normal.
  1942. * When in the 'disable' state, the card enters into a low power mode.
  1943. * When in the 'halt' state, the card is shut down and must be fully
  1944. * restarted to come back on.
  1945. */
  1946. int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
  1947. {
  1948. struct iwl_host_cmd cmd = {
  1949. .id = REPLY_CARD_STATE_CMD,
  1950. .len = sizeof(u32),
  1951. .data = &flags,
  1952. .flags = meta_flag,
  1953. };
  1954. return iwl_send_cmd(priv, &cmd);
  1955. }
  1956. void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
  1957. struct iwl_rx_mem_buffer *rxb)
  1958. {
  1959. #ifdef CONFIG_IWLWIFI_DEBUG
  1960. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1961. struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
  1962. IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
  1963. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  1964. #endif
  1965. }
  1966. EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
  1967. void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
  1968. struct iwl_rx_mem_buffer *rxb)
  1969. {
  1970. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1971. u32 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  1972. IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
  1973. "notification for %s:\n", len,
  1974. get_cmd_string(pkt->hdr.cmd));
  1975. iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, len);
  1976. }
  1977. EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
  1978. void iwl_rx_reply_error(struct iwl_priv *priv,
  1979. struct iwl_rx_mem_buffer *rxb)
  1980. {
  1981. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1982. IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
  1983. "seq 0x%04X ser 0x%08X\n",
  1984. le32_to_cpu(pkt->u.err_resp.error_type),
  1985. get_cmd_string(pkt->u.err_resp.cmd_id),
  1986. pkt->u.err_resp.cmd_id,
  1987. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  1988. le32_to_cpu(pkt->u.err_resp.error_info));
  1989. }
  1990. EXPORT_SYMBOL(iwl_rx_reply_error);
  1991. void iwl_clear_isr_stats(struct iwl_priv *priv)
  1992. {
  1993. memset(&priv->isr_stats, 0, sizeof(priv->isr_stats));
  1994. }
  1995. int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1996. const struct ieee80211_tx_queue_params *params)
  1997. {
  1998. struct iwl_priv *priv = hw->priv;
  1999. unsigned long flags;
  2000. int q;
  2001. IWL_DEBUG_MAC80211(priv, "enter\n");
  2002. if (!iwl_is_ready_rf(priv)) {
  2003. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  2004. return -EIO;
  2005. }
  2006. if (queue >= AC_NUM) {
  2007. IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
  2008. return 0;
  2009. }
  2010. q = AC_NUM - 1 - queue;
  2011. spin_lock_irqsave(&priv->lock, flags);
  2012. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  2013. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  2014. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  2015. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  2016. cpu_to_le16((params->txop * 32));
  2017. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  2018. priv->qos_data.qos_active = 1;
  2019. if (priv->iw_mode == NL80211_IFTYPE_AP)
  2020. iwl_activate_qos(priv, 1);
  2021. else if (priv->assoc_id && iwl_is_associated(priv))
  2022. iwl_activate_qos(priv, 0);
  2023. spin_unlock_irqrestore(&priv->lock, flags);
  2024. IWL_DEBUG_MAC80211(priv, "leave\n");
  2025. return 0;
  2026. }
  2027. EXPORT_SYMBOL(iwl_mac_conf_tx);
  2028. static void iwl_ht_conf(struct iwl_priv *priv,
  2029. struct ieee80211_bss_conf *bss_conf)
  2030. {
  2031. struct ieee80211_sta_ht_cap *ht_conf;
  2032. struct iwl_ht_info *iwl_conf = &priv->current_ht_config;
  2033. struct ieee80211_sta *sta;
  2034. IWL_DEBUG_MAC80211(priv, "enter: \n");
  2035. if (!iwl_conf->is_ht)
  2036. return;
  2037. /*
  2038. * It is totally wrong to base global information on something
  2039. * that is valid only when associated, alas, this driver works
  2040. * that way and I don't know how to fix it.
  2041. */
  2042. rcu_read_lock();
  2043. sta = ieee80211_find_sta(priv->hw, priv->bssid);
  2044. if (!sta) {
  2045. rcu_read_unlock();
  2046. return;
  2047. }
  2048. ht_conf = &sta->ht_cap;
  2049. iwl_conf->sm_ps = (u8)((ht_conf->cap & IEEE80211_HT_CAP_SM_PS) >> 2);
  2050. memcpy(&iwl_conf->mcs, &ht_conf->mcs, 16);
  2051. iwl_conf->ht_protection =
  2052. bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
  2053. iwl_conf->non_GF_STA_present =
  2054. !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
  2055. rcu_read_unlock();
  2056. IWL_DEBUG_MAC80211(priv, "leave\n");
  2057. }
  2058. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  2059. void iwl_bss_info_changed(struct ieee80211_hw *hw,
  2060. struct ieee80211_vif *vif,
  2061. struct ieee80211_bss_conf *bss_conf,
  2062. u32 changes)
  2063. {
  2064. struct iwl_priv *priv = hw->priv;
  2065. int ret;
  2066. IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
  2067. if (!iwl_is_alive(priv))
  2068. return;
  2069. mutex_lock(&priv->mutex);
  2070. if (changes & BSS_CHANGED_BEACON &&
  2071. priv->iw_mode == NL80211_IFTYPE_AP) {
  2072. dev_kfree_skb(priv->ibss_beacon);
  2073. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  2074. }
  2075. if (changes & BSS_CHANGED_BEACON_INT) {
  2076. priv->beacon_int = bss_conf->beacon_int;
  2077. /* TODO: in AP mode, do something to make this take effect */
  2078. }
  2079. if (changes & BSS_CHANGED_BSSID) {
  2080. IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
  2081. /*
  2082. * If there is currently a HW scan going on in the
  2083. * background then we need to cancel it else the RXON
  2084. * below/in post_associate will fail.
  2085. */
  2086. if (iwl_scan_cancel_timeout(priv, 100)) {
  2087. IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
  2088. IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
  2089. mutex_unlock(&priv->mutex);
  2090. return;
  2091. }
  2092. /* mac80211 only sets assoc when in STATION mode */
  2093. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  2094. bss_conf->assoc) {
  2095. memcpy(priv->staging_rxon.bssid_addr,
  2096. bss_conf->bssid, ETH_ALEN);
  2097. /* currently needed in a few places */
  2098. memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
  2099. } else {
  2100. priv->staging_rxon.filter_flags &=
  2101. ~RXON_FILTER_ASSOC_MSK;
  2102. }
  2103. }
  2104. /*
  2105. * This needs to be after setting the BSSID in case
  2106. * mac80211 decides to do both changes at once because
  2107. * it will invoke post_associate.
  2108. */
  2109. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  2110. changes & BSS_CHANGED_BEACON) {
  2111. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  2112. if (beacon)
  2113. iwl_mac_beacon_update(hw, beacon);
  2114. }
  2115. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  2116. IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
  2117. bss_conf->use_short_preamble);
  2118. if (bss_conf->use_short_preamble)
  2119. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2120. else
  2121. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2122. }
  2123. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  2124. IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
  2125. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  2126. priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  2127. else
  2128. priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  2129. }
  2130. if (changes & BSS_CHANGED_BASIC_RATES) {
  2131. /* XXX use this information
  2132. *
  2133. * To do that, remove code from iwl_set_rate() and put something
  2134. * like this here:
  2135. *
  2136. if (A-band)
  2137. priv->staging_rxon.ofdm_basic_rates =
  2138. bss_conf->basic_rates;
  2139. else
  2140. priv->staging_rxon.ofdm_basic_rates =
  2141. bss_conf->basic_rates >> 4;
  2142. priv->staging_rxon.cck_basic_rates =
  2143. bss_conf->basic_rates & 0xF;
  2144. */
  2145. }
  2146. if (changes & BSS_CHANGED_HT) {
  2147. iwl_ht_conf(priv, bss_conf);
  2148. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2149. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2150. }
  2151. if (changes & BSS_CHANGED_ASSOC) {
  2152. IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
  2153. if (bss_conf->assoc) {
  2154. priv->assoc_id = bss_conf->aid;
  2155. priv->beacon_int = bss_conf->beacon_int;
  2156. priv->timestamp = bss_conf->timestamp;
  2157. priv->assoc_capability = bss_conf->assoc_capability;
  2158. /*
  2159. * We have just associated, don't start scan too early
  2160. * leave time for EAPOL exchange to complete.
  2161. *
  2162. * XXX: do this in mac80211
  2163. */
  2164. priv->next_scan_jiffies = jiffies +
  2165. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  2166. if (!iwl_is_rfkill(priv))
  2167. priv->cfg->ops->lib->post_associate(priv);
  2168. } else
  2169. priv->assoc_id = 0;
  2170. }
  2171. if (changes && iwl_is_associated(priv) && priv->assoc_id) {
  2172. IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
  2173. changes);
  2174. ret = iwl_send_rxon_assoc(priv);
  2175. if (!ret) {
  2176. /* Sync active_rxon with latest change. */
  2177. memcpy((void *)&priv->active_rxon,
  2178. &priv->staging_rxon,
  2179. sizeof(struct iwl_rxon_cmd));
  2180. }
  2181. }
  2182. mutex_unlock(&priv->mutex);
  2183. IWL_DEBUG_MAC80211(priv, "leave\n");
  2184. }
  2185. EXPORT_SYMBOL(iwl_bss_info_changed);
  2186. int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  2187. {
  2188. struct iwl_priv *priv = hw->priv;
  2189. unsigned long flags;
  2190. __le64 timestamp;
  2191. IWL_DEBUG_MAC80211(priv, "enter\n");
  2192. if (!iwl_is_ready_rf(priv)) {
  2193. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  2194. return -EIO;
  2195. }
  2196. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  2197. IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n");
  2198. return -EIO;
  2199. }
  2200. spin_lock_irqsave(&priv->lock, flags);
  2201. if (priv->ibss_beacon)
  2202. dev_kfree_skb(priv->ibss_beacon);
  2203. priv->ibss_beacon = skb;
  2204. priv->assoc_id = 0;
  2205. timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
  2206. priv->timestamp = le64_to_cpu(timestamp);
  2207. IWL_DEBUG_MAC80211(priv, "leave\n");
  2208. spin_unlock_irqrestore(&priv->lock, flags);
  2209. iwl_reset_qos(priv);
  2210. priv->cfg->ops->lib->post_associate(priv);
  2211. return 0;
  2212. }
  2213. EXPORT_SYMBOL(iwl_mac_beacon_update);
  2214. int iwl_set_mode(struct iwl_priv *priv, int mode)
  2215. {
  2216. if (mode == NL80211_IFTYPE_ADHOC) {
  2217. const struct iwl_channel_info *ch_info;
  2218. ch_info = iwl_get_channel_info(priv,
  2219. priv->band,
  2220. le16_to_cpu(priv->staging_rxon.channel));
  2221. if (!ch_info || !is_channel_ibss(ch_info)) {
  2222. IWL_ERR(priv, "channel %d not IBSS channel\n",
  2223. le16_to_cpu(priv->staging_rxon.channel));
  2224. return -EINVAL;
  2225. }
  2226. }
  2227. iwl_connection_init_rx_config(priv, mode);
  2228. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2229. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2230. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  2231. iwl_clear_stations_table(priv);
  2232. /* dont commit rxon if rf-kill is on*/
  2233. if (!iwl_is_ready_rf(priv))
  2234. return -EAGAIN;
  2235. iwlcore_commit_rxon(priv);
  2236. return 0;
  2237. }
  2238. EXPORT_SYMBOL(iwl_set_mode);
  2239. int iwl_mac_add_interface(struct ieee80211_hw *hw,
  2240. struct ieee80211_if_init_conf *conf)
  2241. {
  2242. struct iwl_priv *priv = hw->priv;
  2243. unsigned long flags;
  2244. IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type);
  2245. if (priv->vif) {
  2246. IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
  2247. return -EOPNOTSUPP;
  2248. }
  2249. spin_lock_irqsave(&priv->lock, flags);
  2250. priv->vif = conf->vif;
  2251. priv->iw_mode = conf->type;
  2252. spin_unlock_irqrestore(&priv->lock, flags);
  2253. mutex_lock(&priv->mutex);
  2254. if (conf->mac_addr) {
  2255. IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr);
  2256. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  2257. }
  2258. if (iwl_set_mode(priv, conf->type) == -EAGAIN)
  2259. /* we are not ready, will run again when ready */
  2260. set_bit(STATUS_MODE_PENDING, &priv->status);
  2261. mutex_unlock(&priv->mutex);
  2262. IWL_DEBUG_MAC80211(priv, "leave\n");
  2263. return 0;
  2264. }
  2265. EXPORT_SYMBOL(iwl_mac_add_interface);
  2266. void iwl_mac_remove_interface(struct ieee80211_hw *hw,
  2267. struct ieee80211_if_init_conf *conf)
  2268. {
  2269. struct iwl_priv *priv = hw->priv;
  2270. IWL_DEBUG_MAC80211(priv, "enter\n");
  2271. mutex_lock(&priv->mutex);
  2272. if (iwl_is_ready_rf(priv)) {
  2273. iwl_scan_cancel_timeout(priv, 100);
  2274. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2275. iwlcore_commit_rxon(priv);
  2276. }
  2277. if (priv->vif == conf->vif) {
  2278. priv->vif = NULL;
  2279. memset(priv->bssid, 0, ETH_ALEN);
  2280. }
  2281. mutex_unlock(&priv->mutex);
  2282. IWL_DEBUG_MAC80211(priv, "leave\n");
  2283. }
  2284. EXPORT_SYMBOL(iwl_mac_remove_interface);
  2285. /**
  2286. * iwl_mac_config - mac80211 config callback
  2287. *
  2288. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  2289. * be set inappropriately and the driver currently sets the hardware up to
  2290. * use it whenever needed.
  2291. */
  2292. int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
  2293. {
  2294. struct iwl_priv *priv = hw->priv;
  2295. const struct iwl_channel_info *ch_info;
  2296. struct ieee80211_conf *conf = &hw->conf;
  2297. struct iwl_ht_info *ht_conf = &priv->current_ht_config;
  2298. unsigned long flags = 0;
  2299. int ret = 0;
  2300. u16 ch;
  2301. int scan_active = 0;
  2302. mutex_lock(&priv->mutex);
  2303. IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
  2304. conf->channel->hw_value, changed);
  2305. if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
  2306. test_bit(STATUS_SCANNING, &priv->status))) {
  2307. scan_active = 1;
  2308. IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
  2309. }
  2310. /* during scanning mac80211 will delay channel setting until
  2311. * scan finish with changed = 0
  2312. */
  2313. if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
  2314. if (scan_active)
  2315. goto set_ch_out;
  2316. ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
  2317. ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
  2318. if (!is_channel_valid(ch_info)) {
  2319. IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
  2320. ret = -EINVAL;
  2321. goto set_ch_out;
  2322. }
  2323. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  2324. !is_channel_ibss(ch_info)) {
  2325. IWL_ERR(priv, "channel %d in band %d not "
  2326. "IBSS channel\n",
  2327. conf->channel->hw_value, conf->channel->band);
  2328. ret = -EINVAL;
  2329. goto set_ch_out;
  2330. }
  2331. spin_lock_irqsave(&priv->lock, flags);
  2332. /* Configure HT40 channels */
  2333. ht_conf->is_ht = conf_is_ht(conf);
  2334. if (ht_conf->is_ht) {
  2335. if (conf_is_ht40_minus(conf)) {
  2336. ht_conf->extension_chan_offset =
  2337. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  2338. ht_conf->supported_chan_width =
  2339. IWL_CHANNEL_WIDTH_40MHZ;
  2340. } else if (conf_is_ht40_plus(conf)) {
  2341. ht_conf->extension_chan_offset =
  2342. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  2343. ht_conf->supported_chan_width =
  2344. IWL_CHANNEL_WIDTH_40MHZ;
  2345. } else {
  2346. ht_conf->extension_chan_offset =
  2347. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  2348. ht_conf->supported_chan_width =
  2349. IWL_CHANNEL_WIDTH_20MHZ;
  2350. }
  2351. } else
  2352. ht_conf->supported_chan_width = IWL_CHANNEL_WIDTH_20MHZ;
  2353. /* Default to no protection. Protection mode will later be set
  2354. * from BSS config in iwl_ht_conf */
  2355. ht_conf->ht_protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
  2356. /* if we are switching from ht to 2.4 clear flags
  2357. * from any ht related info since 2.4 does not
  2358. * support ht */
  2359. if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
  2360. priv->staging_rxon.flags = 0;
  2361. iwl_set_rxon_channel(priv, conf->channel);
  2362. iwl_set_flags_for_band(priv, conf->channel->band);
  2363. spin_unlock_irqrestore(&priv->lock, flags);
  2364. set_ch_out:
  2365. /* The list of supported rates and rate mask can be different
  2366. * for each band; since the band may have changed, reset
  2367. * the rate mask to what mac80211 lists */
  2368. iwl_set_rate(priv);
  2369. }
  2370. if (changed & IEEE80211_CONF_CHANGE_PS) {
  2371. ret = iwl_power_update_mode(priv, false);
  2372. if (ret)
  2373. IWL_DEBUG_MAC80211(priv, "Error setting sleep level\n");
  2374. }
  2375. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  2376. IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
  2377. priv->tx_power_user_lmt, conf->power_level);
  2378. iwl_set_tx_power(priv, conf->power_level, false);
  2379. }
  2380. /* call to ensure that 4965 rx_chain is set properly in monitor mode */
  2381. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2382. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2383. if (!iwl_is_ready(priv)) {
  2384. IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
  2385. goto out;
  2386. }
  2387. if (scan_active)
  2388. goto out;
  2389. if (memcmp(&priv->active_rxon,
  2390. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  2391. iwlcore_commit_rxon(priv);
  2392. else
  2393. IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n");
  2394. out:
  2395. IWL_DEBUG_MAC80211(priv, "leave\n");
  2396. mutex_unlock(&priv->mutex);
  2397. return ret;
  2398. }
  2399. EXPORT_SYMBOL(iwl_mac_config);
  2400. int iwl_mac_get_tx_stats(struct ieee80211_hw *hw,
  2401. struct ieee80211_tx_queue_stats *stats)
  2402. {
  2403. struct iwl_priv *priv = hw->priv;
  2404. int i, avail;
  2405. struct iwl_tx_queue *txq;
  2406. struct iwl_queue *q;
  2407. unsigned long flags;
  2408. IWL_DEBUG_MAC80211(priv, "enter\n");
  2409. if (!iwl_is_ready_rf(priv)) {
  2410. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  2411. return -EIO;
  2412. }
  2413. spin_lock_irqsave(&priv->lock, flags);
  2414. for (i = 0; i < AC_NUM; i++) {
  2415. txq = &priv->txq[i];
  2416. q = &txq->q;
  2417. avail = iwl_queue_space(q);
  2418. stats[i].len = q->n_window - avail;
  2419. stats[i].limit = q->n_window - q->high_mark;
  2420. stats[i].count = q->n_window;
  2421. }
  2422. spin_unlock_irqrestore(&priv->lock, flags);
  2423. IWL_DEBUG_MAC80211(priv, "leave\n");
  2424. return 0;
  2425. }
  2426. EXPORT_SYMBOL(iwl_mac_get_tx_stats);
  2427. void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
  2428. {
  2429. struct iwl_priv *priv = hw->priv;
  2430. unsigned long flags;
  2431. mutex_lock(&priv->mutex);
  2432. IWL_DEBUG_MAC80211(priv, "enter\n");
  2433. spin_lock_irqsave(&priv->lock, flags);
  2434. memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info));
  2435. spin_unlock_irqrestore(&priv->lock, flags);
  2436. iwl_reset_qos(priv);
  2437. spin_lock_irqsave(&priv->lock, flags);
  2438. priv->assoc_id = 0;
  2439. priv->assoc_capability = 0;
  2440. priv->assoc_station_added = 0;
  2441. /* new association get rid of ibss beacon skb */
  2442. if (priv->ibss_beacon)
  2443. dev_kfree_skb(priv->ibss_beacon);
  2444. priv->ibss_beacon = NULL;
  2445. priv->beacon_int = priv->vif->bss_conf.beacon_int;
  2446. priv->timestamp = 0;
  2447. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  2448. priv->beacon_int = 0;
  2449. spin_unlock_irqrestore(&priv->lock, flags);
  2450. if (!iwl_is_ready_rf(priv)) {
  2451. IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
  2452. mutex_unlock(&priv->mutex);
  2453. return;
  2454. }
  2455. /* we are restarting association process
  2456. * clear RXON_FILTER_ASSOC_MSK bit
  2457. */
  2458. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  2459. iwl_scan_cancel_timeout(priv, 100);
  2460. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2461. iwlcore_commit_rxon(priv);
  2462. }
  2463. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  2464. IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
  2465. mutex_unlock(&priv->mutex);
  2466. return;
  2467. }
  2468. iwl_set_rate(priv);
  2469. mutex_unlock(&priv->mutex);
  2470. IWL_DEBUG_MAC80211(priv, "leave\n");
  2471. }
  2472. EXPORT_SYMBOL(iwl_mac_reset_tsf);
  2473. #ifdef CONFIG_IWLWIFI_DEBUGFS
  2474. #define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES)
  2475. void iwl_reset_traffic_log(struct iwl_priv *priv)
  2476. {
  2477. priv->tx_traffic_idx = 0;
  2478. priv->rx_traffic_idx = 0;
  2479. if (priv->tx_traffic)
  2480. memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
  2481. if (priv->rx_traffic)
  2482. memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
  2483. }
  2484. int iwl_alloc_traffic_mem(struct iwl_priv *priv)
  2485. {
  2486. u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE;
  2487. if (iwl_debug_level & IWL_DL_TX) {
  2488. if (!priv->tx_traffic) {
  2489. priv->tx_traffic =
  2490. kzalloc(traffic_size, GFP_KERNEL);
  2491. if (!priv->tx_traffic)
  2492. return -ENOMEM;
  2493. }
  2494. }
  2495. if (iwl_debug_level & IWL_DL_RX) {
  2496. if (!priv->rx_traffic) {
  2497. priv->rx_traffic =
  2498. kzalloc(traffic_size, GFP_KERNEL);
  2499. if (!priv->rx_traffic)
  2500. return -ENOMEM;
  2501. }
  2502. }
  2503. iwl_reset_traffic_log(priv);
  2504. return 0;
  2505. }
  2506. EXPORT_SYMBOL(iwl_alloc_traffic_mem);
  2507. void iwl_free_traffic_mem(struct iwl_priv *priv)
  2508. {
  2509. kfree(priv->tx_traffic);
  2510. priv->tx_traffic = NULL;
  2511. kfree(priv->rx_traffic);
  2512. priv->rx_traffic = NULL;
  2513. }
  2514. EXPORT_SYMBOL(iwl_free_traffic_mem);
  2515. void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv,
  2516. u16 length, struct ieee80211_hdr *header)
  2517. {
  2518. __le16 fc;
  2519. u16 len;
  2520. if (likely(!(iwl_debug_level & IWL_DL_TX)))
  2521. return;
  2522. if (!priv->tx_traffic)
  2523. return;
  2524. fc = header->frame_control;
  2525. if (ieee80211_is_data(fc)) {
  2526. len = (length > IWL_TRAFFIC_ENTRY_SIZE)
  2527. ? IWL_TRAFFIC_ENTRY_SIZE : length;
  2528. memcpy((priv->tx_traffic +
  2529. (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
  2530. header, len);
  2531. priv->tx_traffic_idx =
  2532. (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
  2533. }
  2534. }
  2535. EXPORT_SYMBOL(iwl_dbg_log_tx_data_frame);
  2536. void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv,
  2537. u16 length, struct ieee80211_hdr *header)
  2538. {
  2539. __le16 fc;
  2540. u16 len;
  2541. if (likely(!(iwl_debug_level & IWL_DL_RX)))
  2542. return;
  2543. if (!priv->rx_traffic)
  2544. return;
  2545. fc = header->frame_control;
  2546. if (ieee80211_is_data(fc)) {
  2547. len = (length > IWL_TRAFFIC_ENTRY_SIZE)
  2548. ? IWL_TRAFFIC_ENTRY_SIZE : length;
  2549. memcpy((priv->rx_traffic +
  2550. (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
  2551. header, len);
  2552. priv->rx_traffic_idx =
  2553. (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
  2554. }
  2555. }
  2556. EXPORT_SYMBOL(iwl_dbg_log_rx_data_frame);
  2557. const char *get_mgmt_string(int cmd)
  2558. {
  2559. switch (cmd) {
  2560. IWL_CMD(MANAGEMENT_ASSOC_REQ);
  2561. IWL_CMD(MANAGEMENT_ASSOC_RESP);
  2562. IWL_CMD(MANAGEMENT_REASSOC_REQ);
  2563. IWL_CMD(MANAGEMENT_REASSOC_RESP);
  2564. IWL_CMD(MANAGEMENT_PROBE_REQ);
  2565. IWL_CMD(MANAGEMENT_PROBE_RESP);
  2566. IWL_CMD(MANAGEMENT_BEACON);
  2567. IWL_CMD(MANAGEMENT_ATIM);
  2568. IWL_CMD(MANAGEMENT_DISASSOC);
  2569. IWL_CMD(MANAGEMENT_AUTH);
  2570. IWL_CMD(MANAGEMENT_DEAUTH);
  2571. IWL_CMD(MANAGEMENT_ACTION);
  2572. default:
  2573. return "UNKNOWN";
  2574. }
  2575. }
  2576. const char *get_ctrl_string(int cmd)
  2577. {
  2578. switch (cmd) {
  2579. IWL_CMD(CONTROL_BACK_REQ);
  2580. IWL_CMD(CONTROL_BACK);
  2581. IWL_CMD(CONTROL_PSPOLL);
  2582. IWL_CMD(CONTROL_RTS);
  2583. IWL_CMD(CONTROL_CTS);
  2584. IWL_CMD(CONTROL_ACK);
  2585. IWL_CMD(CONTROL_CFEND);
  2586. IWL_CMD(CONTROL_CFENDACK);
  2587. default:
  2588. return "UNKNOWN";
  2589. }
  2590. }
  2591. void iwl_clear_tx_stats(struct iwl_priv *priv)
  2592. {
  2593. memset(&priv->tx_stats, 0, sizeof(struct traffic_stats));
  2594. }
  2595. void iwl_clear_rx_stats(struct iwl_priv *priv)
  2596. {
  2597. memset(&priv->rx_stats, 0, sizeof(struct traffic_stats));
  2598. }
  2599. /*
  2600. * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will
  2601. * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass.
  2602. * Use debugFs to display the rx/rx_statistics
  2603. * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL
  2604. * information will be recorded, but DATA pkt still will be recorded
  2605. * for the reason of iwl_led.c need to control the led blinking based on
  2606. * number of tx and rx data.
  2607. *
  2608. */
  2609. void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len)
  2610. {
  2611. struct traffic_stats *stats;
  2612. if (is_tx)
  2613. stats = &priv->tx_stats;
  2614. else
  2615. stats = &priv->rx_stats;
  2616. if (ieee80211_is_mgmt(fc)) {
  2617. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  2618. case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
  2619. stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
  2620. break;
  2621. case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
  2622. stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
  2623. break;
  2624. case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
  2625. stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
  2626. break;
  2627. case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
  2628. stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
  2629. break;
  2630. case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
  2631. stats->mgmt[MANAGEMENT_PROBE_REQ]++;
  2632. break;
  2633. case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
  2634. stats->mgmt[MANAGEMENT_PROBE_RESP]++;
  2635. break;
  2636. case cpu_to_le16(IEEE80211_STYPE_BEACON):
  2637. stats->mgmt[MANAGEMENT_BEACON]++;
  2638. break;
  2639. case cpu_to_le16(IEEE80211_STYPE_ATIM):
  2640. stats->mgmt[MANAGEMENT_ATIM]++;
  2641. break;
  2642. case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
  2643. stats->mgmt[MANAGEMENT_DISASSOC]++;
  2644. break;
  2645. case cpu_to_le16(IEEE80211_STYPE_AUTH):
  2646. stats->mgmt[MANAGEMENT_AUTH]++;
  2647. break;
  2648. case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
  2649. stats->mgmt[MANAGEMENT_DEAUTH]++;
  2650. break;
  2651. case cpu_to_le16(IEEE80211_STYPE_ACTION):
  2652. stats->mgmt[MANAGEMENT_ACTION]++;
  2653. break;
  2654. }
  2655. } else if (ieee80211_is_ctl(fc)) {
  2656. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  2657. case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
  2658. stats->ctrl[CONTROL_BACK_REQ]++;
  2659. break;
  2660. case cpu_to_le16(IEEE80211_STYPE_BACK):
  2661. stats->ctrl[CONTROL_BACK]++;
  2662. break;
  2663. case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
  2664. stats->ctrl[CONTROL_PSPOLL]++;
  2665. break;
  2666. case cpu_to_le16(IEEE80211_STYPE_RTS):
  2667. stats->ctrl[CONTROL_RTS]++;
  2668. break;
  2669. case cpu_to_le16(IEEE80211_STYPE_CTS):
  2670. stats->ctrl[CONTROL_CTS]++;
  2671. break;
  2672. case cpu_to_le16(IEEE80211_STYPE_ACK):
  2673. stats->ctrl[CONTROL_ACK]++;
  2674. break;
  2675. case cpu_to_le16(IEEE80211_STYPE_CFEND):
  2676. stats->ctrl[CONTROL_CFEND]++;
  2677. break;
  2678. case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
  2679. stats->ctrl[CONTROL_CFENDACK]++;
  2680. break;
  2681. }
  2682. } else {
  2683. /* data */
  2684. stats->data_cnt++;
  2685. stats->data_bytes += len;
  2686. }
  2687. }
  2688. EXPORT_SYMBOL(iwl_update_stats);
  2689. #endif
  2690. #ifdef CONFIG_PM
  2691. int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  2692. {
  2693. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2694. /*
  2695. * This function is called when system goes into suspend state
  2696. * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
  2697. * first but since iwl_mac_stop() has no knowledge of who the caller is,
  2698. * it will not call apm_ops.stop() to stop the DMA operation.
  2699. * Calling apm_ops.stop here to make sure we stop the DMA.
  2700. */
  2701. priv->cfg->ops->lib->apm_ops.stop(priv);
  2702. pci_save_state(pdev);
  2703. pci_disable_device(pdev);
  2704. pci_set_power_state(pdev, PCI_D3hot);
  2705. return 0;
  2706. }
  2707. EXPORT_SYMBOL(iwl_pci_suspend);
  2708. int iwl_pci_resume(struct pci_dev *pdev)
  2709. {
  2710. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2711. int ret;
  2712. pci_set_power_state(pdev, PCI_D0);
  2713. ret = pci_enable_device(pdev);
  2714. if (ret)
  2715. return ret;
  2716. pci_restore_state(pdev);
  2717. iwl_enable_interrupts(priv);
  2718. return 0;
  2719. }
  2720. EXPORT_SYMBOL(iwl_pci_resume);
  2721. #endif /* CONFIG_PM */