iwl-agn.c 85 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/mac80211.h>
  42. #include <asm/div64.h>
  43. #define DRV_NAME "iwlagn"
  44. #include "iwl-eeprom.h"
  45. #include "iwl-dev.h"
  46. #include "iwl-core.h"
  47. #include "iwl-io.h"
  48. #include "iwl-helpers.h"
  49. #include "iwl-sta.h"
  50. #include "iwl-calib.h"
  51. /******************************************************************************
  52. *
  53. * module boiler plate
  54. *
  55. ******************************************************************************/
  56. /*
  57. * module name, copyright, version, etc.
  58. */
  59. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  60. #ifdef CONFIG_IWLWIFI_DEBUG
  61. #define VD "d"
  62. #else
  63. #define VD
  64. #endif
  65. #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
  66. #define VS "s"
  67. #else
  68. #define VS
  69. #endif
  70. #define DRV_VERSION IWLWIFI_VERSION VD VS
  71. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  72. MODULE_VERSION(DRV_VERSION);
  73. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  74. MODULE_LICENSE("GPL");
  75. MODULE_ALIAS("iwl4965");
  76. /*************** STATION TABLE MANAGEMENT ****
  77. * mac80211 should be examined to determine if sta_info is duplicating
  78. * the functionality provided here
  79. */
  80. /**************************************************************/
  81. /**
  82. * iwl_commit_rxon - commit staging_rxon to hardware
  83. *
  84. * The RXON command in staging_rxon is committed to the hardware and
  85. * the active_rxon structure is updated with the new data. This
  86. * function correctly transitions out of the RXON_ASSOC_MSK state if
  87. * a HW tune is required based on the RXON structure changes.
  88. */
  89. int iwl_commit_rxon(struct iwl_priv *priv)
  90. {
  91. /* cast away the const for active_rxon in this function */
  92. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  93. int ret;
  94. bool new_assoc =
  95. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  96. if (!iwl_is_alive(priv))
  97. return -EBUSY;
  98. /* always get timestamp with Rx frame */
  99. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  100. /* allow CTS-to-self if possible. this is relevant only for
  101. * 5000, but will not damage 4965 */
  102. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  103. ret = iwl_check_rxon_cmd(priv);
  104. if (ret) {
  105. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  106. return -EINVAL;
  107. }
  108. /* If we don't need to send a full RXON, we can use
  109. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  110. * and other flags for the current radio configuration. */
  111. if (!iwl_full_rxon_required(priv)) {
  112. ret = iwl_send_rxon_assoc(priv);
  113. if (ret) {
  114. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  115. return ret;
  116. }
  117. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  118. return 0;
  119. }
  120. /* station table will be cleared */
  121. priv->assoc_station_added = 0;
  122. /* If we are currently associated and the new config requires
  123. * an RXON_ASSOC and the new config wants the associated mask enabled,
  124. * we must clear the associated from the active configuration
  125. * before we apply the new config */
  126. if (iwl_is_associated(priv) && new_assoc) {
  127. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  128. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  129. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  130. sizeof(struct iwl_rxon_cmd),
  131. &priv->active_rxon);
  132. /* If the mask clearing failed then we set
  133. * active_rxon back to what it was previously */
  134. if (ret) {
  135. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  136. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  137. return ret;
  138. }
  139. }
  140. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  141. "* with%s RXON_FILTER_ASSOC_MSK\n"
  142. "* channel = %d\n"
  143. "* bssid = %pM\n",
  144. (new_assoc ? "" : "out"),
  145. le16_to_cpu(priv->staging_rxon.channel),
  146. priv->staging_rxon.bssid_addr);
  147. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  148. /* Apply the new configuration
  149. * RXON unassoc clears the station table in uCode, send it before
  150. * we add the bcast station. If assoc bit is set, we will send RXON
  151. * after having added the bcast and bssid station.
  152. */
  153. if (!new_assoc) {
  154. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  155. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  156. if (ret) {
  157. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  158. return ret;
  159. }
  160. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  161. }
  162. iwl_clear_stations_table(priv);
  163. priv->start_calib = 0;
  164. /* Add the broadcast address so we can send broadcast frames */
  165. if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
  166. IWL_INVALID_STATION) {
  167. IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
  168. return -EIO;
  169. }
  170. /* If we have set the ASSOC_MSK and we are in BSS mode then
  171. * add the IWL_AP_ID to the station rate table */
  172. if (new_assoc) {
  173. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  174. ret = iwl_rxon_add_station(priv,
  175. priv->active_rxon.bssid_addr, 1);
  176. if (ret == IWL_INVALID_STATION) {
  177. IWL_ERR(priv,
  178. "Error adding AP address for TX.\n");
  179. return -EIO;
  180. }
  181. priv->assoc_station_added = 1;
  182. if (priv->default_wep_key &&
  183. iwl_send_static_wepkey_cmd(priv, 0))
  184. IWL_ERR(priv,
  185. "Could not send WEP static key.\n");
  186. }
  187. /* Apply the new configuration
  188. * RXON assoc doesn't clear the station table in uCode,
  189. */
  190. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  191. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  192. if (ret) {
  193. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  194. return ret;
  195. }
  196. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  197. }
  198. iwl_init_sensitivity(priv);
  199. /* If we issue a new RXON command which required a tune then we must
  200. * send a new TXPOWER command or we won't be able to Tx any frames */
  201. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  202. if (ret) {
  203. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  204. return ret;
  205. }
  206. return 0;
  207. }
  208. void iwl_update_chain_flags(struct iwl_priv *priv)
  209. {
  210. if (priv->cfg->ops->hcmd->set_rxon_chain)
  211. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  212. iwlcore_commit_rxon(priv);
  213. }
  214. static void iwl_clear_free_frames(struct iwl_priv *priv)
  215. {
  216. struct list_head *element;
  217. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  218. priv->frames_count);
  219. while (!list_empty(&priv->free_frames)) {
  220. element = priv->free_frames.next;
  221. list_del(element);
  222. kfree(list_entry(element, struct iwl_frame, list));
  223. priv->frames_count--;
  224. }
  225. if (priv->frames_count) {
  226. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  227. priv->frames_count);
  228. priv->frames_count = 0;
  229. }
  230. }
  231. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  232. {
  233. struct iwl_frame *frame;
  234. struct list_head *element;
  235. if (list_empty(&priv->free_frames)) {
  236. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  237. if (!frame) {
  238. IWL_ERR(priv, "Could not allocate frame!\n");
  239. return NULL;
  240. }
  241. priv->frames_count++;
  242. return frame;
  243. }
  244. element = priv->free_frames.next;
  245. list_del(element);
  246. return list_entry(element, struct iwl_frame, list);
  247. }
  248. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  249. {
  250. memset(frame, 0, sizeof(*frame));
  251. list_add(&frame->list, &priv->free_frames);
  252. }
  253. static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
  254. struct ieee80211_hdr *hdr,
  255. int left)
  256. {
  257. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  258. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  259. (priv->iw_mode != NL80211_IFTYPE_AP)))
  260. return 0;
  261. if (priv->ibss_beacon->len > left)
  262. return 0;
  263. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  264. return priv->ibss_beacon->len;
  265. }
  266. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  267. struct iwl_frame *frame, u8 rate)
  268. {
  269. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  270. unsigned int frame_size;
  271. tx_beacon_cmd = &frame->u.beacon;
  272. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  273. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  274. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  275. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  276. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  277. BUG_ON(frame_size > MAX_MPDU_SIZE);
  278. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  279. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  280. tx_beacon_cmd->tx.rate_n_flags =
  281. iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  282. else
  283. tx_beacon_cmd->tx.rate_n_flags =
  284. iwl_hw_set_rate_n_flags(rate, 0);
  285. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  286. TX_CMD_FLG_TSF_MSK |
  287. TX_CMD_FLG_STA_RATE_MSK;
  288. return sizeof(*tx_beacon_cmd) + frame_size;
  289. }
  290. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  291. {
  292. struct iwl_frame *frame;
  293. unsigned int frame_size;
  294. int rc;
  295. u8 rate;
  296. frame = iwl_get_free_frame(priv);
  297. if (!frame) {
  298. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  299. "command.\n");
  300. return -ENOMEM;
  301. }
  302. rate = iwl_rate_get_lowest_plcp(priv);
  303. frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
  304. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  305. &frame->u.cmd[0]);
  306. iwl_free_frame(priv, frame);
  307. return rc;
  308. }
  309. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  310. {
  311. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  312. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  313. if (sizeof(dma_addr_t) > sizeof(u32))
  314. addr |=
  315. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  316. return addr;
  317. }
  318. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  319. {
  320. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  321. return le16_to_cpu(tb->hi_n_len) >> 4;
  322. }
  323. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  324. dma_addr_t addr, u16 len)
  325. {
  326. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  327. u16 hi_n_len = len << 4;
  328. put_unaligned_le32(addr, &tb->lo);
  329. if (sizeof(dma_addr_t) > sizeof(u32))
  330. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  331. tb->hi_n_len = cpu_to_le16(hi_n_len);
  332. tfd->num_tbs = idx + 1;
  333. }
  334. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  335. {
  336. return tfd->num_tbs & 0x1f;
  337. }
  338. /**
  339. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  340. * @priv - driver private data
  341. * @txq - tx queue
  342. *
  343. * Does NOT advance any TFD circular buffer read/write indexes
  344. * Does NOT free the TFD itself (which is within circular buffer)
  345. */
  346. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  347. {
  348. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  349. struct iwl_tfd *tfd;
  350. struct pci_dev *dev = priv->pci_dev;
  351. int index = txq->q.read_ptr;
  352. int i;
  353. int num_tbs;
  354. tfd = &tfd_tmp[index];
  355. /* Sanity check on number of chunks */
  356. num_tbs = iwl_tfd_get_num_tbs(tfd);
  357. if (num_tbs >= IWL_NUM_OF_TBS) {
  358. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  359. /* @todo issue fatal error, it is quite serious situation */
  360. return;
  361. }
  362. /* Unmap tx_cmd */
  363. if (num_tbs)
  364. pci_unmap_single(dev,
  365. pci_unmap_addr(&txq->meta[index], mapping),
  366. pci_unmap_len(&txq->meta[index], len),
  367. PCI_DMA_BIDIRECTIONAL);
  368. /* Unmap chunks, if any. */
  369. for (i = 1; i < num_tbs; i++) {
  370. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  371. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  372. if (txq->txb) {
  373. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  374. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  375. }
  376. }
  377. }
  378. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  379. struct iwl_tx_queue *txq,
  380. dma_addr_t addr, u16 len,
  381. u8 reset, u8 pad)
  382. {
  383. struct iwl_queue *q;
  384. struct iwl_tfd *tfd, *tfd_tmp;
  385. u32 num_tbs;
  386. q = &txq->q;
  387. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  388. tfd = &tfd_tmp[q->write_ptr];
  389. if (reset)
  390. memset(tfd, 0, sizeof(*tfd));
  391. num_tbs = iwl_tfd_get_num_tbs(tfd);
  392. /* Each TFD can point to a maximum 20 Tx buffers */
  393. if (num_tbs >= IWL_NUM_OF_TBS) {
  394. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  395. IWL_NUM_OF_TBS);
  396. return -EINVAL;
  397. }
  398. BUG_ON(addr & ~DMA_BIT_MASK(36));
  399. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  400. IWL_ERR(priv, "Unaligned address = %llx\n",
  401. (unsigned long long)addr);
  402. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  403. return 0;
  404. }
  405. /*
  406. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  407. * given Tx queue, and enable the DMA channel used for that queue.
  408. *
  409. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  410. * channels supported in hardware.
  411. */
  412. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  413. struct iwl_tx_queue *txq)
  414. {
  415. int txq_id = txq->q.id;
  416. /* Circular buffer (TFD queue in DRAM) physical base address */
  417. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  418. txq->q.dma_addr >> 8);
  419. return 0;
  420. }
  421. /******************************************************************************
  422. *
  423. * Generic RX handler implementations
  424. *
  425. ******************************************************************************/
  426. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  427. struct iwl_rx_mem_buffer *rxb)
  428. {
  429. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  430. struct iwl_alive_resp *palive;
  431. struct delayed_work *pwork;
  432. palive = &pkt->u.alive_frame;
  433. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  434. "0x%01X 0x%01X\n",
  435. palive->is_valid, palive->ver_type,
  436. palive->ver_subtype);
  437. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  438. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  439. memcpy(&priv->card_alive_init,
  440. &pkt->u.alive_frame,
  441. sizeof(struct iwl_init_alive_resp));
  442. pwork = &priv->init_alive_start;
  443. } else {
  444. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  445. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  446. sizeof(struct iwl_alive_resp));
  447. pwork = &priv->alive_start;
  448. }
  449. /* We delay the ALIVE response by 5ms to
  450. * give the HW RF Kill time to activate... */
  451. if (palive->is_valid == UCODE_VALID_OK)
  452. queue_delayed_work(priv->workqueue, pwork,
  453. msecs_to_jiffies(5));
  454. else
  455. IWL_WARN(priv, "uCode did not respond OK.\n");
  456. }
  457. static void iwl_bg_beacon_update(struct work_struct *work)
  458. {
  459. struct iwl_priv *priv =
  460. container_of(work, struct iwl_priv, beacon_update);
  461. struct sk_buff *beacon;
  462. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  463. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  464. if (!beacon) {
  465. IWL_ERR(priv, "update beacon failed\n");
  466. return;
  467. }
  468. mutex_lock(&priv->mutex);
  469. /* new beacon skb is allocated every time; dispose previous.*/
  470. if (priv->ibss_beacon)
  471. dev_kfree_skb(priv->ibss_beacon);
  472. priv->ibss_beacon = beacon;
  473. mutex_unlock(&priv->mutex);
  474. iwl_send_beacon_cmd(priv);
  475. }
  476. /**
  477. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  478. *
  479. * This callback is provided in order to send a statistics request.
  480. *
  481. * This timer function is continually reset to execute within
  482. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  483. * was received. We need to ensure we receive the statistics in order
  484. * to update the temperature used for calibrating the TXPOWER.
  485. */
  486. static void iwl_bg_statistics_periodic(unsigned long data)
  487. {
  488. struct iwl_priv *priv = (struct iwl_priv *)data;
  489. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  490. return;
  491. /* dont send host command if rf-kill is on */
  492. if (!iwl_is_ready_rf(priv))
  493. return;
  494. iwl_send_statistics_request(priv, CMD_ASYNC);
  495. }
  496. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  497. struct iwl_rx_mem_buffer *rxb)
  498. {
  499. #ifdef CONFIG_IWLWIFI_DEBUG
  500. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  501. struct iwl4965_beacon_notif *beacon =
  502. (struct iwl4965_beacon_notif *)pkt->u.raw;
  503. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  504. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  505. "tsf %d %d rate %d\n",
  506. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  507. beacon->beacon_notify_hdr.failure_frame,
  508. le32_to_cpu(beacon->ibss_mgr_status),
  509. le32_to_cpu(beacon->high_tsf),
  510. le32_to_cpu(beacon->low_tsf), rate);
  511. #endif
  512. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  513. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  514. queue_work(priv->workqueue, &priv->beacon_update);
  515. }
  516. /* Handle notification from uCode that card's power state is changing
  517. * due to software, hardware, or critical temperature RFKILL */
  518. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  519. struct iwl_rx_mem_buffer *rxb)
  520. {
  521. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  522. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  523. unsigned long status = priv->status;
  524. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
  525. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  526. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  527. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  528. RF_CARD_DISABLED)) {
  529. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  530. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  531. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  532. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  533. if (!(flags & RXON_CARD_DISABLED)) {
  534. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  535. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  536. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  537. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  538. }
  539. if (flags & RF_CARD_DISABLED)
  540. iwl_tt_enter_ct_kill(priv);
  541. }
  542. if (!(flags & RF_CARD_DISABLED))
  543. iwl_tt_exit_ct_kill(priv);
  544. if (flags & HW_CARD_DISABLED)
  545. set_bit(STATUS_RF_KILL_HW, &priv->status);
  546. else
  547. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  548. if (!(flags & RXON_CARD_DISABLED))
  549. iwl_scan_cancel(priv);
  550. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  551. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  552. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  553. test_bit(STATUS_RF_KILL_HW, &priv->status));
  554. else
  555. wake_up_interruptible(&priv->wait_command_queue);
  556. }
  557. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  558. {
  559. if (src == IWL_PWR_SRC_VAUX) {
  560. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  561. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  562. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  563. ~APMG_PS_CTRL_MSK_PWR_SRC);
  564. } else {
  565. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  566. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  567. ~APMG_PS_CTRL_MSK_PWR_SRC);
  568. }
  569. return 0;
  570. }
  571. /**
  572. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  573. *
  574. * Setup the RX handlers for each of the reply types sent from the uCode
  575. * to the host.
  576. *
  577. * This function chains into the hardware specific files for them to setup
  578. * any hardware specific handlers as well.
  579. */
  580. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  581. {
  582. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  583. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  584. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  585. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  586. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  587. iwl_rx_pm_debug_statistics_notif;
  588. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  589. /*
  590. * The same handler is used for both the REPLY to a discrete
  591. * statistics request from the host as well as for the periodic
  592. * statistics notifications (after received beacons) from the uCode.
  593. */
  594. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
  595. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  596. iwl_setup_spectrum_handlers(priv);
  597. iwl_setup_rx_scan_handlers(priv);
  598. /* status change handler */
  599. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  600. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  601. iwl_rx_missed_beacon_notif;
  602. /* Rx handlers */
  603. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  604. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  605. /* block ack */
  606. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  607. /* Set up hardware specific Rx handlers */
  608. priv->cfg->ops->lib->rx_handler_setup(priv);
  609. }
  610. /**
  611. * iwl_rx_handle - Main entry function for receiving responses from uCode
  612. *
  613. * Uses the priv->rx_handlers callback function array to invoke
  614. * the appropriate handlers, including command responses,
  615. * frame-received notifications, and other notifications.
  616. */
  617. void iwl_rx_handle(struct iwl_priv *priv)
  618. {
  619. struct iwl_rx_mem_buffer *rxb;
  620. struct iwl_rx_packet *pkt;
  621. struct iwl_rx_queue *rxq = &priv->rxq;
  622. u32 r, i;
  623. int reclaim;
  624. unsigned long flags;
  625. u8 fill_rx = 0;
  626. u32 count = 8;
  627. int total_empty;
  628. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  629. * buffer that the driver may process (last buffer filled by ucode). */
  630. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  631. i = rxq->read;
  632. /* Rx interrupt, but nothing sent from uCode */
  633. if (i == r)
  634. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  635. /* calculate total frames need to be restock after handling RX */
  636. total_empty = r - priv->rxq.write_actual;
  637. if (total_empty < 0)
  638. total_empty += RX_QUEUE_SIZE;
  639. if (total_empty > (RX_QUEUE_SIZE / 2))
  640. fill_rx = 1;
  641. while (i != r) {
  642. rxb = rxq->queue[i];
  643. /* If an RXB doesn't have a Rx queue slot associated with it,
  644. * then a bug has been introduced in the queue refilling
  645. * routines -- catch it here */
  646. BUG_ON(rxb == NULL);
  647. rxq->queue[i] = NULL;
  648. pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
  649. priv->hw_params.rx_buf_size + 256,
  650. PCI_DMA_FROMDEVICE);
  651. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  652. /* Reclaim a command buffer only if this packet is a response
  653. * to a (driver-originated) command.
  654. * If the packet (e.g. Rx frame) originated from uCode,
  655. * there is no command buffer to reclaim.
  656. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  657. * but apparently a few don't get set; catch them here. */
  658. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  659. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  660. (pkt->hdr.cmd != REPLY_RX) &&
  661. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  662. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  663. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  664. (pkt->hdr.cmd != REPLY_TX);
  665. /* Based on type of command response or notification,
  666. * handle those that need handling via function in
  667. * rx_handlers table. See iwl_setup_rx_handlers() */
  668. if (priv->rx_handlers[pkt->hdr.cmd]) {
  669. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  670. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  671. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  672. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  673. } else {
  674. /* No handling needed */
  675. IWL_DEBUG_RX(priv,
  676. "r %d i %d No handler needed for %s, 0x%02x\n",
  677. r, i, get_cmd_string(pkt->hdr.cmd),
  678. pkt->hdr.cmd);
  679. }
  680. if (reclaim) {
  681. /* Invoke any callbacks, transfer the skb to caller, and
  682. * fire off the (possibly) blocking iwl_send_cmd()
  683. * as we reclaim the driver command queue */
  684. if (rxb && rxb->skb)
  685. iwl_tx_cmd_complete(priv, rxb);
  686. else
  687. IWL_WARN(priv, "Claim null rxb?\n");
  688. }
  689. /* For now we just don't re-use anything. We can tweak this
  690. * later to try and re-use notification packets and SKBs that
  691. * fail to Rx correctly */
  692. if (rxb->skb != NULL) {
  693. priv->alloc_rxb_skb--;
  694. dev_kfree_skb_any(rxb->skb);
  695. rxb->skb = NULL;
  696. }
  697. spin_lock_irqsave(&rxq->lock, flags);
  698. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  699. spin_unlock_irqrestore(&rxq->lock, flags);
  700. i = (i + 1) & RX_QUEUE_MASK;
  701. /* If there are a lot of unused frames,
  702. * restock the Rx queue so ucode wont assert. */
  703. if (fill_rx) {
  704. count++;
  705. if (count >= 8) {
  706. priv->rxq.read = i;
  707. iwl_rx_replenish_now(priv);
  708. count = 0;
  709. }
  710. }
  711. }
  712. /* Backtrack one entry */
  713. priv->rxq.read = i;
  714. if (fill_rx)
  715. iwl_rx_replenish_now(priv);
  716. else
  717. iwl_rx_queue_restock(priv);
  718. }
  719. /* call this function to flush any scheduled tasklet */
  720. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  721. {
  722. /* wait to make sure we flush pending tasklet*/
  723. synchronize_irq(priv->pci_dev->irq);
  724. tasklet_kill(&priv->irq_tasklet);
  725. }
  726. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  727. {
  728. u32 inta, handled = 0;
  729. u32 inta_fh;
  730. unsigned long flags;
  731. #ifdef CONFIG_IWLWIFI_DEBUG
  732. u32 inta_mask;
  733. #endif
  734. spin_lock_irqsave(&priv->lock, flags);
  735. /* Ack/clear/reset pending uCode interrupts.
  736. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  737. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  738. inta = iwl_read32(priv, CSR_INT);
  739. iwl_write32(priv, CSR_INT, inta);
  740. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  741. * Any new interrupts that happen after this, either while we're
  742. * in this tasklet, or later, will show up in next ISR/tasklet. */
  743. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  744. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  745. #ifdef CONFIG_IWLWIFI_DEBUG
  746. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  747. /* just for debug */
  748. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  749. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  750. inta, inta_mask, inta_fh);
  751. }
  752. #endif
  753. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  754. * atomic, make sure that inta covers all the interrupts that
  755. * we've discovered, even if FH interrupt came in just after
  756. * reading CSR_INT. */
  757. if (inta_fh & CSR49_FH_INT_RX_MASK)
  758. inta |= CSR_INT_BIT_FH_RX;
  759. if (inta_fh & CSR49_FH_INT_TX_MASK)
  760. inta |= CSR_INT_BIT_FH_TX;
  761. /* Now service all interrupt bits discovered above. */
  762. if (inta & CSR_INT_BIT_HW_ERR) {
  763. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  764. /* Tell the device to stop sending interrupts */
  765. iwl_disable_interrupts(priv);
  766. priv->isr_stats.hw++;
  767. iwl_irq_handle_error(priv);
  768. handled |= CSR_INT_BIT_HW_ERR;
  769. spin_unlock_irqrestore(&priv->lock, flags);
  770. return;
  771. }
  772. #ifdef CONFIG_IWLWIFI_DEBUG
  773. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  774. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  775. if (inta & CSR_INT_BIT_SCD) {
  776. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  777. "the frame/frames.\n");
  778. priv->isr_stats.sch++;
  779. }
  780. /* Alive notification via Rx interrupt will do the real work */
  781. if (inta & CSR_INT_BIT_ALIVE) {
  782. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  783. priv->isr_stats.alive++;
  784. }
  785. }
  786. #endif
  787. /* Safely ignore these bits for debug checks below */
  788. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  789. /* HW RF KILL switch toggled */
  790. if (inta & CSR_INT_BIT_RF_KILL) {
  791. int hw_rf_kill = 0;
  792. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  793. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  794. hw_rf_kill = 1;
  795. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  796. hw_rf_kill ? "disable radio" : "enable radio");
  797. priv->isr_stats.rfkill++;
  798. /* driver only loads ucode once setting the interface up.
  799. * the driver allows loading the ucode even if the radio
  800. * is killed. Hence update the killswitch state here. The
  801. * rfkill handler will care about restarting if needed.
  802. */
  803. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  804. if (hw_rf_kill)
  805. set_bit(STATUS_RF_KILL_HW, &priv->status);
  806. else
  807. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  808. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  809. }
  810. handled |= CSR_INT_BIT_RF_KILL;
  811. }
  812. /* Chip got too hot and stopped itself */
  813. if (inta & CSR_INT_BIT_CT_KILL) {
  814. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  815. priv->isr_stats.ctkill++;
  816. handled |= CSR_INT_BIT_CT_KILL;
  817. }
  818. /* Error detected by uCode */
  819. if (inta & CSR_INT_BIT_SW_ERR) {
  820. IWL_ERR(priv, "Microcode SW error detected. "
  821. " Restarting 0x%X.\n", inta);
  822. priv->isr_stats.sw++;
  823. priv->isr_stats.sw_err = inta;
  824. iwl_irq_handle_error(priv);
  825. handled |= CSR_INT_BIT_SW_ERR;
  826. }
  827. /* uCode wakes up after power-down sleep */
  828. if (inta & CSR_INT_BIT_WAKEUP) {
  829. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  830. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  831. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  832. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  833. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  834. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  835. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  836. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  837. priv->isr_stats.wakeup++;
  838. handled |= CSR_INT_BIT_WAKEUP;
  839. }
  840. /* All uCode command responses, including Tx command responses,
  841. * Rx "responses" (frame-received notification), and other
  842. * notifications from uCode come through here*/
  843. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  844. iwl_rx_handle(priv);
  845. priv->isr_stats.rx++;
  846. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  847. }
  848. if (inta & CSR_INT_BIT_FH_TX) {
  849. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  850. priv->isr_stats.tx++;
  851. handled |= CSR_INT_BIT_FH_TX;
  852. /* FH finished to write, send event */
  853. priv->ucode_write_complete = 1;
  854. wake_up_interruptible(&priv->wait_command_queue);
  855. }
  856. if (inta & ~handled) {
  857. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  858. priv->isr_stats.unhandled++;
  859. }
  860. if (inta & ~(priv->inta_mask)) {
  861. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  862. inta & ~priv->inta_mask);
  863. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  864. }
  865. /* Re-enable all interrupts */
  866. /* only Re-enable if diabled by irq */
  867. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  868. iwl_enable_interrupts(priv);
  869. #ifdef CONFIG_IWLWIFI_DEBUG
  870. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  871. inta = iwl_read32(priv, CSR_INT);
  872. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  873. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  874. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  875. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  876. }
  877. #endif
  878. spin_unlock_irqrestore(&priv->lock, flags);
  879. }
  880. /* tasklet for iwlagn interrupt */
  881. static void iwl_irq_tasklet(struct iwl_priv *priv)
  882. {
  883. u32 inta = 0;
  884. u32 handled = 0;
  885. unsigned long flags;
  886. #ifdef CONFIG_IWLWIFI_DEBUG
  887. u32 inta_mask;
  888. #endif
  889. spin_lock_irqsave(&priv->lock, flags);
  890. /* Ack/clear/reset pending uCode interrupts.
  891. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  892. */
  893. iwl_write32(priv, CSR_INT, priv->inta);
  894. inta = priv->inta;
  895. #ifdef CONFIG_IWLWIFI_DEBUG
  896. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  897. /* just for debug */
  898. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  899. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  900. inta, inta_mask);
  901. }
  902. #endif
  903. /* saved interrupt in inta variable now we can reset priv->inta */
  904. priv->inta = 0;
  905. /* Now service all interrupt bits discovered above. */
  906. if (inta & CSR_INT_BIT_HW_ERR) {
  907. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  908. /* Tell the device to stop sending interrupts */
  909. iwl_disable_interrupts(priv);
  910. priv->isr_stats.hw++;
  911. iwl_irq_handle_error(priv);
  912. handled |= CSR_INT_BIT_HW_ERR;
  913. spin_unlock_irqrestore(&priv->lock, flags);
  914. return;
  915. }
  916. #ifdef CONFIG_IWLWIFI_DEBUG
  917. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  918. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  919. if (inta & CSR_INT_BIT_SCD) {
  920. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  921. "the frame/frames.\n");
  922. priv->isr_stats.sch++;
  923. }
  924. /* Alive notification via Rx interrupt will do the real work */
  925. if (inta & CSR_INT_BIT_ALIVE) {
  926. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  927. priv->isr_stats.alive++;
  928. }
  929. }
  930. #endif
  931. /* Safely ignore these bits for debug checks below */
  932. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  933. /* HW RF KILL switch toggled */
  934. if (inta & CSR_INT_BIT_RF_KILL) {
  935. int hw_rf_kill = 0;
  936. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  937. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  938. hw_rf_kill = 1;
  939. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  940. hw_rf_kill ? "disable radio" : "enable radio");
  941. priv->isr_stats.rfkill++;
  942. /* driver only loads ucode once setting the interface up.
  943. * the driver allows loading the ucode even if the radio
  944. * is killed. Hence update the killswitch state here. The
  945. * rfkill handler will care about restarting if needed.
  946. */
  947. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  948. if (hw_rf_kill)
  949. set_bit(STATUS_RF_KILL_HW, &priv->status);
  950. else
  951. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  952. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  953. }
  954. handled |= CSR_INT_BIT_RF_KILL;
  955. }
  956. /* Chip got too hot and stopped itself */
  957. if (inta & CSR_INT_BIT_CT_KILL) {
  958. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  959. priv->isr_stats.ctkill++;
  960. handled |= CSR_INT_BIT_CT_KILL;
  961. }
  962. /* Error detected by uCode */
  963. if (inta & CSR_INT_BIT_SW_ERR) {
  964. IWL_ERR(priv, "Microcode SW error detected. "
  965. " Restarting 0x%X.\n", inta);
  966. priv->isr_stats.sw++;
  967. priv->isr_stats.sw_err = inta;
  968. iwl_irq_handle_error(priv);
  969. handled |= CSR_INT_BIT_SW_ERR;
  970. }
  971. /* uCode wakes up after power-down sleep */
  972. if (inta & CSR_INT_BIT_WAKEUP) {
  973. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  974. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  975. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  976. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  977. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  978. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  979. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  980. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  981. priv->isr_stats.wakeup++;
  982. handled |= CSR_INT_BIT_WAKEUP;
  983. }
  984. /* All uCode command responses, including Tx command responses,
  985. * Rx "responses" (frame-received notification), and other
  986. * notifications from uCode come through here*/
  987. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  988. CSR_INT_BIT_RX_PERIODIC)) {
  989. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  990. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  991. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  992. iwl_write32(priv, CSR_FH_INT_STATUS,
  993. CSR49_FH_INT_RX_MASK);
  994. }
  995. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  996. handled |= CSR_INT_BIT_RX_PERIODIC;
  997. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  998. }
  999. /* Sending RX interrupt require many steps to be done in the
  1000. * the device:
  1001. * 1- write interrupt to current index in ICT table.
  1002. * 2- dma RX frame.
  1003. * 3- update RX shared data to indicate last write index.
  1004. * 4- send interrupt.
  1005. * This could lead to RX race, driver could receive RX interrupt
  1006. * but the shared data changes does not reflect this.
  1007. * this could lead to RX race, RX periodic will solve this race
  1008. */
  1009. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1010. CSR_INT_PERIODIC_DIS);
  1011. iwl_rx_handle(priv);
  1012. /* Only set RX periodic if real RX is received. */
  1013. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1014. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1015. CSR_INT_PERIODIC_ENA);
  1016. priv->isr_stats.rx++;
  1017. }
  1018. if (inta & CSR_INT_BIT_FH_TX) {
  1019. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1020. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  1021. priv->isr_stats.tx++;
  1022. handled |= CSR_INT_BIT_FH_TX;
  1023. /* FH finished to write, send event */
  1024. priv->ucode_write_complete = 1;
  1025. wake_up_interruptible(&priv->wait_command_queue);
  1026. }
  1027. if (inta & ~handled) {
  1028. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1029. priv->isr_stats.unhandled++;
  1030. }
  1031. if (inta & ~(priv->inta_mask)) {
  1032. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1033. inta & ~priv->inta_mask);
  1034. }
  1035. /* Re-enable all interrupts */
  1036. /* only Re-enable if diabled by irq */
  1037. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1038. iwl_enable_interrupts(priv);
  1039. spin_unlock_irqrestore(&priv->lock, flags);
  1040. }
  1041. /******************************************************************************
  1042. *
  1043. * uCode download functions
  1044. *
  1045. ******************************************************************************/
  1046. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1047. {
  1048. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1049. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1050. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1051. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1052. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1053. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1054. }
  1055. static void iwl_nic_start(struct iwl_priv *priv)
  1056. {
  1057. /* Remove all resets to allow NIC to operate */
  1058. iwl_write32(priv, CSR_RESET, 0);
  1059. }
  1060. /**
  1061. * iwl_read_ucode - Read uCode images from disk file.
  1062. *
  1063. * Copy into buffers for card to fetch via bus-mastering
  1064. */
  1065. static int iwl_read_ucode(struct iwl_priv *priv)
  1066. {
  1067. struct iwl_ucode_header *ucode;
  1068. int ret = -EINVAL, index;
  1069. const struct firmware *ucode_raw;
  1070. const char *name_pre = priv->cfg->fw_name_pre;
  1071. const unsigned int api_max = priv->cfg->ucode_api_max;
  1072. const unsigned int api_min = priv->cfg->ucode_api_min;
  1073. char buf[25];
  1074. u8 *src;
  1075. size_t len;
  1076. u32 api_ver, build;
  1077. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1078. u16 eeprom_ver;
  1079. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1080. * request_firmware() is synchronous, file is in memory on return. */
  1081. for (index = api_max; index >= api_min; index--) {
  1082. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  1083. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1084. if (ret < 0) {
  1085. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1086. buf, ret);
  1087. if (ret == -ENOENT)
  1088. continue;
  1089. else
  1090. goto error;
  1091. } else {
  1092. if (index < api_max)
  1093. IWL_ERR(priv, "Loaded firmware %s, "
  1094. "which is deprecated. "
  1095. "Please use API v%u instead.\n",
  1096. buf, api_max);
  1097. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1098. buf, ucode_raw->size);
  1099. break;
  1100. }
  1101. }
  1102. if (ret < 0)
  1103. goto error;
  1104. /* Make sure that we got at least the v1 header! */
  1105. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1106. IWL_ERR(priv, "File size way too small!\n");
  1107. ret = -EINVAL;
  1108. goto err_release;
  1109. }
  1110. /* Data from ucode file: header followed by uCode images */
  1111. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1112. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1113. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1114. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1115. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1116. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1117. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1118. init_data_size =
  1119. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1120. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1121. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1122. /* api_ver should match the api version forming part of the
  1123. * firmware filename ... but we don't check for that and only rely
  1124. * on the API version read from firmware header from here on forward */
  1125. if (api_ver < api_min || api_ver > api_max) {
  1126. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1127. "Driver supports v%u, firmware is v%u.\n",
  1128. api_max, api_ver);
  1129. priv->ucode_ver = 0;
  1130. ret = -EINVAL;
  1131. goto err_release;
  1132. }
  1133. if (api_ver != api_max)
  1134. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1135. "got v%u. New firmware can be obtained "
  1136. "from http://www.intellinuxwireless.org.\n",
  1137. api_max, api_ver);
  1138. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1139. IWL_UCODE_MAJOR(priv->ucode_ver),
  1140. IWL_UCODE_MINOR(priv->ucode_ver),
  1141. IWL_UCODE_API(priv->ucode_ver),
  1142. IWL_UCODE_SERIAL(priv->ucode_ver));
  1143. if (build)
  1144. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1145. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1146. IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
  1147. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1148. ? "OTP" : "EEPROM", eeprom_ver);
  1149. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1150. priv->ucode_ver);
  1151. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1152. inst_size);
  1153. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1154. data_size);
  1155. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1156. init_size);
  1157. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1158. init_data_size);
  1159. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1160. boot_size);
  1161. /* Verify size of file vs. image size info in file's header */
  1162. if (ucode_raw->size !=
  1163. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1164. inst_size + data_size + init_size +
  1165. init_data_size + boot_size) {
  1166. IWL_DEBUG_INFO(priv,
  1167. "uCode file size %d does not match expected size\n",
  1168. (int)ucode_raw->size);
  1169. ret = -EINVAL;
  1170. goto err_release;
  1171. }
  1172. /* Verify that uCode images will fit in card's SRAM */
  1173. if (inst_size > priv->hw_params.max_inst_size) {
  1174. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1175. inst_size);
  1176. ret = -EINVAL;
  1177. goto err_release;
  1178. }
  1179. if (data_size > priv->hw_params.max_data_size) {
  1180. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1181. data_size);
  1182. ret = -EINVAL;
  1183. goto err_release;
  1184. }
  1185. if (init_size > priv->hw_params.max_inst_size) {
  1186. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1187. init_size);
  1188. ret = -EINVAL;
  1189. goto err_release;
  1190. }
  1191. if (init_data_size > priv->hw_params.max_data_size) {
  1192. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1193. init_data_size);
  1194. ret = -EINVAL;
  1195. goto err_release;
  1196. }
  1197. if (boot_size > priv->hw_params.max_bsm_size) {
  1198. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1199. boot_size);
  1200. ret = -EINVAL;
  1201. goto err_release;
  1202. }
  1203. /* Allocate ucode buffers for card's bus-master loading ... */
  1204. /* Runtime instructions and 2 copies of data:
  1205. * 1) unmodified from disk
  1206. * 2) backup cache for save/restore during power-downs */
  1207. priv->ucode_code.len = inst_size;
  1208. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1209. priv->ucode_data.len = data_size;
  1210. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1211. priv->ucode_data_backup.len = data_size;
  1212. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1213. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1214. !priv->ucode_data_backup.v_addr)
  1215. goto err_pci_alloc;
  1216. /* Initialization instructions and data */
  1217. if (init_size && init_data_size) {
  1218. priv->ucode_init.len = init_size;
  1219. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1220. priv->ucode_init_data.len = init_data_size;
  1221. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1222. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1223. goto err_pci_alloc;
  1224. }
  1225. /* Bootstrap (instructions only, no data) */
  1226. if (boot_size) {
  1227. priv->ucode_boot.len = boot_size;
  1228. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1229. if (!priv->ucode_boot.v_addr)
  1230. goto err_pci_alloc;
  1231. }
  1232. /* Copy images into buffers for card's bus-master reads ... */
  1233. /* Runtime instructions (first block of data in file) */
  1234. len = inst_size;
  1235. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1236. memcpy(priv->ucode_code.v_addr, src, len);
  1237. src += len;
  1238. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1239. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1240. /* Runtime data (2nd block)
  1241. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1242. len = data_size;
  1243. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1244. memcpy(priv->ucode_data.v_addr, src, len);
  1245. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1246. src += len;
  1247. /* Initialization instructions (3rd block) */
  1248. if (init_size) {
  1249. len = init_size;
  1250. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1251. len);
  1252. memcpy(priv->ucode_init.v_addr, src, len);
  1253. src += len;
  1254. }
  1255. /* Initialization data (4th block) */
  1256. if (init_data_size) {
  1257. len = init_data_size;
  1258. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1259. len);
  1260. memcpy(priv->ucode_init_data.v_addr, src, len);
  1261. src += len;
  1262. }
  1263. /* Bootstrap instructions (5th block) */
  1264. len = boot_size;
  1265. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1266. memcpy(priv->ucode_boot.v_addr, src, len);
  1267. /* We have our copies now, allow OS release its copies */
  1268. release_firmware(ucode_raw);
  1269. return 0;
  1270. err_pci_alloc:
  1271. IWL_ERR(priv, "failed to allocate pci memory\n");
  1272. ret = -ENOMEM;
  1273. iwl_dealloc_ucode_pci(priv);
  1274. err_release:
  1275. release_firmware(ucode_raw);
  1276. error:
  1277. return ret;
  1278. }
  1279. /**
  1280. * iwl_alive_start - called after REPLY_ALIVE notification received
  1281. * from protocol/runtime uCode (initialization uCode's
  1282. * Alive gets handled by iwl_init_alive_start()).
  1283. */
  1284. static void iwl_alive_start(struct iwl_priv *priv)
  1285. {
  1286. int ret = 0;
  1287. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1288. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1289. /* We had an error bringing up the hardware, so take it
  1290. * all the way back down so we can try again */
  1291. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1292. goto restart;
  1293. }
  1294. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1295. * This is a paranoid check, because we would not have gotten the
  1296. * "runtime" alive if code weren't properly loaded. */
  1297. if (iwl_verify_ucode(priv)) {
  1298. /* Runtime instruction load was bad;
  1299. * take it all the way back down so we can try again */
  1300. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1301. goto restart;
  1302. }
  1303. iwl_clear_stations_table(priv);
  1304. ret = priv->cfg->ops->lib->alive_notify(priv);
  1305. if (ret) {
  1306. IWL_WARN(priv,
  1307. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1308. goto restart;
  1309. }
  1310. /* After the ALIVE response, we can send host commands to the uCode */
  1311. set_bit(STATUS_ALIVE, &priv->status);
  1312. if (iwl_is_rfkill(priv))
  1313. return;
  1314. ieee80211_wake_queues(priv->hw);
  1315. priv->active_rate = priv->rates_mask;
  1316. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1317. if (iwl_is_associated(priv)) {
  1318. struct iwl_rxon_cmd *active_rxon =
  1319. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1320. /* apply any changes in staging */
  1321. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1322. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1323. } else {
  1324. /* Initialize our rx_config data */
  1325. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1326. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1327. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1328. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1329. }
  1330. /* Configure Bluetooth device coexistence support */
  1331. iwl_send_bt_config(priv);
  1332. iwl_reset_run_time_calib(priv);
  1333. /* Configure the adapter for unassociated operation */
  1334. iwlcore_commit_rxon(priv);
  1335. /* At this point, the NIC is initialized and operational */
  1336. iwl_rf_kill_ct_config(priv);
  1337. iwl_leds_register(priv);
  1338. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1339. set_bit(STATUS_READY, &priv->status);
  1340. wake_up_interruptible(&priv->wait_command_queue);
  1341. iwl_power_update_mode(priv, true);
  1342. /* reassociate for ADHOC mode */
  1343. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1344. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1345. priv->vif);
  1346. if (beacon)
  1347. iwl_mac_beacon_update(priv->hw, beacon);
  1348. }
  1349. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1350. iwl_set_mode(priv, priv->iw_mode);
  1351. return;
  1352. restart:
  1353. queue_work(priv->workqueue, &priv->restart);
  1354. }
  1355. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1356. static void __iwl_down(struct iwl_priv *priv)
  1357. {
  1358. unsigned long flags;
  1359. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1360. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1361. if (!exit_pending)
  1362. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1363. iwl_leds_unregister(priv);
  1364. iwl_clear_stations_table(priv);
  1365. /* Unblock any waiting calls */
  1366. wake_up_interruptible_all(&priv->wait_command_queue);
  1367. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1368. * exiting the module */
  1369. if (!exit_pending)
  1370. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1371. /* stop and reset the on-board processor */
  1372. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1373. /* tell the device to stop sending interrupts */
  1374. spin_lock_irqsave(&priv->lock, flags);
  1375. iwl_disable_interrupts(priv);
  1376. spin_unlock_irqrestore(&priv->lock, flags);
  1377. iwl_synchronize_irq(priv);
  1378. if (priv->mac80211_registered)
  1379. ieee80211_stop_queues(priv->hw);
  1380. /* If we have not previously called iwl_init() then
  1381. * clear all bits but the RF Kill bit and return */
  1382. if (!iwl_is_init(priv)) {
  1383. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1384. STATUS_RF_KILL_HW |
  1385. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1386. STATUS_GEO_CONFIGURED |
  1387. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1388. STATUS_EXIT_PENDING;
  1389. goto exit;
  1390. }
  1391. /* ...otherwise clear out all the status bits but the RF Kill
  1392. * bit and continue taking the NIC down. */
  1393. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1394. STATUS_RF_KILL_HW |
  1395. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1396. STATUS_GEO_CONFIGURED |
  1397. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1398. STATUS_FW_ERROR |
  1399. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1400. STATUS_EXIT_PENDING;
  1401. /* device going down, Stop using ICT table */
  1402. iwl_disable_ict(priv);
  1403. spin_lock_irqsave(&priv->lock, flags);
  1404. iwl_clear_bit(priv, CSR_GP_CNTRL,
  1405. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1406. spin_unlock_irqrestore(&priv->lock, flags);
  1407. iwl_txq_ctx_stop(priv);
  1408. iwl_rxq_stop(priv);
  1409. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  1410. APMG_CLK_VAL_DMA_CLK_RQT);
  1411. udelay(5);
  1412. /* FIXME: apm_ops.suspend(priv) */
  1413. if (exit_pending)
  1414. priv->cfg->ops->lib->apm_ops.stop(priv);
  1415. else
  1416. priv->cfg->ops->lib->apm_ops.reset(priv);
  1417. exit:
  1418. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1419. if (priv->ibss_beacon)
  1420. dev_kfree_skb(priv->ibss_beacon);
  1421. priv->ibss_beacon = NULL;
  1422. /* clear out any free frames */
  1423. iwl_clear_free_frames(priv);
  1424. }
  1425. static void iwl_down(struct iwl_priv *priv)
  1426. {
  1427. mutex_lock(&priv->mutex);
  1428. __iwl_down(priv);
  1429. mutex_unlock(&priv->mutex);
  1430. iwl_cancel_deferred_work(priv);
  1431. }
  1432. #define HW_READY_TIMEOUT (50)
  1433. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1434. {
  1435. int ret = 0;
  1436. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1437. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1438. /* See if we got it */
  1439. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1440. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1441. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1442. HW_READY_TIMEOUT);
  1443. if (ret != -ETIMEDOUT)
  1444. priv->hw_ready = true;
  1445. else
  1446. priv->hw_ready = false;
  1447. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1448. (priv->hw_ready == 1) ? "ready" : "not ready");
  1449. return ret;
  1450. }
  1451. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1452. {
  1453. int ret = 0;
  1454. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1455. ret = iwl_set_hw_ready(priv);
  1456. if (priv->hw_ready)
  1457. return ret;
  1458. /* If HW is not ready, prepare the conditions to check again */
  1459. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1460. CSR_HW_IF_CONFIG_REG_PREPARE);
  1461. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1462. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1463. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1464. /* HW should be ready by now, check again. */
  1465. if (ret != -ETIMEDOUT)
  1466. iwl_set_hw_ready(priv);
  1467. return ret;
  1468. }
  1469. #define MAX_HW_RESTARTS 5
  1470. static int __iwl_up(struct iwl_priv *priv)
  1471. {
  1472. int i;
  1473. int ret;
  1474. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1475. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1476. return -EIO;
  1477. }
  1478. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1479. IWL_ERR(priv, "ucode not available for device bringup\n");
  1480. return -EIO;
  1481. }
  1482. iwl_prepare_card_hw(priv);
  1483. if (!priv->hw_ready) {
  1484. IWL_WARN(priv, "Exit HW not ready\n");
  1485. return -EIO;
  1486. }
  1487. /* If platform's RF_KILL switch is NOT set to KILL */
  1488. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1489. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1490. else
  1491. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1492. if (iwl_is_rfkill(priv)) {
  1493. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1494. iwl_enable_interrupts(priv);
  1495. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1496. return 0;
  1497. }
  1498. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1499. ret = iwl_hw_nic_init(priv);
  1500. if (ret) {
  1501. IWL_ERR(priv, "Unable to init nic\n");
  1502. return ret;
  1503. }
  1504. /* make sure rfkill handshake bits are cleared */
  1505. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1506. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1507. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1508. /* clear (again), then enable host interrupts */
  1509. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1510. iwl_enable_interrupts(priv);
  1511. /* really make sure rfkill handshake bits are cleared */
  1512. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1513. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1514. /* Copy original ucode data image from disk into backup cache.
  1515. * This will be used to initialize the on-board processor's
  1516. * data SRAM for a clean start when the runtime program first loads. */
  1517. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1518. priv->ucode_data.len);
  1519. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1520. iwl_clear_stations_table(priv);
  1521. /* load bootstrap state machine,
  1522. * load bootstrap program into processor's memory,
  1523. * prepare to load the "initialize" uCode */
  1524. ret = priv->cfg->ops->lib->load_ucode(priv);
  1525. if (ret) {
  1526. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1527. ret);
  1528. continue;
  1529. }
  1530. /* start card; "initialize" will load runtime ucode */
  1531. iwl_nic_start(priv);
  1532. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1533. return 0;
  1534. }
  1535. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1536. __iwl_down(priv);
  1537. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1538. /* tried to restart and config the device for as long as our
  1539. * patience could withstand */
  1540. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1541. return -EIO;
  1542. }
  1543. /*****************************************************************************
  1544. *
  1545. * Workqueue callbacks
  1546. *
  1547. *****************************************************************************/
  1548. static void iwl_bg_init_alive_start(struct work_struct *data)
  1549. {
  1550. struct iwl_priv *priv =
  1551. container_of(data, struct iwl_priv, init_alive_start.work);
  1552. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1553. return;
  1554. mutex_lock(&priv->mutex);
  1555. priv->cfg->ops->lib->init_alive_start(priv);
  1556. mutex_unlock(&priv->mutex);
  1557. }
  1558. static void iwl_bg_alive_start(struct work_struct *data)
  1559. {
  1560. struct iwl_priv *priv =
  1561. container_of(data, struct iwl_priv, alive_start.work);
  1562. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1563. return;
  1564. /* enable dram interrupt */
  1565. iwl_reset_ict(priv);
  1566. mutex_lock(&priv->mutex);
  1567. iwl_alive_start(priv);
  1568. mutex_unlock(&priv->mutex);
  1569. }
  1570. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1571. {
  1572. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1573. run_time_calib_work);
  1574. mutex_lock(&priv->mutex);
  1575. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1576. test_bit(STATUS_SCANNING, &priv->status)) {
  1577. mutex_unlock(&priv->mutex);
  1578. return;
  1579. }
  1580. if (priv->start_calib) {
  1581. iwl_chain_noise_calibration(priv, &priv->statistics);
  1582. iwl_sensitivity_calibration(priv, &priv->statistics);
  1583. }
  1584. mutex_unlock(&priv->mutex);
  1585. return;
  1586. }
  1587. static void iwl_bg_up(struct work_struct *data)
  1588. {
  1589. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  1590. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1591. return;
  1592. mutex_lock(&priv->mutex);
  1593. __iwl_up(priv);
  1594. mutex_unlock(&priv->mutex);
  1595. }
  1596. static void iwl_bg_restart(struct work_struct *data)
  1597. {
  1598. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1599. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1600. return;
  1601. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1602. mutex_lock(&priv->mutex);
  1603. priv->vif = NULL;
  1604. priv->is_open = 0;
  1605. mutex_unlock(&priv->mutex);
  1606. iwl_down(priv);
  1607. ieee80211_restart_hw(priv->hw);
  1608. } else {
  1609. iwl_down(priv);
  1610. queue_work(priv->workqueue, &priv->up);
  1611. }
  1612. }
  1613. static void iwl_bg_rx_replenish(struct work_struct *data)
  1614. {
  1615. struct iwl_priv *priv =
  1616. container_of(data, struct iwl_priv, rx_replenish);
  1617. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1618. return;
  1619. mutex_lock(&priv->mutex);
  1620. iwl_rx_replenish(priv);
  1621. mutex_unlock(&priv->mutex);
  1622. }
  1623. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  1624. void iwl_post_associate(struct iwl_priv *priv)
  1625. {
  1626. struct ieee80211_conf *conf = NULL;
  1627. int ret = 0;
  1628. unsigned long flags;
  1629. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1630. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  1631. return;
  1632. }
  1633. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  1634. priv->assoc_id, priv->active_rxon.bssid_addr);
  1635. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1636. return;
  1637. if (!priv->vif || !priv->is_open)
  1638. return;
  1639. iwl_scan_cancel_timeout(priv, 200);
  1640. conf = ieee80211_get_hw_conf(priv->hw);
  1641. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1642. iwlcore_commit_rxon(priv);
  1643. iwl_setup_rxon_timing(priv);
  1644. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1645. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1646. if (ret)
  1647. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1648. "Attempting to continue.\n");
  1649. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1650. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  1651. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1652. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1653. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1654. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  1655. priv->assoc_id, priv->beacon_int);
  1656. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1657. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1658. else
  1659. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1660. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1661. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1662. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1663. else
  1664. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1665. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1666. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1667. }
  1668. iwlcore_commit_rxon(priv);
  1669. switch (priv->iw_mode) {
  1670. case NL80211_IFTYPE_STATION:
  1671. break;
  1672. case NL80211_IFTYPE_ADHOC:
  1673. /* assume default assoc id */
  1674. priv->assoc_id = 1;
  1675. iwl_rxon_add_station(priv, priv->bssid, 0);
  1676. iwl_send_beacon_cmd(priv);
  1677. break;
  1678. default:
  1679. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  1680. __func__, priv->iw_mode);
  1681. break;
  1682. }
  1683. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1684. priv->assoc_station_added = 1;
  1685. spin_lock_irqsave(&priv->lock, flags);
  1686. iwl_activate_qos(priv, 0);
  1687. spin_unlock_irqrestore(&priv->lock, flags);
  1688. /* the chain noise calibration will enabled PM upon completion
  1689. * If chain noise has already been run, then we need to enable
  1690. * power management here */
  1691. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  1692. iwl_power_update_mode(priv, false);
  1693. /* Enable Rx differential gain and sensitivity calibrations */
  1694. iwl_chain_noise_reset(priv);
  1695. priv->start_calib = 1;
  1696. }
  1697. /*****************************************************************************
  1698. *
  1699. * mac80211 entry point functions
  1700. *
  1701. *****************************************************************************/
  1702. #define UCODE_READY_TIMEOUT (4 * HZ)
  1703. static int iwl_mac_start(struct ieee80211_hw *hw)
  1704. {
  1705. struct iwl_priv *priv = hw->priv;
  1706. int ret;
  1707. IWL_DEBUG_MAC80211(priv, "enter\n");
  1708. /* we should be verifying the device is ready to be opened */
  1709. mutex_lock(&priv->mutex);
  1710. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  1711. * ucode filename and max sizes are card-specific. */
  1712. if (!priv->ucode_code.len) {
  1713. ret = iwl_read_ucode(priv);
  1714. if (ret) {
  1715. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  1716. mutex_unlock(&priv->mutex);
  1717. return ret;
  1718. }
  1719. }
  1720. ret = __iwl_up(priv);
  1721. mutex_unlock(&priv->mutex);
  1722. if (ret)
  1723. return ret;
  1724. if (iwl_is_rfkill(priv))
  1725. goto out;
  1726. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  1727. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  1728. * mac80211 will not be run successfully. */
  1729. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  1730. test_bit(STATUS_READY, &priv->status),
  1731. UCODE_READY_TIMEOUT);
  1732. if (!ret) {
  1733. if (!test_bit(STATUS_READY, &priv->status)) {
  1734. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  1735. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  1736. return -ETIMEDOUT;
  1737. }
  1738. }
  1739. out:
  1740. priv->is_open = 1;
  1741. IWL_DEBUG_MAC80211(priv, "leave\n");
  1742. return 0;
  1743. }
  1744. static void iwl_mac_stop(struct ieee80211_hw *hw)
  1745. {
  1746. struct iwl_priv *priv = hw->priv;
  1747. IWL_DEBUG_MAC80211(priv, "enter\n");
  1748. if (!priv->is_open)
  1749. return;
  1750. priv->is_open = 0;
  1751. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  1752. /* stop mac, cancel any scan request and clear
  1753. * RXON_FILTER_ASSOC_MSK BIT
  1754. */
  1755. mutex_lock(&priv->mutex);
  1756. iwl_scan_cancel_timeout(priv, 100);
  1757. mutex_unlock(&priv->mutex);
  1758. }
  1759. iwl_down(priv);
  1760. flush_workqueue(priv->workqueue);
  1761. /* enable interrupts again in order to receive rfkill changes */
  1762. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1763. iwl_enable_interrupts(priv);
  1764. IWL_DEBUG_MAC80211(priv, "leave\n");
  1765. }
  1766. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  1767. {
  1768. struct iwl_priv *priv = hw->priv;
  1769. IWL_DEBUG_MACDUMP(priv, "enter\n");
  1770. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  1771. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  1772. if (iwl_tx_skb(priv, skb))
  1773. dev_kfree_skb_any(skb);
  1774. IWL_DEBUG_MACDUMP(priv, "leave\n");
  1775. return NETDEV_TX_OK;
  1776. }
  1777. void iwl_config_ap(struct iwl_priv *priv)
  1778. {
  1779. int ret = 0;
  1780. unsigned long flags;
  1781. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1782. return;
  1783. /* The following should be done only at AP bring up */
  1784. if (!iwl_is_associated(priv)) {
  1785. /* RXON - unassoc (to set timing command) */
  1786. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1787. iwlcore_commit_rxon(priv);
  1788. /* RXON Timing */
  1789. iwl_setup_rxon_timing(priv);
  1790. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1791. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1792. if (ret)
  1793. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1794. "Attempting to continue.\n");
  1795. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1796. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1797. /* FIXME: what should be the assoc_id for AP? */
  1798. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1799. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1800. priv->staging_rxon.flags |=
  1801. RXON_FLG_SHORT_PREAMBLE_MSK;
  1802. else
  1803. priv->staging_rxon.flags &=
  1804. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1805. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1806. if (priv->assoc_capability &
  1807. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1808. priv->staging_rxon.flags |=
  1809. RXON_FLG_SHORT_SLOT_MSK;
  1810. else
  1811. priv->staging_rxon.flags &=
  1812. ~RXON_FLG_SHORT_SLOT_MSK;
  1813. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1814. priv->staging_rxon.flags &=
  1815. ~RXON_FLG_SHORT_SLOT_MSK;
  1816. }
  1817. /* restore RXON assoc */
  1818. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1819. iwlcore_commit_rxon(priv);
  1820. spin_lock_irqsave(&priv->lock, flags);
  1821. iwl_activate_qos(priv, 1);
  1822. spin_unlock_irqrestore(&priv->lock, flags);
  1823. iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
  1824. }
  1825. iwl_send_beacon_cmd(priv);
  1826. /* FIXME - we need to add code here to detect a totally new
  1827. * configuration, reset the AP, unassoc, rxon timing, assoc,
  1828. * clear sta table, add BCAST sta... */
  1829. }
  1830. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  1831. struct ieee80211_key_conf *keyconf, const u8 *addr,
  1832. u32 iv32, u16 *phase1key)
  1833. {
  1834. struct iwl_priv *priv = hw->priv;
  1835. IWL_DEBUG_MAC80211(priv, "enter\n");
  1836. iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
  1837. IWL_DEBUG_MAC80211(priv, "leave\n");
  1838. }
  1839. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  1840. struct ieee80211_vif *vif,
  1841. struct ieee80211_sta *sta,
  1842. struct ieee80211_key_conf *key)
  1843. {
  1844. struct iwl_priv *priv = hw->priv;
  1845. const u8 *addr;
  1846. int ret;
  1847. u8 sta_id;
  1848. bool is_default_wep_key = false;
  1849. IWL_DEBUG_MAC80211(priv, "enter\n");
  1850. if (priv->cfg->mod_params->sw_crypto) {
  1851. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  1852. return -EOPNOTSUPP;
  1853. }
  1854. addr = sta ? sta->addr : iwl_bcast_addr;
  1855. sta_id = iwl_find_station(priv, addr);
  1856. if (sta_id == IWL_INVALID_STATION) {
  1857. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  1858. addr);
  1859. return -EINVAL;
  1860. }
  1861. mutex_lock(&priv->mutex);
  1862. iwl_scan_cancel_timeout(priv, 100);
  1863. mutex_unlock(&priv->mutex);
  1864. /* If we are getting WEP group key and we didn't receive any key mapping
  1865. * so far, we are in legacy wep mode (group key only), otherwise we are
  1866. * in 1X mode.
  1867. * In legacy wep mode, we use another host command to the uCode */
  1868. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  1869. priv->iw_mode != NL80211_IFTYPE_AP) {
  1870. if (cmd == SET_KEY)
  1871. is_default_wep_key = !priv->key_mapping_key;
  1872. else
  1873. is_default_wep_key =
  1874. (key->hw_key_idx == HW_KEY_DEFAULT);
  1875. }
  1876. switch (cmd) {
  1877. case SET_KEY:
  1878. if (is_default_wep_key)
  1879. ret = iwl_set_default_wep_key(priv, key);
  1880. else
  1881. ret = iwl_set_dynamic_key(priv, key, sta_id);
  1882. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  1883. break;
  1884. case DISABLE_KEY:
  1885. if (is_default_wep_key)
  1886. ret = iwl_remove_default_wep_key(priv, key);
  1887. else
  1888. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  1889. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  1890. break;
  1891. default:
  1892. ret = -EINVAL;
  1893. }
  1894. IWL_DEBUG_MAC80211(priv, "leave\n");
  1895. return ret;
  1896. }
  1897. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  1898. enum ieee80211_ampdu_mlme_action action,
  1899. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  1900. {
  1901. struct iwl_priv *priv = hw->priv;
  1902. int ret;
  1903. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  1904. sta->addr, tid);
  1905. if (!(priv->cfg->sku & IWL_SKU_N))
  1906. return -EACCES;
  1907. switch (action) {
  1908. case IEEE80211_AMPDU_RX_START:
  1909. IWL_DEBUG_HT(priv, "start Rx\n");
  1910. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  1911. case IEEE80211_AMPDU_RX_STOP:
  1912. IWL_DEBUG_HT(priv, "stop Rx\n");
  1913. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  1914. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1915. return 0;
  1916. else
  1917. return ret;
  1918. case IEEE80211_AMPDU_TX_START:
  1919. IWL_DEBUG_HT(priv, "start Tx\n");
  1920. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  1921. case IEEE80211_AMPDU_TX_STOP:
  1922. IWL_DEBUG_HT(priv, "stop Tx\n");
  1923. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  1924. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1925. return 0;
  1926. else
  1927. return ret;
  1928. default:
  1929. IWL_DEBUG_HT(priv, "unknown\n");
  1930. return -EINVAL;
  1931. break;
  1932. }
  1933. return 0;
  1934. }
  1935. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  1936. struct ieee80211_low_level_stats *stats)
  1937. {
  1938. struct iwl_priv *priv = hw->priv;
  1939. priv = hw->priv;
  1940. IWL_DEBUG_MAC80211(priv, "enter\n");
  1941. IWL_DEBUG_MAC80211(priv, "leave\n");
  1942. return 0;
  1943. }
  1944. /*****************************************************************************
  1945. *
  1946. * sysfs attributes
  1947. *
  1948. *****************************************************************************/
  1949. #ifdef CONFIG_IWLWIFI_DEBUG
  1950. /*
  1951. * The following adds a new attribute to the sysfs representation
  1952. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  1953. * used for controlling the debug level.
  1954. *
  1955. * See the level definitions in iwl for details.
  1956. *
  1957. * The debug_level being managed using sysfs below is a per device debug
  1958. * level that is used instead of the global debug level if it (the per
  1959. * device debug level) is set.
  1960. */
  1961. static ssize_t show_debug_level(struct device *d,
  1962. struct device_attribute *attr, char *buf)
  1963. {
  1964. struct iwl_priv *priv = dev_get_drvdata(d);
  1965. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  1966. }
  1967. static ssize_t store_debug_level(struct device *d,
  1968. struct device_attribute *attr,
  1969. const char *buf, size_t count)
  1970. {
  1971. struct iwl_priv *priv = dev_get_drvdata(d);
  1972. unsigned long val;
  1973. int ret;
  1974. ret = strict_strtoul(buf, 0, &val);
  1975. if (ret)
  1976. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  1977. else {
  1978. priv->debug_level = val;
  1979. if (iwl_alloc_traffic_mem(priv))
  1980. IWL_ERR(priv,
  1981. "Not enough memory to generate traffic log\n");
  1982. }
  1983. return strnlen(buf, count);
  1984. }
  1985. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  1986. show_debug_level, store_debug_level);
  1987. #endif /* CONFIG_IWLWIFI_DEBUG */
  1988. static ssize_t show_temperature(struct device *d,
  1989. struct device_attribute *attr, char *buf)
  1990. {
  1991. struct iwl_priv *priv = dev_get_drvdata(d);
  1992. if (!iwl_is_alive(priv))
  1993. return -EAGAIN;
  1994. return sprintf(buf, "%d\n", priv->temperature);
  1995. }
  1996. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  1997. static ssize_t show_tx_power(struct device *d,
  1998. struct device_attribute *attr, char *buf)
  1999. {
  2000. struct iwl_priv *priv = dev_get_drvdata(d);
  2001. if (!iwl_is_ready_rf(priv))
  2002. return sprintf(buf, "off\n");
  2003. else
  2004. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2005. }
  2006. static ssize_t store_tx_power(struct device *d,
  2007. struct device_attribute *attr,
  2008. const char *buf, size_t count)
  2009. {
  2010. struct iwl_priv *priv = dev_get_drvdata(d);
  2011. unsigned long val;
  2012. int ret;
  2013. ret = strict_strtoul(buf, 10, &val);
  2014. if (ret)
  2015. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2016. else {
  2017. ret = iwl_set_tx_power(priv, val, false);
  2018. if (ret)
  2019. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2020. ret);
  2021. else
  2022. ret = count;
  2023. }
  2024. return ret;
  2025. }
  2026. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2027. static ssize_t show_flags(struct device *d,
  2028. struct device_attribute *attr, char *buf)
  2029. {
  2030. struct iwl_priv *priv = dev_get_drvdata(d);
  2031. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2032. }
  2033. static ssize_t store_flags(struct device *d,
  2034. struct device_attribute *attr,
  2035. const char *buf, size_t count)
  2036. {
  2037. struct iwl_priv *priv = dev_get_drvdata(d);
  2038. unsigned long val;
  2039. u32 flags;
  2040. int ret = strict_strtoul(buf, 0, &val);
  2041. if (ret)
  2042. return ret;
  2043. flags = (u32)val;
  2044. mutex_lock(&priv->mutex);
  2045. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2046. /* Cancel any currently running scans... */
  2047. if (iwl_scan_cancel_timeout(priv, 100))
  2048. IWL_WARN(priv, "Could not cancel scan.\n");
  2049. else {
  2050. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2051. priv->staging_rxon.flags = cpu_to_le32(flags);
  2052. iwlcore_commit_rxon(priv);
  2053. }
  2054. }
  2055. mutex_unlock(&priv->mutex);
  2056. return count;
  2057. }
  2058. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2059. static ssize_t show_filter_flags(struct device *d,
  2060. struct device_attribute *attr, char *buf)
  2061. {
  2062. struct iwl_priv *priv = dev_get_drvdata(d);
  2063. return sprintf(buf, "0x%04X\n",
  2064. le32_to_cpu(priv->active_rxon.filter_flags));
  2065. }
  2066. static ssize_t store_filter_flags(struct device *d,
  2067. struct device_attribute *attr,
  2068. const char *buf, size_t count)
  2069. {
  2070. struct iwl_priv *priv = dev_get_drvdata(d);
  2071. unsigned long val;
  2072. u32 filter_flags;
  2073. int ret = strict_strtoul(buf, 0, &val);
  2074. if (ret)
  2075. return ret;
  2076. filter_flags = (u32)val;
  2077. mutex_lock(&priv->mutex);
  2078. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2079. /* Cancel any currently running scans... */
  2080. if (iwl_scan_cancel_timeout(priv, 100))
  2081. IWL_WARN(priv, "Could not cancel scan.\n");
  2082. else {
  2083. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2084. "0x%04X\n", filter_flags);
  2085. priv->staging_rxon.filter_flags =
  2086. cpu_to_le32(filter_flags);
  2087. iwlcore_commit_rxon(priv);
  2088. }
  2089. }
  2090. mutex_unlock(&priv->mutex);
  2091. return count;
  2092. }
  2093. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2094. store_filter_flags);
  2095. static ssize_t show_statistics(struct device *d,
  2096. struct device_attribute *attr, char *buf)
  2097. {
  2098. struct iwl_priv *priv = dev_get_drvdata(d);
  2099. u32 size = sizeof(struct iwl_notif_statistics);
  2100. u32 len = 0, ofs = 0;
  2101. u8 *data = (u8 *)&priv->statistics;
  2102. int rc = 0;
  2103. if (!iwl_is_alive(priv))
  2104. return -EAGAIN;
  2105. mutex_lock(&priv->mutex);
  2106. rc = iwl_send_statistics_request(priv, 0);
  2107. mutex_unlock(&priv->mutex);
  2108. if (rc) {
  2109. len = sprintf(buf,
  2110. "Error sending statistics request: 0x%08X\n", rc);
  2111. return len;
  2112. }
  2113. while (size && (PAGE_SIZE - len)) {
  2114. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2115. PAGE_SIZE - len, 1);
  2116. len = strlen(buf);
  2117. if (PAGE_SIZE - len)
  2118. buf[len++] = '\n';
  2119. ofs += 16;
  2120. size -= min(size, 16U);
  2121. }
  2122. return len;
  2123. }
  2124. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2125. /*****************************************************************************
  2126. *
  2127. * driver setup and teardown
  2128. *
  2129. *****************************************************************************/
  2130. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2131. {
  2132. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2133. init_waitqueue_head(&priv->wait_command_queue);
  2134. INIT_WORK(&priv->up, iwl_bg_up);
  2135. INIT_WORK(&priv->restart, iwl_bg_restart);
  2136. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2137. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2138. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2139. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2140. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2141. iwl_setup_scan_deferred_work(priv);
  2142. if (priv->cfg->ops->lib->setup_deferred_work)
  2143. priv->cfg->ops->lib->setup_deferred_work(priv);
  2144. init_timer(&priv->statistics_periodic);
  2145. priv->statistics_periodic.data = (unsigned long)priv;
  2146. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2147. if (!priv->cfg->use_isr_legacy)
  2148. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2149. iwl_irq_tasklet, (unsigned long)priv);
  2150. else
  2151. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2152. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2153. }
  2154. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2155. {
  2156. if (priv->cfg->ops->lib->cancel_deferred_work)
  2157. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2158. cancel_delayed_work_sync(&priv->init_alive_start);
  2159. cancel_delayed_work(&priv->scan_check);
  2160. cancel_delayed_work(&priv->alive_start);
  2161. cancel_work_sync(&priv->beacon_update);
  2162. del_timer_sync(&priv->statistics_periodic);
  2163. }
  2164. static struct attribute *iwl_sysfs_entries[] = {
  2165. &dev_attr_flags.attr,
  2166. &dev_attr_filter_flags.attr,
  2167. &dev_attr_statistics.attr,
  2168. &dev_attr_temperature.attr,
  2169. &dev_attr_tx_power.attr,
  2170. #ifdef CONFIG_IWLWIFI_DEBUG
  2171. &dev_attr_debug_level.attr,
  2172. #endif
  2173. NULL
  2174. };
  2175. static struct attribute_group iwl_attribute_group = {
  2176. .name = NULL, /* put in device directory */
  2177. .attrs = iwl_sysfs_entries,
  2178. };
  2179. static struct ieee80211_ops iwl_hw_ops = {
  2180. .tx = iwl_mac_tx,
  2181. .start = iwl_mac_start,
  2182. .stop = iwl_mac_stop,
  2183. .add_interface = iwl_mac_add_interface,
  2184. .remove_interface = iwl_mac_remove_interface,
  2185. .config = iwl_mac_config,
  2186. .configure_filter = iwl_configure_filter,
  2187. .set_key = iwl_mac_set_key,
  2188. .update_tkip_key = iwl_mac_update_tkip_key,
  2189. .get_stats = iwl_mac_get_stats,
  2190. .get_tx_stats = iwl_mac_get_tx_stats,
  2191. .conf_tx = iwl_mac_conf_tx,
  2192. .reset_tsf = iwl_mac_reset_tsf,
  2193. .bss_info_changed = iwl_bss_info_changed,
  2194. .ampdu_action = iwl_mac_ampdu_action,
  2195. .hw_scan = iwl_mac_hw_scan
  2196. };
  2197. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2198. {
  2199. int err = 0;
  2200. struct iwl_priv *priv;
  2201. struct ieee80211_hw *hw;
  2202. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2203. unsigned long flags;
  2204. u16 pci_cmd;
  2205. /************************
  2206. * 1. Allocating HW data
  2207. ************************/
  2208. /* Disabling hardware scan means that mac80211 will perform scans
  2209. * "the hard way", rather than using device's scan. */
  2210. if (cfg->mod_params->disable_hw_scan) {
  2211. if (iwl_debug_level & IWL_DL_INFO)
  2212. dev_printk(KERN_DEBUG, &(pdev->dev),
  2213. "Disabling hw_scan\n");
  2214. iwl_hw_ops.hw_scan = NULL;
  2215. }
  2216. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2217. if (!hw) {
  2218. err = -ENOMEM;
  2219. goto out;
  2220. }
  2221. priv = hw->priv;
  2222. /* At this point both hw and priv are allocated. */
  2223. SET_IEEE80211_DEV(hw, &pdev->dev);
  2224. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2225. priv->cfg = cfg;
  2226. priv->pci_dev = pdev;
  2227. priv->inta_mask = CSR_INI_SET_MASK;
  2228. #ifdef CONFIG_IWLWIFI_DEBUG
  2229. atomic_set(&priv->restrict_refcnt, 0);
  2230. #endif
  2231. if (iwl_alloc_traffic_mem(priv))
  2232. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2233. /**************************
  2234. * 2. Initializing PCI bus
  2235. **************************/
  2236. if (pci_enable_device(pdev)) {
  2237. err = -ENODEV;
  2238. goto out_ieee80211_free_hw;
  2239. }
  2240. pci_set_master(pdev);
  2241. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2242. if (!err)
  2243. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2244. if (err) {
  2245. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2246. if (!err)
  2247. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2248. /* both attempts failed: */
  2249. if (err) {
  2250. IWL_WARN(priv, "No suitable DMA available.\n");
  2251. goto out_pci_disable_device;
  2252. }
  2253. }
  2254. err = pci_request_regions(pdev, DRV_NAME);
  2255. if (err)
  2256. goto out_pci_disable_device;
  2257. pci_set_drvdata(pdev, priv);
  2258. /***********************
  2259. * 3. Read REV register
  2260. ***********************/
  2261. priv->hw_base = pci_iomap(pdev, 0, 0);
  2262. if (!priv->hw_base) {
  2263. err = -ENODEV;
  2264. goto out_pci_release_regions;
  2265. }
  2266. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2267. (unsigned long long) pci_resource_len(pdev, 0));
  2268. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2269. /* this spin lock will be used in apm_ops.init and EEPROM access
  2270. * we should init now
  2271. */
  2272. spin_lock_init(&priv->reg_lock);
  2273. iwl_hw_detect(priv);
  2274. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2275. priv->cfg->name, priv->hw_rev);
  2276. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2277. * PCI Tx retries from interfering with C3 CPU state */
  2278. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2279. iwl_prepare_card_hw(priv);
  2280. if (!priv->hw_ready) {
  2281. IWL_WARN(priv, "Failed, HW not ready\n");
  2282. goto out_iounmap;
  2283. }
  2284. /* amp init */
  2285. err = priv->cfg->ops->lib->apm_ops.init(priv);
  2286. if (err < 0) {
  2287. IWL_ERR(priv, "Failed to init APMG\n");
  2288. goto out_iounmap;
  2289. }
  2290. /*****************
  2291. * 4. Read EEPROM
  2292. *****************/
  2293. /* Read the EEPROM */
  2294. err = iwl_eeprom_init(priv);
  2295. if (err) {
  2296. IWL_ERR(priv, "Unable to init EEPROM\n");
  2297. goto out_iounmap;
  2298. }
  2299. err = iwl_eeprom_check_version(priv);
  2300. if (err)
  2301. goto out_free_eeprom;
  2302. /* extract MAC Address */
  2303. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2304. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2305. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2306. /************************
  2307. * 5. Setup HW constants
  2308. ************************/
  2309. if (iwl_set_hw_params(priv)) {
  2310. IWL_ERR(priv, "failed to set hw parameters\n");
  2311. goto out_free_eeprom;
  2312. }
  2313. /*******************
  2314. * 6. Setup priv
  2315. *******************/
  2316. err = iwl_init_drv(priv);
  2317. if (err)
  2318. goto out_free_eeprom;
  2319. /* At this point both hw and priv are initialized. */
  2320. /********************
  2321. * 7. Setup services
  2322. ********************/
  2323. spin_lock_irqsave(&priv->lock, flags);
  2324. iwl_disable_interrupts(priv);
  2325. spin_unlock_irqrestore(&priv->lock, flags);
  2326. pci_enable_msi(priv->pci_dev);
  2327. iwl_alloc_isr_ict(priv);
  2328. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2329. IRQF_SHARED, DRV_NAME, priv);
  2330. if (err) {
  2331. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2332. goto out_disable_msi;
  2333. }
  2334. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2335. if (err) {
  2336. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2337. goto out_free_irq;
  2338. }
  2339. iwl_setup_deferred_work(priv);
  2340. iwl_setup_rx_handlers(priv);
  2341. /**********************************
  2342. * 8. Setup and register mac80211
  2343. **********************************/
  2344. /* enable interrupts if needed: hw bug w/a */
  2345. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2346. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2347. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2348. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2349. }
  2350. iwl_enable_interrupts(priv);
  2351. err = iwl_setup_mac(priv);
  2352. if (err)
  2353. goto out_remove_sysfs;
  2354. err = iwl_dbgfs_register(priv, DRV_NAME);
  2355. if (err)
  2356. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  2357. /* If platform's RF_KILL switch is NOT set to KILL */
  2358. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2359. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2360. else
  2361. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2362. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  2363. test_bit(STATUS_RF_KILL_HW, &priv->status));
  2364. iwl_power_initialize(priv);
  2365. iwl_tt_initialize(priv);
  2366. return 0;
  2367. out_remove_sysfs:
  2368. destroy_workqueue(priv->workqueue);
  2369. priv->workqueue = NULL;
  2370. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2371. out_free_irq:
  2372. free_irq(priv->pci_dev->irq, priv);
  2373. iwl_free_isr_ict(priv);
  2374. out_disable_msi:
  2375. pci_disable_msi(priv->pci_dev);
  2376. iwl_uninit_drv(priv);
  2377. out_free_eeprom:
  2378. iwl_eeprom_free(priv);
  2379. out_iounmap:
  2380. pci_iounmap(pdev, priv->hw_base);
  2381. out_pci_release_regions:
  2382. pci_set_drvdata(pdev, NULL);
  2383. pci_release_regions(pdev);
  2384. out_pci_disable_device:
  2385. pci_disable_device(pdev);
  2386. out_ieee80211_free_hw:
  2387. ieee80211_free_hw(priv->hw);
  2388. iwl_free_traffic_mem(priv);
  2389. out:
  2390. return err;
  2391. }
  2392. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2393. {
  2394. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2395. unsigned long flags;
  2396. if (!priv)
  2397. return;
  2398. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2399. iwl_dbgfs_unregister(priv);
  2400. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2401. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2402. * to be called and iwl_down since we are removing the device
  2403. * we need to set STATUS_EXIT_PENDING bit.
  2404. */
  2405. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2406. if (priv->mac80211_registered) {
  2407. ieee80211_unregister_hw(priv->hw);
  2408. priv->mac80211_registered = 0;
  2409. } else {
  2410. iwl_down(priv);
  2411. }
  2412. iwl_tt_exit(priv);
  2413. /* make sure we flush any pending irq or
  2414. * tasklet for the driver
  2415. */
  2416. spin_lock_irqsave(&priv->lock, flags);
  2417. iwl_disable_interrupts(priv);
  2418. spin_unlock_irqrestore(&priv->lock, flags);
  2419. iwl_synchronize_irq(priv);
  2420. iwl_dealloc_ucode_pci(priv);
  2421. if (priv->rxq.bd)
  2422. iwl_rx_queue_free(priv, &priv->rxq);
  2423. iwl_hw_txq_ctx_free(priv);
  2424. iwl_clear_stations_table(priv);
  2425. iwl_eeprom_free(priv);
  2426. /*netif_stop_queue(dev); */
  2427. flush_workqueue(priv->workqueue);
  2428. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  2429. * priv->workqueue... so we can't take down the workqueue
  2430. * until now... */
  2431. destroy_workqueue(priv->workqueue);
  2432. priv->workqueue = NULL;
  2433. iwl_free_traffic_mem(priv);
  2434. free_irq(priv->pci_dev->irq, priv);
  2435. pci_disable_msi(priv->pci_dev);
  2436. pci_iounmap(pdev, priv->hw_base);
  2437. pci_release_regions(pdev);
  2438. pci_disable_device(pdev);
  2439. pci_set_drvdata(pdev, NULL);
  2440. iwl_uninit_drv(priv);
  2441. iwl_free_isr_ict(priv);
  2442. if (priv->ibss_beacon)
  2443. dev_kfree_skb(priv->ibss_beacon);
  2444. ieee80211_free_hw(priv->hw);
  2445. }
  2446. /*****************************************************************************
  2447. *
  2448. * driver and module entry point
  2449. *
  2450. *****************************************************************************/
  2451. /* Hardware specific file defines the PCI IDs table for that hardware module */
  2452. static struct pci_device_id iwl_hw_card_ids[] = {
  2453. #ifdef CONFIG_IWL4965
  2454. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  2455. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  2456. #endif /* CONFIG_IWL4965 */
  2457. #ifdef CONFIG_IWL5000
  2458. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
  2459. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
  2460. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
  2461. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
  2462. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
  2463. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
  2464. {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
  2465. {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
  2466. {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
  2467. {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
  2468. /* 5350 WiFi/WiMax */
  2469. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
  2470. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
  2471. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
  2472. /* 5150 Wifi/WiMax */
  2473. {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
  2474. {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
  2475. /* 6000/6050 Series */
  2476. {IWL_PCI_DEVICE(0x008D, PCI_ANY_ID, iwl6000h_2agn_cfg)},
  2477. {IWL_PCI_DEVICE(0x008E, PCI_ANY_ID, iwl6000h_2agn_cfg)},
  2478. {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2479. {IWL_PCI_DEVICE(0x422C, PCI_ANY_ID, iwl6000i_2agn_cfg)},
  2480. {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2481. {IWL_PCI_DEVICE(0x4239, PCI_ANY_ID, iwl6000i_2agn_cfg)},
  2482. {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2483. {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2484. {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2485. {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2486. /* 1000 Series WiFi */
  2487. {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2488. {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2489. #endif /* CONFIG_IWL5000 */
  2490. {0}
  2491. };
  2492. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  2493. static struct pci_driver iwl_driver = {
  2494. .name = DRV_NAME,
  2495. .id_table = iwl_hw_card_ids,
  2496. .probe = iwl_pci_probe,
  2497. .remove = __devexit_p(iwl_pci_remove),
  2498. #ifdef CONFIG_PM
  2499. .suspend = iwl_pci_suspend,
  2500. .resume = iwl_pci_resume,
  2501. #endif
  2502. };
  2503. static int __init iwl_init(void)
  2504. {
  2505. int ret;
  2506. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  2507. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  2508. ret = iwlagn_rate_control_register();
  2509. if (ret) {
  2510. printk(KERN_ERR DRV_NAME
  2511. "Unable to register rate control algorithm: %d\n", ret);
  2512. return ret;
  2513. }
  2514. ret = pci_register_driver(&iwl_driver);
  2515. if (ret) {
  2516. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  2517. goto error_register;
  2518. }
  2519. return ret;
  2520. error_register:
  2521. iwlagn_rate_control_unregister();
  2522. return ret;
  2523. }
  2524. static void __exit iwl_exit(void)
  2525. {
  2526. pci_unregister_driver(&iwl_driver);
  2527. iwlagn_rate_control_unregister();
  2528. }
  2529. module_exit(iwl_exit);
  2530. module_init(iwl_init);
  2531. #ifdef CONFIG_IWLWIFI_DEBUG
  2532. module_param_named(debug50, iwl_debug_level, uint, 0444);
  2533. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  2534. module_param_named(debug, iwl_debug_level, uint, 0644);
  2535. MODULE_PARM_DESC(debug, "debug output mask");
  2536. #endif