attach.c 10 KB

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  1. /*
  2. * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
  3. * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
  4. *
  5. * Permission to use, copy, modify, and distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. *
  17. */
  18. /*************************************\
  19. * Attach/Detach Functions and helpers *
  20. \*************************************/
  21. #include <linux/pci.h>
  22. #include "ath5k.h"
  23. #include "reg.h"
  24. #include "debug.h"
  25. #include "base.h"
  26. /**
  27. * ath5k_hw_post - Power On Self Test helper function
  28. *
  29. * @ah: The &struct ath5k_hw
  30. */
  31. static int ath5k_hw_post(struct ath5k_hw *ah)
  32. {
  33. static const u32 static_pattern[4] = {
  34. 0x55555555, 0xaaaaaaaa,
  35. 0x66666666, 0x99999999
  36. };
  37. static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) };
  38. int i, c;
  39. u16 cur_reg;
  40. u32 var_pattern;
  41. u32 init_val;
  42. u32 cur_val;
  43. for (c = 0; c < 2; c++) {
  44. cur_reg = regs[c];
  45. /* Save previous value */
  46. init_val = ath5k_hw_reg_read(ah, cur_reg);
  47. for (i = 0; i < 256; i++) {
  48. var_pattern = i << 16 | i;
  49. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  50. cur_val = ath5k_hw_reg_read(ah, cur_reg);
  51. if (cur_val != var_pattern) {
  52. ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
  53. return -EAGAIN;
  54. }
  55. /* Found on ndiswrapper dumps */
  56. var_pattern = 0x0039080f;
  57. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  58. }
  59. for (i = 0; i < 4; i++) {
  60. var_pattern = static_pattern[i];
  61. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  62. cur_val = ath5k_hw_reg_read(ah, cur_reg);
  63. if (cur_val != var_pattern) {
  64. ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
  65. return -EAGAIN;
  66. }
  67. /* Found on ndiswrapper dumps */
  68. var_pattern = 0x003b080f;
  69. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  70. }
  71. /* Restore previous value */
  72. ath5k_hw_reg_write(ah, init_val, cur_reg);
  73. }
  74. return 0;
  75. }
  76. /**
  77. * ath5k_hw_attach - Check if hw is supported and init the needed structs
  78. *
  79. * @sc: The &struct ath5k_softc we got from the driver's attach function
  80. *
  81. * Check if the device is supported, perform a POST and initialize the needed
  82. * structs. Returns -ENOMEM if we don't have memory for the needed structs,
  83. * -ENODEV if the device is not supported or prints an error msg if something
  84. * else went wrong.
  85. */
  86. struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc)
  87. {
  88. struct ath5k_hw *ah;
  89. struct pci_dev *pdev = sc->pdev;
  90. struct ath5k_eeprom_info *ee;
  91. int ret;
  92. u32 srev;
  93. /*If we passed the test malloc a ath5k_hw struct*/
  94. ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
  95. if (ah == NULL) {
  96. ret = -ENOMEM;
  97. ATH5K_ERR(sc, "out of memory\n");
  98. goto err;
  99. }
  100. ah->ah_sc = sc;
  101. ah->ah_iobase = sc->iobase;
  102. /*
  103. * HW information
  104. */
  105. ah->ah_op_mode = NL80211_IFTYPE_STATION;
  106. ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
  107. ah->ah_turbo = false;
  108. ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
  109. ah->ah_imr = 0;
  110. ah->ah_atim_window = 0;
  111. ah->ah_aifs = AR5K_TUNE_AIFS;
  112. ah->ah_cw_min = AR5K_TUNE_CWMIN;
  113. ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
  114. ah->ah_software_retry = false;
  115. /*
  116. * Find the mac version
  117. */
  118. srev = ath5k_hw_reg_read(ah, AR5K_SREV);
  119. if (srev < AR5K_SREV_AR5311)
  120. ah->ah_version = AR5K_AR5210;
  121. else if (srev < AR5K_SREV_AR5212)
  122. ah->ah_version = AR5K_AR5211;
  123. else
  124. ah->ah_version = AR5K_AR5212;
  125. /*Fill the ath5k_hw struct with the needed functions*/
  126. ret = ath5k_hw_init_desc_functions(ah);
  127. if (ret)
  128. goto err_free;
  129. /* Bring device out of sleep and reset it's units */
  130. ret = ath5k_hw_nic_wakeup(ah, 0, true);
  131. if (ret)
  132. goto err_free;
  133. /* Get MAC, PHY and RADIO revisions */
  134. ah->ah_mac_srev = srev;
  135. ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
  136. ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
  137. ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
  138. 0xffffffff;
  139. ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
  140. CHANNEL_5GHZ);
  141. ah->ah_phy = AR5K_PHY(0);
  142. /* Try to identify radio chip based on it's srev */
  143. switch (ah->ah_radio_5ghz_revision & 0xf0) {
  144. case AR5K_SREV_RAD_5111:
  145. ah->ah_radio = AR5K_RF5111;
  146. ah->ah_single_chip = false;
  147. ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
  148. CHANNEL_2GHZ);
  149. break;
  150. case AR5K_SREV_RAD_5112:
  151. case AR5K_SREV_RAD_2112:
  152. ah->ah_radio = AR5K_RF5112;
  153. ah->ah_single_chip = false;
  154. ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
  155. CHANNEL_2GHZ);
  156. break;
  157. case AR5K_SREV_RAD_2413:
  158. ah->ah_radio = AR5K_RF2413;
  159. ah->ah_single_chip = true;
  160. break;
  161. case AR5K_SREV_RAD_5413:
  162. ah->ah_radio = AR5K_RF5413;
  163. ah->ah_single_chip = true;
  164. break;
  165. case AR5K_SREV_RAD_2316:
  166. ah->ah_radio = AR5K_RF2316;
  167. ah->ah_single_chip = true;
  168. break;
  169. case AR5K_SREV_RAD_2317:
  170. ah->ah_radio = AR5K_RF2317;
  171. ah->ah_single_chip = true;
  172. break;
  173. case AR5K_SREV_RAD_5424:
  174. if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
  175. ah->ah_mac_version == AR5K_SREV_AR2417){
  176. ah->ah_radio = AR5K_RF2425;
  177. ah->ah_single_chip = true;
  178. } else {
  179. ah->ah_radio = AR5K_RF5413;
  180. ah->ah_single_chip = true;
  181. }
  182. break;
  183. default:
  184. /* Identify radio based on mac/phy srev */
  185. if (ah->ah_version == AR5K_AR5210) {
  186. ah->ah_radio = AR5K_RF5110;
  187. ah->ah_single_chip = false;
  188. } else if (ah->ah_version == AR5K_AR5211) {
  189. ah->ah_radio = AR5K_RF5111;
  190. ah->ah_single_chip = false;
  191. ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
  192. CHANNEL_2GHZ);
  193. } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
  194. ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
  195. ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
  196. ah->ah_radio = AR5K_RF2425;
  197. ah->ah_single_chip = true;
  198. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
  199. } else if (srev == AR5K_SREV_AR5213A &&
  200. ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
  201. ah->ah_radio = AR5K_RF5112;
  202. ah->ah_single_chip = false;
  203. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
  204. } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
  205. ah->ah_radio = AR5K_RF2316;
  206. ah->ah_single_chip = true;
  207. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
  208. } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
  209. ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
  210. ah->ah_radio = AR5K_RF5413;
  211. ah->ah_single_chip = true;
  212. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
  213. } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
  214. ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
  215. ah->ah_radio = AR5K_RF2413;
  216. ah->ah_single_chip = true;
  217. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
  218. } else {
  219. ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
  220. ret = -ENODEV;
  221. goto err_free;
  222. }
  223. }
  224. /* Return on unsuported chips (unsupported eeprom etc) */
  225. if ((srev >= AR5K_SREV_AR5416) &&
  226. (srev < AR5K_SREV_AR2425)) {
  227. ATH5K_ERR(sc, "Device not yet supported.\n");
  228. ret = -ENODEV;
  229. goto err_free;
  230. }
  231. /*
  232. * POST
  233. */
  234. ret = ath5k_hw_post(ah);
  235. if (ret)
  236. goto err_free;
  237. /* Enable pci core retry fix on Hainan (5213A) and later chips */
  238. if (srev >= AR5K_SREV_AR5213A)
  239. AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX);
  240. /*
  241. * Get card capabilities, calibration values etc
  242. * TODO: EEPROM work
  243. */
  244. ret = ath5k_eeprom_init(ah);
  245. if (ret) {
  246. ATH5K_ERR(sc, "unable to init EEPROM\n");
  247. goto err_free;
  248. }
  249. /*
  250. * Write PCI-E power save settings
  251. */
  252. if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
  253. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  254. ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
  255. ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
  256. /* Shut off RX when elecidle is asserted */
  257. ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
  258. ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
  259. /* If serdes programing is enabled, increase PCI-E
  260. * tx power for systems with long trace from host
  261. * to minicard connector. */
  262. if (ee->ee_serdes)
  263. ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
  264. else
  265. ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES);
  266. /* Shut off PLL and CLKREQ active in L1 */
  267. ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
  268. /* Preserve other settings */
  269. ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
  270. ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
  271. ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
  272. /* Reset SERDES to load new settings */
  273. ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
  274. mdelay(1);
  275. }
  276. /* Get misc capabilities */
  277. ret = ath5k_hw_set_capabilities(ah);
  278. if (ret) {
  279. ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
  280. sc->pdev->device);
  281. goto err_free;
  282. }
  283. /* Crypto settings */
  284. ee = &ah->ah_capabilities.cap_eeprom;
  285. ah->ah_aes_support = srev >= AR5K_SREV_AR5212_V4 &&
  286. (ee->ee_version >= AR5K_EEPROM_VERSION_5_0 &&
  287. !AR5K_EEPROM_AES_DIS(ee->ee_misc5));
  288. if (srev >= AR5K_SREV_AR2414) {
  289. ah->ah_combined_mic = true;
  290. AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
  291. AR5K_MISC_MODE_COMBINED_MIC);
  292. }
  293. /* MAC address is cleared until add_interface */
  294. ath5k_hw_set_lladdr(ah, (u8[ETH_ALEN]){});
  295. /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
  296. memset(ah->ah_bssid, 0xff, ETH_ALEN);
  297. ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
  298. ath5k_hw_set_opmode(ah);
  299. ath5k_hw_rfgain_opt_init(ah);
  300. /* turn on HW LEDs */
  301. ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);
  302. return ah;
  303. err_free:
  304. kfree(ah);
  305. err:
  306. return ERR_PTR(ret);
  307. }
  308. /**
  309. * ath5k_hw_detach - Free the ath5k_hw struct
  310. *
  311. * @ah: The &struct ath5k_hw
  312. */
  313. void ath5k_hw_detach(struct ath5k_hw *ah)
  314. {
  315. ATH5K_TRACE(ah->ah_sc);
  316. __set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
  317. if (ah->ah_rf_banks != NULL)
  318. kfree(ah->ah_rf_banks);
  319. ath5k_eeprom_detach(ah);
  320. /* assume interrupts are down */
  321. kfree(ah);
  322. }