efx.c 60 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2005-2008 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/pci.h>
  12. #include <linux/netdevice.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/delay.h>
  15. #include <linux/notifier.h>
  16. #include <linux/ip.h>
  17. #include <linux/tcp.h>
  18. #include <linux/in.h>
  19. #include <linux/crc32.h>
  20. #include <linux/ethtool.h>
  21. #include <linux/topology.h>
  22. #include "net_driver.h"
  23. #include "ethtool.h"
  24. #include "tx.h"
  25. #include "rx.h"
  26. #include "efx.h"
  27. #include "mdio_10g.h"
  28. #include "falcon.h"
  29. #define EFX_MAX_MTU (9 * 1024)
  30. /* RX slow fill workqueue. If memory allocation fails in the fast path,
  31. * a work item is pushed onto this work queue to retry the allocation later,
  32. * to avoid the NIC being starved of RX buffers. Since this is a per cpu
  33. * workqueue, there is nothing to be gained in making it per NIC
  34. */
  35. static struct workqueue_struct *refill_workqueue;
  36. /* Reset workqueue. If any NIC has a hardware failure then a reset will be
  37. * queued onto this work queue. This is not a per-nic work queue, because
  38. * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
  39. */
  40. static struct workqueue_struct *reset_workqueue;
  41. /**************************************************************************
  42. *
  43. * Configurable values
  44. *
  45. *************************************************************************/
  46. /*
  47. * Use separate channels for TX and RX events
  48. *
  49. * Set this to 1 to use separate channels for TX and RX. It allows us
  50. * to control interrupt affinity separately for TX and RX.
  51. *
  52. * This is only used in MSI-X interrupt mode
  53. */
  54. static unsigned int separate_tx_channels;
  55. module_param(separate_tx_channels, uint, 0644);
  56. MODULE_PARM_DESC(separate_tx_channels,
  57. "Use separate channels for TX and RX");
  58. /* This is the weight assigned to each of the (per-channel) virtual
  59. * NAPI devices.
  60. */
  61. static int napi_weight = 64;
  62. /* This is the time (in jiffies) between invocations of the hardware
  63. * monitor, which checks for known hardware bugs and resets the
  64. * hardware and driver as necessary.
  65. */
  66. unsigned int efx_monitor_interval = 1 * HZ;
  67. /* This controls whether or not the driver will initialise devices
  68. * with invalid MAC addresses stored in the EEPROM or flash. If true,
  69. * such devices will be initialised with a random locally-generated
  70. * MAC address. This allows for loading the sfc_mtd driver to
  71. * reprogram the flash, even if the flash contents (including the MAC
  72. * address) have previously been erased.
  73. */
  74. static unsigned int allow_bad_hwaddr;
  75. /* Initial interrupt moderation settings. They can be modified after
  76. * module load with ethtool.
  77. *
  78. * The default for RX should strike a balance between increasing the
  79. * round-trip latency and reducing overhead.
  80. */
  81. static unsigned int rx_irq_mod_usec = 60;
  82. /* Initial interrupt moderation settings. They can be modified after
  83. * module load with ethtool.
  84. *
  85. * This default is chosen to ensure that a 10G link does not go idle
  86. * while a TX queue is stopped after it has become full. A queue is
  87. * restarted when it drops below half full. The time this takes (assuming
  88. * worst case 3 descriptors per packet and 1024 descriptors) is
  89. * 512 / 3 * 1.2 = 205 usec.
  90. */
  91. static unsigned int tx_irq_mod_usec = 150;
  92. /* This is the first interrupt mode to try out of:
  93. * 0 => MSI-X
  94. * 1 => MSI
  95. * 2 => legacy
  96. */
  97. static unsigned int interrupt_mode;
  98. /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
  99. * i.e. the number of CPUs among which we may distribute simultaneous
  100. * interrupt handling.
  101. *
  102. * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
  103. * The default (0) means to assign an interrupt to each package (level II cache)
  104. */
  105. static unsigned int rss_cpus;
  106. module_param(rss_cpus, uint, 0444);
  107. MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
  108. static int phy_flash_cfg;
  109. module_param(phy_flash_cfg, int, 0644);
  110. MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
  111. static unsigned irq_adapt_low_thresh = 10000;
  112. module_param(irq_adapt_low_thresh, uint, 0644);
  113. MODULE_PARM_DESC(irq_adapt_low_thresh,
  114. "Threshold score for reducing IRQ moderation");
  115. static unsigned irq_adapt_high_thresh = 20000;
  116. module_param(irq_adapt_high_thresh, uint, 0644);
  117. MODULE_PARM_DESC(irq_adapt_high_thresh,
  118. "Threshold score for increasing IRQ moderation");
  119. /**************************************************************************
  120. *
  121. * Utility functions and prototypes
  122. *
  123. *************************************************************************/
  124. static void efx_remove_channel(struct efx_channel *channel);
  125. static void efx_remove_port(struct efx_nic *efx);
  126. static void efx_fini_napi(struct efx_nic *efx);
  127. static void efx_fini_channels(struct efx_nic *efx);
  128. #define EFX_ASSERT_RESET_SERIALISED(efx) \
  129. do { \
  130. if (efx->state == STATE_RUNNING) \
  131. ASSERT_RTNL(); \
  132. } while (0)
  133. /**************************************************************************
  134. *
  135. * Event queue processing
  136. *
  137. *************************************************************************/
  138. /* Process channel's event queue
  139. *
  140. * This function is responsible for processing the event queue of a
  141. * single channel. The caller must guarantee that this function will
  142. * never be concurrently called more than once on the same channel,
  143. * though different channels may be being processed concurrently.
  144. */
  145. static int efx_process_channel(struct efx_channel *channel, int rx_quota)
  146. {
  147. struct efx_nic *efx = channel->efx;
  148. int rx_packets;
  149. if (unlikely(efx->reset_pending != RESET_TYPE_NONE ||
  150. !channel->enabled))
  151. return 0;
  152. rx_packets = falcon_process_eventq(channel, rx_quota);
  153. if (rx_packets == 0)
  154. return 0;
  155. /* Deliver last RX packet. */
  156. if (channel->rx_pkt) {
  157. __efx_rx_packet(channel, channel->rx_pkt,
  158. channel->rx_pkt_csummed);
  159. channel->rx_pkt = NULL;
  160. }
  161. efx_rx_strategy(channel);
  162. efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]);
  163. return rx_packets;
  164. }
  165. /* Mark channel as finished processing
  166. *
  167. * Note that since we will not receive further interrupts for this
  168. * channel before we finish processing and call the eventq_read_ack()
  169. * method, there is no need to use the interrupt hold-off timers.
  170. */
  171. static inline void efx_channel_processed(struct efx_channel *channel)
  172. {
  173. /* The interrupt handler for this channel may set work_pending
  174. * as soon as we acknowledge the events we've seen. Make sure
  175. * it's cleared before then. */
  176. channel->work_pending = false;
  177. smp_wmb();
  178. falcon_eventq_read_ack(channel);
  179. }
  180. /* NAPI poll handler
  181. *
  182. * NAPI guarantees serialisation of polls of the same device, which
  183. * provides the guarantee required by efx_process_channel().
  184. */
  185. static int efx_poll(struct napi_struct *napi, int budget)
  186. {
  187. struct efx_channel *channel =
  188. container_of(napi, struct efx_channel, napi_str);
  189. int rx_packets;
  190. EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n",
  191. channel->channel, raw_smp_processor_id());
  192. rx_packets = efx_process_channel(channel, budget);
  193. if (rx_packets < budget) {
  194. struct efx_nic *efx = channel->efx;
  195. if (channel->used_flags & EFX_USED_BY_RX &&
  196. efx->irq_rx_adaptive &&
  197. unlikely(++channel->irq_count == 1000)) {
  198. unsigned old_irq_moderation = channel->irq_moderation;
  199. if (unlikely(channel->irq_mod_score <
  200. irq_adapt_low_thresh)) {
  201. channel->irq_moderation =
  202. max_t(int,
  203. channel->irq_moderation -
  204. FALCON_IRQ_MOD_RESOLUTION,
  205. FALCON_IRQ_MOD_RESOLUTION);
  206. } else if (unlikely(channel->irq_mod_score >
  207. irq_adapt_high_thresh)) {
  208. channel->irq_moderation =
  209. min(channel->irq_moderation +
  210. FALCON_IRQ_MOD_RESOLUTION,
  211. efx->irq_rx_moderation);
  212. }
  213. if (channel->irq_moderation != old_irq_moderation)
  214. falcon_set_int_moderation(channel);
  215. channel->irq_count = 0;
  216. channel->irq_mod_score = 0;
  217. }
  218. /* There is no race here; although napi_disable() will
  219. * only wait for napi_complete(), this isn't a problem
  220. * since efx_channel_processed() will have no effect if
  221. * interrupts have already been disabled.
  222. */
  223. napi_complete(napi);
  224. efx_channel_processed(channel);
  225. }
  226. return rx_packets;
  227. }
  228. /* Process the eventq of the specified channel immediately on this CPU
  229. *
  230. * Disable hardware generated interrupts, wait for any existing
  231. * processing to finish, then directly poll (and ack ) the eventq.
  232. * Finally reenable NAPI and interrupts.
  233. *
  234. * Since we are touching interrupts the caller should hold the suspend lock
  235. */
  236. void efx_process_channel_now(struct efx_channel *channel)
  237. {
  238. struct efx_nic *efx = channel->efx;
  239. BUG_ON(!channel->used_flags);
  240. BUG_ON(!channel->enabled);
  241. /* Disable interrupts and wait for ISRs to complete */
  242. falcon_disable_interrupts(efx);
  243. if (efx->legacy_irq)
  244. synchronize_irq(efx->legacy_irq);
  245. if (channel->irq)
  246. synchronize_irq(channel->irq);
  247. /* Wait for any NAPI processing to complete */
  248. napi_disable(&channel->napi_str);
  249. /* Poll the channel */
  250. efx_process_channel(channel, efx->type->evq_size);
  251. /* Ack the eventq. This may cause an interrupt to be generated
  252. * when they are reenabled */
  253. efx_channel_processed(channel);
  254. napi_enable(&channel->napi_str);
  255. falcon_enable_interrupts(efx);
  256. }
  257. /* Create event queue
  258. * Event queue memory allocations are done only once. If the channel
  259. * is reset, the memory buffer will be reused; this guards against
  260. * errors during channel reset and also simplifies interrupt handling.
  261. */
  262. static int efx_probe_eventq(struct efx_channel *channel)
  263. {
  264. EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel);
  265. return falcon_probe_eventq(channel);
  266. }
  267. /* Prepare channel's event queue */
  268. static void efx_init_eventq(struct efx_channel *channel)
  269. {
  270. EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel);
  271. channel->eventq_read_ptr = 0;
  272. falcon_init_eventq(channel);
  273. }
  274. static void efx_fini_eventq(struct efx_channel *channel)
  275. {
  276. EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel);
  277. falcon_fini_eventq(channel);
  278. }
  279. static void efx_remove_eventq(struct efx_channel *channel)
  280. {
  281. EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel);
  282. falcon_remove_eventq(channel);
  283. }
  284. /**************************************************************************
  285. *
  286. * Channel handling
  287. *
  288. *************************************************************************/
  289. static int efx_probe_channel(struct efx_channel *channel)
  290. {
  291. struct efx_tx_queue *tx_queue;
  292. struct efx_rx_queue *rx_queue;
  293. int rc;
  294. EFX_LOG(channel->efx, "creating channel %d\n", channel->channel);
  295. rc = efx_probe_eventq(channel);
  296. if (rc)
  297. goto fail1;
  298. efx_for_each_channel_tx_queue(tx_queue, channel) {
  299. rc = efx_probe_tx_queue(tx_queue);
  300. if (rc)
  301. goto fail2;
  302. }
  303. efx_for_each_channel_rx_queue(rx_queue, channel) {
  304. rc = efx_probe_rx_queue(rx_queue);
  305. if (rc)
  306. goto fail3;
  307. }
  308. channel->n_rx_frm_trunc = 0;
  309. return 0;
  310. fail3:
  311. efx_for_each_channel_rx_queue(rx_queue, channel)
  312. efx_remove_rx_queue(rx_queue);
  313. fail2:
  314. efx_for_each_channel_tx_queue(tx_queue, channel)
  315. efx_remove_tx_queue(tx_queue);
  316. fail1:
  317. return rc;
  318. }
  319. static void efx_set_channel_names(struct efx_nic *efx)
  320. {
  321. struct efx_channel *channel;
  322. const char *type = "";
  323. int number;
  324. efx_for_each_channel(channel, efx) {
  325. number = channel->channel;
  326. if (efx->n_channels > efx->n_rx_queues) {
  327. if (channel->channel < efx->n_rx_queues) {
  328. type = "-rx";
  329. } else {
  330. type = "-tx";
  331. number -= efx->n_rx_queues;
  332. }
  333. }
  334. snprintf(channel->name, sizeof(channel->name),
  335. "%s%s-%d", efx->name, type, number);
  336. }
  337. }
  338. /* Channels are shutdown and reinitialised whilst the NIC is running
  339. * to propagate configuration changes (mtu, checksum offload), or
  340. * to clear hardware error conditions
  341. */
  342. static void efx_init_channels(struct efx_nic *efx)
  343. {
  344. struct efx_tx_queue *tx_queue;
  345. struct efx_rx_queue *rx_queue;
  346. struct efx_channel *channel;
  347. /* Calculate the rx buffer allocation parameters required to
  348. * support the current MTU, including padding for header
  349. * alignment and overruns.
  350. */
  351. efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) +
  352. EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
  353. efx->type->rx_buffer_padding);
  354. efx->rx_buffer_order = get_order(efx->rx_buffer_len);
  355. /* Initialise the channels */
  356. efx_for_each_channel(channel, efx) {
  357. EFX_LOG(channel->efx, "init chan %d\n", channel->channel);
  358. efx_init_eventq(channel);
  359. efx_for_each_channel_tx_queue(tx_queue, channel)
  360. efx_init_tx_queue(tx_queue);
  361. /* The rx buffer allocation strategy is MTU dependent */
  362. efx_rx_strategy(channel);
  363. efx_for_each_channel_rx_queue(rx_queue, channel)
  364. efx_init_rx_queue(rx_queue);
  365. WARN_ON(channel->rx_pkt != NULL);
  366. efx_rx_strategy(channel);
  367. }
  368. }
  369. /* This enables event queue processing and packet transmission.
  370. *
  371. * Note that this function is not allowed to fail, since that would
  372. * introduce too much complexity into the suspend/resume path.
  373. */
  374. static void efx_start_channel(struct efx_channel *channel)
  375. {
  376. struct efx_rx_queue *rx_queue;
  377. EFX_LOG(channel->efx, "starting chan %d\n", channel->channel);
  378. /* The interrupt handler for this channel may set work_pending
  379. * as soon as we enable it. Make sure it's cleared before
  380. * then. Similarly, make sure it sees the enabled flag set. */
  381. channel->work_pending = false;
  382. channel->enabled = true;
  383. smp_wmb();
  384. napi_enable(&channel->napi_str);
  385. /* Load up RX descriptors */
  386. efx_for_each_channel_rx_queue(rx_queue, channel)
  387. efx_fast_push_rx_descriptors(rx_queue);
  388. }
  389. /* This disables event queue processing and packet transmission.
  390. * This function does not guarantee that all queue processing
  391. * (e.g. RX refill) is complete.
  392. */
  393. static void efx_stop_channel(struct efx_channel *channel)
  394. {
  395. struct efx_rx_queue *rx_queue;
  396. if (!channel->enabled)
  397. return;
  398. EFX_LOG(channel->efx, "stop chan %d\n", channel->channel);
  399. channel->enabled = false;
  400. napi_disable(&channel->napi_str);
  401. /* Ensure that any worker threads have exited or will be no-ops */
  402. efx_for_each_channel_rx_queue(rx_queue, channel) {
  403. spin_lock_bh(&rx_queue->add_lock);
  404. spin_unlock_bh(&rx_queue->add_lock);
  405. }
  406. }
  407. static void efx_fini_channels(struct efx_nic *efx)
  408. {
  409. struct efx_channel *channel;
  410. struct efx_tx_queue *tx_queue;
  411. struct efx_rx_queue *rx_queue;
  412. int rc;
  413. EFX_ASSERT_RESET_SERIALISED(efx);
  414. BUG_ON(efx->port_enabled);
  415. rc = falcon_flush_queues(efx);
  416. if (rc)
  417. EFX_ERR(efx, "failed to flush queues\n");
  418. else
  419. EFX_LOG(efx, "successfully flushed all queues\n");
  420. efx_for_each_channel(channel, efx) {
  421. EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel);
  422. efx_for_each_channel_rx_queue(rx_queue, channel)
  423. efx_fini_rx_queue(rx_queue);
  424. efx_for_each_channel_tx_queue(tx_queue, channel)
  425. efx_fini_tx_queue(tx_queue);
  426. efx_fini_eventq(channel);
  427. }
  428. }
  429. static void efx_remove_channel(struct efx_channel *channel)
  430. {
  431. struct efx_tx_queue *tx_queue;
  432. struct efx_rx_queue *rx_queue;
  433. EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel);
  434. efx_for_each_channel_rx_queue(rx_queue, channel)
  435. efx_remove_rx_queue(rx_queue);
  436. efx_for_each_channel_tx_queue(tx_queue, channel)
  437. efx_remove_tx_queue(tx_queue);
  438. efx_remove_eventq(channel);
  439. channel->used_flags = 0;
  440. }
  441. void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue, int delay)
  442. {
  443. queue_delayed_work(refill_workqueue, &rx_queue->work, delay);
  444. }
  445. /**************************************************************************
  446. *
  447. * Port handling
  448. *
  449. **************************************************************************/
  450. /* This ensures that the kernel is kept informed (via
  451. * netif_carrier_on/off) of the link status, and also maintains the
  452. * link status's stop on the port's TX queue.
  453. */
  454. static void efx_link_status_changed(struct efx_nic *efx)
  455. {
  456. /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
  457. * that no events are triggered between unregister_netdev() and the
  458. * driver unloading. A more general condition is that NETDEV_CHANGE
  459. * can only be generated between NETDEV_UP and NETDEV_DOWN */
  460. if (!netif_running(efx->net_dev))
  461. return;
  462. if (efx->port_inhibited) {
  463. netif_carrier_off(efx->net_dev);
  464. return;
  465. }
  466. if (efx->link_up != netif_carrier_ok(efx->net_dev)) {
  467. efx->n_link_state_changes++;
  468. if (efx->link_up)
  469. netif_carrier_on(efx->net_dev);
  470. else
  471. netif_carrier_off(efx->net_dev);
  472. }
  473. /* Status message for kernel log */
  474. if (efx->link_up) {
  475. EFX_INFO(efx, "link up at %uMbps %s-duplex (MTU %d)%s\n",
  476. efx->link_speed, efx->link_fd ? "full" : "half",
  477. efx->net_dev->mtu,
  478. (efx->promiscuous ? " [PROMISC]" : ""));
  479. } else {
  480. EFX_INFO(efx, "link down\n");
  481. }
  482. }
  483. static void efx_fini_port(struct efx_nic *efx);
  484. /* This call reinitialises the MAC to pick up new PHY settings. The
  485. * caller must hold the mac_lock */
  486. void __efx_reconfigure_port(struct efx_nic *efx)
  487. {
  488. WARN_ON(!mutex_is_locked(&efx->mac_lock));
  489. EFX_LOG(efx, "reconfiguring MAC from PHY settings on CPU %d\n",
  490. raw_smp_processor_id());
  491. /* Serialise the promiscuous flag with efx_set_multicast_list. */
  492. if (efx_dev_registered(efx)) {
  493. netif_addr_lock_bh(efx->net_dev);
  494. netif_addr_unlock_bh(efx->net_dev);
  495. }
  496. falcon_deconfigure_mac_wrapper(efx);
  497. /* Reconfigure the PHY, disabling transmit in mac level loopback. */
  498. if (LOOPBACK_INTERNAL(efx))
  499. efx->phy_mode |= PHY_MODE_TX_DISABLED;
  500. else
  501. efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
  502. efx->phy_op->reconfigure(efx);
  503. if (falcon_switch_mac(efx))
  504. goto fail;
  505. efx->mac_op->reconfigure(efx);
  506. /* Inform kernel of loss/gain of carrier */
  507. efx_link_status_changed(efx);
  508. return;
  509. fail:
  510. EFX_ERR(efx, "failed to reconfigure MAC\n");
  511. efx->port_enabled = false;
  512. efx_fini_port(efx);
  513. }
  514. /* Reinitialise the MAC to pick up new PHY settings, even if the port is
  515. * disabled. */
  516. void efx_reconfigure_port(struct efx_nic *efx)
  517. {
  518. EFX_ASSERT_RESET_SERIALISED(efx);
  519. mutex_lock(&efx->mac_lock);
  520. __efx_reconfigure_port(efx);
  521. mutex_unlock(&efx->mac_lock);
  522. }
  523. /* Asynchronous efx_reconfigure_port work item. To speed up efx_flush_all()
  524. * we don't efx_reconfigure_port() if the port is disabled. Care is taken
  525. * in efx_stop_all() and efx_start_port() to prevent PHY events being lost */
  526. static void efx_phy_work(struct work_struct *data)
  527. {
  528. struct efx_nic *efx = container_of(data, struct efx_nic, phy_work);
  529. mutex_lock(&efx->mac_lock);
  530. if (efx->port_enabled)
  531. __efx_reconfigure_port(efx);
  532. mutex_unlock(&efx->mac_lock);
  533. }
  534. static void efx_mac_work(struct work_struct *data)
  535. {
  536. struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
  537. mutex_lock(&efx->mac_lock);
  538. if (efx->port_enabled)
  539. efx->mac_op->irq(efx);
  540. mutex_unlock(&efx->mac_lock);
  541. }
  542. static int efx_probe_port(struct efx_nic *efx)
  543. {
  544. int rc;
  545. EFX_LOG(efx, "create port\n");
  546. /* Connect up MAC/PHY operations table and read MAC address */
  547. rc = falcon_probe_port(efx);
  548. if (rc)
  549. goto err;
  550. if (phy_flash_cfg)
  551. efx->phy_mode = PHY_MODE_SPECIAL;
  552. /* Sanity check MAC address */
  553. if (is_valid_ether_addr(efx->mac_address)) {
  554. memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN);
  555. } else {
  556. EFX_ERR(efx, "invalid MAC address %pM\n",
  557. efx->mac_address);
  558. if (!allow_bad_hwaddr) {
  559. rc = -EINVAL;
  560. goto err;
  561. }
  562. random_ether_addr(efx->net_dev->dev_addr);
  563. EFX_INFO(efx, "using locally-generated MAC %pM\n",
  564. efx->net_dev->dev_addr);
  565. }
  566. return 0;
  567. err:
  568. efx_remove_port(efx);
  569. return rc;
  570. }
  571. static int efx_init_port(struct efx_nic *efx)
  572. {
  573. int rc;
  574. EFX_LOG(efx, "init port\n");
  575. rc = efx->phy_op->init(efx);
  576. if (rc)
  577. return rc;
  578. mutex_lock(&efx->mac_lock);
  579. efx->phy_op->reconfigure(efx);
  580. rc = falcon_switch_mac(efx);
  581. mutex_unlock(&efx->mac_lock);
  582. if (rc)
  583. goto fail;
  584. efx->mac_op->reconfigure(efx);
  585. efx->port_initialized = true;
  586. efx_stats_enable(efx);
  587. return 0;
  588. fail:
  589. efx->phy_op->fini(efx);
  590. return rc;
  591. }
  592. /* Allow efx_reconfigure_port() to be scheduled, and close the window
  593. * between efx_stop_port and efx_flush_all whereby a previously scheduled
  594. * efx_phy_work()/efx_mac_work() may have been cancelled */
  595. static void efx_start_port(struct efx_nic *efx)
  596. {
  597. EFX_LOG(efx, "start port\n");
  598. BUG_ON(efx->port_enabled);
  599. mutex_lock(&efx->mac_lock);
  600. efx->port_enabled = true;
  601. __efx_reconfigure_port(efx);
  602. efx->mac_op->irq(efx);
  603. mutex_unlock(&efx->mac_lock);
  604. }
  605. /* Prevent efx_phy_work, efx_mac_work, and efx_monitor() from executing,
  606. * and efx_set_multicast_list() from scheduling efx_phy_work. efx_phy_work
  607. * and efx_mac_work may still be scheduled via NAPI processing until
  608. * efx_flush_all() is called */
  609. static void efx_stop_port(struct efx_nic *efx)
  610. {
  611. EFX_LOG(efx, "stop port\n");
  612. mutex_lock(&efx->mac_lock);
  613. efx->port_enabled = false;
  614. mutex_unlock(&efx->mac_lock);
  615. /* Serialise against efx_set_multicast_list() */
  616. if (efx_dev_registered(efx)) {
  617. netif_addr_lock_bh(efx->net_dev);
  618. netif_addr_unlock_bh(efx->net_dev);
  619. }
  620. }
  621. static void efx_fini_port(struct efx_nic *efx)
  622. {
  623. EFX_LOG(efx, "shut down port\n");
  624. if (!efx->port_initialized)
  625. return;
  626. efx_stats_disable(efx);
  627. efx->phy_op->fini(efx);
  628. efx->port_initialized = false;
  629. efx->link_up = false;
  630. efx_link_status_changed(efx);
  631. }
  632. static void efx_remove_port(struct efx_nic *efx)
  633. {
  634. EFX_LOG(efx, "destroying port\n");
  635. falcon_remove_port(efx);
  636. }
  637. /**************************************************************************
  638. *
  639. * NIC handling
  640. *
  641. **************************************************************************/
  642. /* This configures the PCI device to enable I/O and DMA. */
  643. static int efx_init_io(struct efx_nic *efx)
  644. {
  645. struct pci_dev *pci_dev = efx->pci_dev;
  646. dma_addr_t dma_mask = efx->type->max_dma_mask;
  647. int rc;
  648. EFX_LOG(efx, "initialising I/O\n");
  649. rc = pci_enable_device(pci_dev);
  650. if (rc) {
  651. EFX_ERR(efx, "failed to enable PCI device\n");
  652. goto fail1;
  653. }
  654. pci_set_master(pci_dev);
  655. /* Set the PCI DMA mask. Try all possibilities from our
  656. * genuine mask down to 32 bits, because some architectures
  657. * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
  658. * masks event though they reject 46 bit masks.
  659. */
  660. while (dma_mask > 0x7fffffffUL) {
  661. if (pci_dma_supported(pci_dev, dma_mask) &&
  662. ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0))
  663. break;
  664. dma_mask >>= 1;
  665. }
  666. if (rc) {
  667. EFX_ERR(efx, "could not find a suitable DMA mask\n");
  668. goto fail2;
  669. }
  670. EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask);
  671. rc = pci_set_consistent_dma_mask(pci_dev, dma_mask);
  672. if (rc) {
  673. /* pci_set_consistent_dma_mask() is not *allowed* to
  674. * fail with a mask that pci_set_dma_mask() accepted,
  675. * but just in case...
  676. */
  677. EFX_ERR(efx, "failed to set consistent DMA mask\n");
  678. goto fail2;
  679. }
  680. efx->membase_phys = pci_resource_start(efx->pci_dev,
  681. efx->type->mem_bar);
  682. rc = pci_request_region(pci_dev, efx->type->mem_bar, "sfc");
  683. if (rc) {
  684. EFX_ERR(efx, "request for memory BAR failed\n");
  685. rc = -EIO;
  686. goto fail3;
  687. }
  688. efx->membase = ioremap_nocache(efx->membase_phys,
  689. efx->type->mem_map_size);
  690. if (!efx->membase) {
  691. EFX_ERR(efx, "could not map memory BAR %d at %llx+%x\n",
  692. efx->type->mem_bar,
  693. (unsigned long long)efx->membase_phys,
  694. efx->type->mem_map_size);
  695. rc = -ENOMEM;
  696. goto fail4;
  697. }
  698. EFX_LOG(efx, "memory BAR %u at %llx+%x (virtual %p)\n",
  699. efx->type->mem_bar, (unsigned long long)efx->membase_phys,
  700. efx->type->mem_map_size, efx->membase);
  701. return 0;
  702. fail4:
  703. pci_release_region(efx->pci_dev, efx->type->mem_bar);
  704. fail3:
  705. efx->membase_phys = 0;
  706. fail2:
  707. pci_disable_device(efx->pci_dev);
  708. fail1:
  709. return rc;
  710. }
  711. static void efx_fini_io(struct efx_nic *efx)
  712. {
  713. EFX_LOG(efx, "shutting down I/O\n");
  714. if (efx->membase) {
  715. iounmap(efx->membase);
  716. efx->membase = NULL;
  717. }
  718. if (efx->membase_phys) {
  719. pci_release_region(efx->pci_dev, efx->type->mem_bar);
  720. efx->membase_phys = 0;
  721. }
  722. pci_disable_device(efx->pci_dev);
  723. }
  724. /* Get number of RX queues wanted. Return number of online CPU
  725. * packages in the expectation that an IRQ balancer will spread
  726. * interrupts across them. */
  727. static int efx_wanted_rx_queues(void)
  728. {
  729. cpumask_var_t core_mask;
  730. int count;
  731. int cpu;
  732. if (unlikely(!alloc_cpumask_var(&core_mask, GFP_KERNEL))) {
  733. printk(KERN_WARNING
  734. "sfc: RSS disabled due to allocation failure\n");
  735. return 1;
  736. }
  737. cpumask_clear(core_mask);
  738. count = 0;
  739. for_each_online_cpu(cpu) {
  740. if (!cpumask_test_cpu(cpu, core_mask)) {
  741. ++count;
  742. cpumask_or(core_mask, core_mask,
  743. topology_core_cpumask(cpu));
  744. }
  745. }
  746. free_cpumask_var(core_mask);
  747. return count;
  748. }
  749. /* Probe the number and type of interrupts we are able to obtain, and
  750. * the resulting numbers of channels and RX queues.
  751. */
  752. static void efx_probe_interrupts(struct efx_nic *efx)
  753. {
  754. int max_channels =
  755. min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS);
  756. int rc, i;
  757. if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
  758. struct msix_entry xentries[EFX_MAX_CHANNELS];
  759. int wanted_ints;
  760. int rx_queues;
  761. /* We want one RX queue and interrupt per CPU package
  762. * (or as specified by the rss_cpus module parameter).
  763. * We will need one channel per interrupt.
  764. */
  765. rx_queues = rss_cpus ? rss_cpus : efx_wanted_rx_queues();
  766. wanted_ints = rx_queues + (separate_tx_channels ? 1 : 0);
  767. wanted_ints = min(wanted_ints, max_channels);
  768. for (i = 0; i < wanted_ints; i++)
  769. xentries[i].entry = i;
  770. rc = pci_enable_msix(efx->pci_dev, xentries, wanted_ints);
  771. if (rc > 0) {
  772. EFX_ERR(efx, "WARNING: Insufficient MSI-X vectors"
  773. " available (%d < %d).\n", rc, wanted_ints);
  774. EFX_ERR(efx, "WARNING: Performance may be reduced.\n");
  775. EFX_BUG_ON_PARANOID(rc >= wanted_ints);
  776. wanted_ints = rc;
  777. rc = pci_enable_msix(efx->pci_dev, xentries,
  778. wanted_ints);
  779. }
  780. if (rc == 0) {
  781. efx->n_rx_queues = min(rx_queues, wanted_ints);
  782. efx->n_channels = wanted_ints;
  783. for (i = 0; i < wanted_ints; i++)
  784. efx->channel[i].irq = xentries[i].vector;
  785. } else {
  786. /* Fall back to single channel MSI */
  787. efx->interrupt_mode = EFX_INT_MODE_MSI;
  788. EFX_ERR(efx, "could not enable MSI-X\n");
  789. }
  790. }
  791. /* Try single interrupt MSI */
  792. if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
  793. efx->n_rx_queues = 1;
  794. efx->n_channels = 1;
  795. rc = pci_enable_msi(efx->pci_dev);
  796. if (rc == 0) {
  797. efx->channel[0].irq = efx->pci_dev->irq;
  798. } else {
  799. EFX_ERR(efx, "could not enable MSI\n");
  800. efx->interrupt_mode = EFX_INT_MODE_LEGACY;
  801. }
  802. }
  803. /* Assume legacy interrupts */
  804. if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
  805. efx->n_rx_queues = 1;
  806. efx->n_channels = 1 + (separate_tx_channels ? 1 : 0);
  807. efx->legacy_irq = efx->pci_dev->irq;
  808. }
  809. }
  810. static void efx_remove_interrupts(struct efx_nic *efx)
  811. {
  812. struct efx_channel *channel;
  813. /* Remove MSI/MSI-X interrupts */
  814. efx_for_each_channel(channel, efx)
  815. channel->irq = 0;
  816. pci_disable_msi(efx->pci_dev);
  817. pci_disable_msix(efx->pci_dev);
  818. /* Remove legacy interrupt */
  819. efx->legacy_irq = 0;
  820. }
  821. static void efx_set_channels(struct efx_nic *efx)
  822. {
  823. struct efx_tx_queue *tx_queue;
  824. struct efx_rx_queue *rx_queue;
  825. efx_for_each_tx_queue(tx_queue, efx) {
  826. if (separate_tx_channels)
  827. tx_queue->channel = &efx->channel[efx->n_channels-1];
  828. else
  829. tx_queue->channel = &efx->channel[0];
  830. tx_queue->channel->used_flags |= EFX_USED_BY_TX;
  831. }
  832. efx_for_each_rx_queue(rx_queue, efx) {
  833. rx_queue->channel = &efx->channel[rx_queue->queue];
  834. rx_queue->channel->used_flags |= EFX_USED_BY_RX;
  835. }
  836. }
  837. static int efx_probe_nic(struct efx_nic *efx)
  838. {
  839. int rc;
  840. EFX_LOG(efx, "creating NIC\n");
  841. /* Carry out hardware-type specific initialisation */
  842. rc = falcon_probe_nic(efx);
  843. if (rc)
  844. return rc;
  845. /* Determine the number of channels and RX queues by trying to hook
  846. * in MSI-X interrupts. */
  847. efx_probe_interrupts(efx);
  848. efx_set_channels(efx);
  849. /* Initialise the interrupt moderation settings */
  850. efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true);
  851. return 0;
  852. }
  853. static void efx_remove_nic(struct efx_nic *efx)
  854. {
  855. EFX_LOG(efx, "destroying NIC\n");
  856. efx_remove_interrupts(efx);
  857. falcon_remove_nic(efx);
  858. }
  859. /**************************************************************************
  860. *
  861. * NIC startup/shutdown
  862. *
  863. *************************************************************************/
  864. static int efx_probe_all(struct efx_nic *efx)
  865. {
  866. struct efx_channel *channel;
  867. int rc;
  868. /* Create NIC */
  869. rc = efx_probe_nic(efx);
  870. if (rc) {
  871. EFX_ERR(efx, "failed to create NIC\n");
  872. goto fail1;
  873. }
  874. /* Create port */
  875. rc = efx_probe_port(efx);
  876. if (rc) {
  877. EFX_ERR(efx, "failed to create port\n");
  878. goto fail2;
  879. }
  880. /* Create channels */
  881. efx_for_each_channel(channel, efx) {
  882. rc = efx_probe_channel(channel);
  883. if (rc) {
  884. EFX_ERR(efx, "failed to create channel %d\n",
  885. channel->channel);
  886. goto fail3;
  887. }
  888. }
  889. efx_set_channel_names(efx);
  890. return 0;
  891. fail3:
  892. efx_for_each_channel(channel, efx)
  893. efx_remove_channel(channel);
  894. efx_remove_port(efx);
  895. fail2:
  896. efx_remove_nic(efx);
  897. fail1:
  898. return rc;
  899. }
  900. /* Called after previous invocation(s) of efx_stop_all, restarts the
  901. * port, kernel transmit queue, NAPI processing and hardware interrupts,
  902. * and ensures that the port is scheduled to be reconfigured.
  903. * This function is safe to call multiple times when the NIC is in any
  904. * state. */
  905. static void efx_start_all(struct efx_nic *efx)
  906. {
  907. struct efx_channel *channel;
  908. EFX_ASSERT_RESET_SERIALISED(efx);
  909. /* Check that it is appropriate to restart the interface. All
  910. * of these flags are safe to read under just the rtnl lock */
  911. if (efx->port_enabled)
  912. return;
  913. if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT))
  914. return;
  915. if (efx_dev_registered(efx) && !netif_running(efx->net_dev))
  916. return;
  917. /* Mark the port as enabled so port reconfigurations can start, then
  918. * restart the transmit interface early so the watchdog timer stops */
  919. efx_start_port(efx);
  920. if (efx_dev_registered(efx))
  921. efx_wake_queue(efx);
  922. efx_for_each_channel(channel, efx)
  923. efx_start_channel(channel);
  924. falcon_enable_interrupts(efx);
  925. /* Start hardware monitor if we're in RUNNING */
  926. if (efx->state == STATE_RUNNING)
  927. queue_delayed_work(efx->workqueue, &efx->monitor_work,
  928. efx_monitor_interval);
  929. }
  930. /* Flush all delayed work. Should only be called when no more delayed work
  931. * will be scheduled. This doesn't flush pending online resets (efx_reset),
  932. * since we're holding the rtnl_lock at this point. */
  933. static void efx_flush_all(struct efx_nic *efx)
  934. {
  935. struct efx_rx_queue *rx_queue;
  936. /* Make sure the hardware monitor is stopped */
  937. cancel_delayed_work_sync(&efx->monitor_work);
  938. /* Ensure that all RX slow refills are complete. */
  939. efx_for_each_rx_queue(rx_queue, efx)
  940. cancel_delayed_work_sync(&rx_queue->work);
  941. /* Stop scheduled port reconfigurations */
  942. cancel_work_sync(&efx->mac_work);
  943. cancel_work_sync(&efx->phy_work);
  944. }
  945. /* Quiesce hardware and software without bringing the link down.
  946. * Safe to call multiple times, when the nic and interface is in any
  947. * state. The caller is guaranteed to subsequently be in a position
  948. * to modify any hardware and software state they see fit without
  949. * taking locks. */
  950. static void efx_stop_all(struct efx_nic *efx)
  951. {
  952. struct efx_channel *channel;
  953. EFX_ASSERT_RESET_SERIALISED(efx);
  954. /* port_enabled can be read safely under the rtnl lock */
  955. if (!efx->port_enabled)
  956. return;
  957. /* Disable interrupts and wait for ISR to complete */
  958. falcon_disable_interrupts(efx);
  959. if (efx->legacy_irq)
  960. synchronize_irq(efx->legacy_irq);
  961. efx_for_each_channel(channel, efx) {
  962. if (channel->irq)
  963. synchronize_irq(channel->irq);
  964. }
  965. /* Stop all NAPI processing and synchronous rx refills */
  966. efx_for_each_channel(channel, efx)
  967. efx_stop_channel(channel);
  968. /* Stop all asynchronous port reconfigurations. Since all
  969. * event processing has already been stopped, there is no
  970. * window to loose phy events */
  971. efx_stop_port(efx);
  972. /* Flush efx_phy_work, efx_mac_work, refill_workqueue, monitor_work */
  973. efx_flush_all(efx);
  974. /* Isolate the MAC from the TX and RX engines, so that queue
  975. * flushes will complete in a timely fashion. */
  976. falcon_deconfigure_mac_wrapper(efx);
  977. msleep(10); /* Let the Rx FIFO drain */
  978. falcon_drain_tx_fifo(efx);
  979. /* Stop the kernel transmit interface late, so the watchdog
  980. * timer isn't ticking over the flush */
  981. if (efx_dev_registered(efx)) {
  982. efx_stop_queue(efx);
  983. netif_tx_lock_bh(efx->net_dev);
  984. netif_tx_unlock_bh(efx->net_dev);
  985. }
  986. }
  987. static void efx_remove_all(struct efx_nic *efx)
  988. {
  989. struct efx_channel *channel;
  990. efx_for_each_channel(channel, efx)
  991. efx_remove_channel(channel);
  992. efx_remove_port(efx);
  993. efx_remove_nic(efx);
  994. }
  995. /* A convinience function to safely flush all the queues */
  996. void efx_flush_queues(struct efx_nic *efx)
  997. {
  998. EFX_ASSERT_RESET_SERIALISED(efx);
  999. efx_stop_all(efx);
  1000. efx_fini_channels(efx);
  1001. efx_init_channels(efx);
  1002. efx_start_all(efx);
  1003. }
  1004. /**************************************************************************
  1005. *
  1006. * Interrupt moderation
  1007. *
  1008. **************************************************************************/
  1009. /* Set interrupt moderation parameters */
  1010. void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs,
  1011. bool rx_adaptive)
  1012. {
  1013. struct efx_tx_queue *tx_queue;
  1014. struct efx_rx_queue *rx_queue;
  1015. EFX_ASSERT_RESET_SERIALISED(efx);
  1016. efx_for_each_tx_queue(tx_queue, efx)
  1017. tx_queue->channel->irq_moderation = tx_usecs;
  1018. efx->irq_rx_adaptive = rx_adaptive;
  1019. efx->irq_rx_moderation = rx_usecs;
  1020. efx_for_each_rx_queue(rx_queue, efx)
  1021. rx_queue->channel->irq_moderation = rx_usecs;
  1022. }
  1023. /**************************************************************************
  1024. *
  1025. * Hardware monitor
  1026. *
  1027. **************************************************************************/
  1028. /* Run periodically off the general workqueue. Serialised against
  1029. * efx_reconfigure_port via the mac_lock */
  1030. static void efx_monitor(struct work_struct *data)
  1031. {
  1032. struct efx_nic *efx = container_of(data, struct efx_nic,
  1033. monitor_work.work);
  1034. int rc;
  1035. EFX_TRACE(efx, "hardware monitor executing on CPU %d\n",
  1036. raw_smp_processor_id());
  1037. /* If the mac_lock is already held then it is likely a port
  1038. * reconfiguration is already in place, which will likely do
  1039. * most of the work of check_hw() anyway. */
  1040. if (!mutex_trylock(&efx->mac_lock))
  1041. goto out_requeue;
  1042. if (!efx->port_enabled)
  1043. goto out_unlock;
  1044. rc = efx->board_info.monitor(efx);
  1045. if (rc) {
  1046. EFX_ERR(efx, "Board sensor %s; shutting down PHY\n",
  1047. (rc == -ERANGE) ? "reported fault" : "failed");
  1048. efx->phy_mode |= PHY_MODE_LOW_POWER;
  1049. falcon_sim_phy_event(efx);
  1050. }
  1051. efx->phy_op->poll(efx);
  1052. efx->mac_op->poll(efx);
  1053. out_unlock:
  1054. mutex_unlock(&efx->mac_lock);
  1055. out_requeue:
  1056. queue_delayed_work(efx->workqueue, &efx->monitor_work,
  1057. efx_monitor_interval);
  1058. }
  1059. /**************************************************************************
  1060. *
  1061. * ioctls
  1062. *
  1063. *************************************************************************/
  1064. /* Net device ioctl
  1065. * Context: process, rtnl_lock() held.
  1066. */
  1067. static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
  1068. {
  1069. struct efx_nic *efx = netdev_priv(net_dev);
  1070. struct mii_ioctl_data *data = if_mii(ifr);
  1071. EFX_ASSERT_RESET_SERIALISED(efx);
  1072. /* Convert phy_id from older PRTAD/DEVAD format */
  1073. if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &&
  1074. (data->phy_id & 0xfc00) == 0x0400)
  1075. data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400;
  1076. return mdio_mii_ioctl(&efx->mdio, data, cmd);
  1077. }
  1078. /**************************************************************************
  1079. *
  1080. * NAPI interface
  1081. *
  1082. **************************************************************************/
  1083. static int efx_init_napi(struct efx_nic *efx)
  1084. {
  1085. struct efx_channel *channel;
  1086. efx_for_each_channel(channel, efx) {
  1087. channel->napi_dev = efx->net_dev;
  1088. netif_napi_add(channel->napi_dev, &channel->napi_str,
  1089. efx_poll, napi_weight);
  1090. }
  1091. return 0;
  1092. }
  1093. static void efx_fini_napi(struct efx_nic *efx)
  1094. {
  1095. struct efx_channel *channel;
  1096. efx_for_each_channel(channel, efx) {
  1097. if (channel->napi_dev)
  1098. netif_napi_del(&channel->napi_str);
  1099. channel->napi_dev = NULL;
  1100. }
  1101. }
  1102. /**************************************************************************
  1103. *
  1104. * Kernel netpoll interface
  1105. *
  1106. *************************************************************************/
  1107. #ifdef CONFIG_NET_POLL_CONTROLLER
  1108. /* Although in the common case interrupts will be disabled, this is not
  1109. * guaranteed. However, all our work happens inside the NAPI callback,
  1110. * so no locking is required.
  1111. */
  1112. static void efx_netpoll(struct net_device *net_dev)
  1113. {
  1114. struct efx_nic *efx = netdev_priv(net_dev);
  1115. struct efx_channel *channel;
  1116. efx_for_each_channel(channel, efx)
  1117. efx_schedule_channel(channel);
  1118. }
  1119. #endif
  1120. /**************************************************************************
  1121. *
  1122. * Kernel net device interface
  1123. *
  1124. *************************************************************************/
  1125. /* Context: process, rtnl_lock() held. */
  1126. static int efx_net_open(struct net_device *net_dev)
  1127. {
  1128. struct efx_nic *efx = netdev_priv(net_dev);
  1129. EFX_ASSERT_RESET_SERIALISED(efx);
  1130. EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name,
  1131. raw_smp_processor_id());
  1132. if (efx->state == STATE_DISABLED)
  1133. return -EIO;
  1134. if (efx->phy_mode & PHY_MODE_SPECIAL)
  1135. return -EBUSY;
  1136. efx_start_all(efx);
  1137. return 0;
  1138. }
  1139. /* Context: process, rtnl_lock() held.
  1140. * Note that the kernel will ignore our return code; this method
  1141. * should really be a void.
  1142. */
  1143. static int efx_net_stop(struct net_device *net_dev)
  1144. {
  1145. struct efx_nic *efx = netdev_priv(net_dev);
  1146. EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name,
  1147. raw_smp_processor_id());
  1148. if (efx->state != STATE_DISABLED) {
  1149. /* Stop the device and flush all the channels */
  1150. efx_stop_all(efx);
  1151. efx_fini_channels(efx);
  1152. efx_init_channels(efx);
  1153. }
  1154. return 0;
  1155. }
  1156. void efx_stats_disable(struct efx_nic *efx)
  1157. {
  1158. spin_lock(&efx->stats_lock);
  1159. ++efx->stats_disable_count;
  1160. spin_unlock(&efx->stats_lock);
  1161. }
  1162. void efx_stats_enable(struct efx_nic *efx)
  1163. {
  1164. spin_lock(&efx->stats_lock);
  1165. --efx->stats_disable_count;
  1166. spin_unlock(&efx->stats_lock);
  1167. }
  1168. /* Context: process, dev_base_lock or RTNL held, non-blocking. */
  1169. static struct net_device_stats *efx_net_stats(struct net_device *net_dev)
  1170. {
  1171. struct efx_nic *efx = netdev_priv(net_dev);
  1172. struct efx_mac_stats *mac_stats = &efx->mac_stats;
  1173. struct net_device_stats *stats = &net_dev->stats;
  1174. /* Update stats if possible, but do not wait if another thread
  1175. * is updating them or if MAC stats fetches are temporarily
  1176. * disabled; slightly stale stats are acceptable.
  1177. */
  1178. if (!spin_trylock(&efx->stats_lock))
  1179. return stats;
  1180. if (!efx->stats_disable_count) {
  1181. efx->mac_op->update_stats(efx);
  1182. falcon_update_nic_stats(efx);
  1183. }
  1184. spin_unlock(&efx->stats_lock);
  1185. stats->rx_packets = mac_stats->rx_packets;
  1186. stats->tx_packets = mac_stats->tx_packets;
  1187. stats->rx_bytes = mac_stats->rx_bytes;
  1188. stats->tx_bytes = mac_stats->tx_bytes;
  1189. stats->multicast = mac_stats->rx_multicast;
  1190. stats->collisions = mac_stats->tx_collision;
  1191. stats->rx_length_errors = (mac_stats->rx_gtjumbo +
  1192. mac_stats->rx_length_error);
  1193. stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt;
  1194. stats->rx_crc_errors = mac_stats->rx_bad;
  1195. stats->rx_frame_errors = mac_stats->rx_align_error;
  1196. stats->rx_fifo_errors = mac_stats->rx_overflow;
  1197. stats->rx_missed_errors = mac_stats->rx_missed;
  1198. stats->tx_window_errors = mac_stats->tx_late_collision;
  1199. stats->rx_errors = (stats->rx_length_errors +
  1200. stats->rx_over_errors +
  1201. stats->rx_crc_errors +
  1202. stats->rx_frame_errors +
  1203. stats->rx_fifo_errors +
  1204. stats->rx_missed_errors +
  1205. mac_stats->rx_symbol_error);
  1206. stats->tx_errors = (stats->tx_window_errors +
  1207. mac_stats->tx_bad);
  1208. return stats;
  1209. }
  1210. /* Context: netif_tx_lock held, BHs disabled. */
  1211. static void efx_watchdog(struct net_device *net_dev)
  1212. {
  1213. struct efx_nic *efx = netdev_priv(net_dev);
  1214. EFX_ERR(efx, "TX stuck with stop_count=%d port_enabled=%d:"
  1215. " resetting channels\n",
  1216. atomic_read(&efx->netif_stop_count), efx->port_enabled);
  1217. efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
  1218. }
  1219. /* Context: process, rtnl_lock() held. */
  1220. static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
  1221. {
  1222. struct efx_nic *efx = netdev_priv(net_dev);
  1223. int rc = 0;
  1224. EFX_ASSERT_RESET_SERIALISED(efx);
  1225. if (new_mtu > EFX_MAX_MTU)
  1226. return -EINVAL;
  1227. efx_stop_all(efx);
  1228. EFX_LOG(efx, "changing MTU to %d\n", new_mtu);
  1229. efx_fini_channels(efx);
  1230. net_dev->mtu = new_mtu;
  1231. efx_init_channels(efx);
  1232. efx_start_all(efx);
  1233. return rc;
  1234. }
  1235. static int efx_set_mac_address(struct net_device *net_dev, void *data)
  1236. {
  1237. struct efx_nic *efx = netdev_priv(net_dev);
  1238. struct sockaddr *addr = data;
  1239. char *new_addr = addr->sa_data;
  1240. EFX_ASSERT_RESET_SERIALISED(efx);
  1241. if (!is_valid_ether_addr(new_addr)) {
  1242. EFX_ERR(efx, "invalid ethernet MAC address requested: %pM\n",
  1243. new_addr);
  1244. return -EINVAL;
  1245. }
  1246. memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len);
  1247. /* Reconfigure the MAC */
  1248. efx_reconfigure_port(efx);
  1249. return 0;
  1250. }
  1251. /* Context: netif_addr_lock held, BHs disabled. */
  1252. static void efx_set_multicast_list(struct net_device *net_dev)
  1253. {
  1254. struct efx_nic *efx = netdev_priv(net_dev);
  1255. struct dev_mc_list *mc_list = net_dev->mc_list;
  1256. union efx_multicast_hash *mc_hash = &efx->multicast_hash;
  1257. bool promiscuous = !!(net_dev->flags & IFF_PROMISC);
  1258. bool changed = (efx->promiscuous != promiscuous);
  1259. u32 crc;
  1260. int bit;
  1261. int i;
  1262. efx->promiscuous = promiscuous;
  1263. /* Build multicast hash table */
  1264. if (promiscuous || (net_dev->flags & IFF_ALLMULTI)) {
  1265. memset(mc_hash, 0xff, sizeof(*mc_hash));
  1266. } else {
  1267. memset(mc_hash, 0x00, sizeof(*mc_hash));
  1268. for (i = 0; i < net_dev->mc_count; i++) {
  1269. crc = ether_crc_le(ETH_ALEN, mc_list->dmi_addr);
  1270. bit = crc & (EFX_MCAST_HASH_ENTRIES - 1);
  1271. set_bit_le(bit, mc_hash->byte);
  1272. mc_list = mc_list->next;
  1273. }
  1274. }
  1275. if (!efx->port_enabled)
  1276. /* Delay pushing settings until efx_start_port() */
  1277. return;
  1278. if (changed)
  1279. queue_work(efx->workqueue, &efx->phy_work);
  1280. /* Create and activate new global multicast hash table */
  1281. falcon_set_multicast_hash(efx);
  1282. }
  1283. static const struct net_device_ops efx_netdev_ops = {
  1284. .ndo_open = efx_net_open,
  1285. .ndo_stop = efx_net_stop,
  1286. .ndo_get_stats = efx_net_stats,
  1287. .ndo_tx_timeout = efx_watchdog,
  1288. .ndo_start_xmit = efx_hard_start_xmit,
  1289. .ndo_validate_addr = eth_validate_addr,
  1290. .ndo_do_ioctl = efx_ioctl,
  1291. .ndo_change_mtu = efx_change_mtu,
  1292. .ndo_set_mac_address = efx_set_mac_address,
  1293. .ndo_set_multicast_list = efx_set_multicast_list,
  1294. #ifdef CONFIG_NET_POLL_CONTROLLER
  1295. .ndo_poll_controller = efx_netpoll,
  1296. #endif
  1297. };
  1298. static void efx_update_name(struct efx_nic *efx)
  1299. {
  1300. strcpy(efx->name, efx->net_dev->name);
  1301. efx_mtd_rename(efx);
  1302. efx_set_channel_names(efx);
  1303. }
  1304. static int efx_netdev_event(struct notifier_block *this,
  1305. unsigned long event, void *ptr)
  1306. {
  1307. struct net_device *net_dev = ptr;
  1308. if (net_dev->netdev_ops == &efx_netdev_ops &&
  1309. event == NETDEV_CHANGENAME)
  1310. efx_update_name(netdev_priv(net_dev));
  1311. return NOTIFY_DONE;
  1312. }
  1313. static struct notifier_block efx_netdev_notifier = {
  1314. .notifier_call = efx_netdev_event,
  1315. };
  1316. static ssize_t
  1317. show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
  1318. {
  1319. struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
  1320. return sprintf(buf, "%d\n", efx->phy_type);
  1321. }
  1322. static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL);
  1323. static int efx_register_netdev(struct efx_nic *efx)
  1324. {
  1325. struct net_device *net_dev = efx->net_dev;
  1326. int rc;
  1327. net_dev->watchdog_timeo = 5 * HZ;
  1328. net_dev->irq = efx->pci_dev->irq;
  1329. net_dev->netdev_ops = &efx_netdev_ops;
  1330. SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev);
  1331. SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops);
  1332. /* Clear MAC statistics */
  1333. efx->mac_op->update_stats(efx);
  1334. memset(&efx->mac_stats, 0, sizeof(efx->mac_stats));
  1335. rtnl_lock();
  1336. rc = dev_alloc_name(net_dev, net_dev->name);
  1337. if (rc < 0)
  1338. goto fail_locked;
  1339. efx_update_name(efx);
  1340. rc = register_netdevice(net_dev);
  1341. if (rc)
  1342. goto fail_locked;
  1343. /* Always start with carrier off; PHY events will detect the link */
  1344. netif_carrier_off(efx->net_dev);
  1345. rtnl_unlock();
  1346. rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type);
  1347. if (rc) {
  1348. EFX_ERR(efx, "failed to init net dev attributes\n");
  1349. goto fail_registered;
  1350. }
  1351. return 0;
  1352. fail_locked:
  1353. rtnl_unlock();
  1354. EFX_ERR(efx, "could not register net dev\n");
  1355. return rc;
  1356. fail_registered:
  1357. unregister_netdev(net_dev);
  1358. return rc;
  1359. }
  1360. static void efx_unregister_netdev(struct efx_nic *efx)
  1361. {
  1362. struct efx_tx_queue *tx_queue;
  1363. if (!efx->net_dev)
  1364. return;
  1365. BUG_ON(netdev_priv(efx->net_dev) != efx);
  1366. /* Free up any skbs still remaining. This has to happen before
  1367. * we try to unregister the netdev as running their destructors
  1368. * may be needed to get the device ref. count to 0. */
  1369. efx_for_each_tx_queue(tx_queue, efx)
  1370. efx_release_tx_buffers(tx_queue);
  1371. if (efx_dev_registered(efx)) {
  1372. strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
  1373. device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
  1374. unregister_netdev(efx->net_dev);
  1375. }
  1376. }
  1377. /**************************************************************************
  1378. *
  1379. * Device reset and suspend
  1380. *
  1381. **************************************************************************/
  1382. /* Tears down the entire software state and most of the hardware state
  1383. * before reset. */
  1384. void efx_reset_down(struct efx_nic *efx, enum reset_type method,
  1385. struct ethtool_cmd *ecmd)
  1386. {
  1387. EFX_ASSERT_RESET_SERIALISED(efx);
  1388. efx_stats_disable(efx);
  1389. efx_stop_all(efx);
  1390. mutex_lock(&efx->mac_lock);
  1391. mutex_lock(&efx->spi_lock);
  1392. efx->phy_op->get_settings(efx, ecmd);
  1393. efx_fini_channels(efx);
  1394. if (efx->port_initialized && method != RESET_TYPE_INVISIBLE)
  1395. efx->phy_op->fini(efx);
  1396. }
  1397. /* This function will always ensure that the locks acquired in
  1398. * efx_reset_down() are released. A failure return code indicates
  1399. * that we were unable to reinitialise the hardware, and the
  1400. * driver should be disabled. If ok is false, then the rx and tx
  1401. * engines are not restarted, pending a RESET_DISABLE. */
  1402. int efx_reset_up(struct efx_nic *efx, enum reset_type method,
  1403. struct ethtool_cmd *ecmd, bool ok)
  1404. {
  1405. int rc;
  1406. EFX_ASSERT_RESET_SERIALISED(efx);
  1407. rc = falcon_init_nic(efx);
  1408. if (rc) {
  1409. EFX_ERR(efx, "failed to initialise NIC\n");
  1410. ok = false;
  1411. }
  1412. if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) {
  1413. if (ok) {
  1414. rc = efx->phy_op->init(efx);
  1415. if (rc)
  1416. ok = false;
  1417. }
  1418. if (!ok)
  1419. efx->port_initialized = false;
  1420. }
  1421. if (ok) {
  1422. efx_init_channels(efx);
  1423. if (efx->phy_op->set_settings(efx, ecmd))
  1424. EFX_ERR(efx, "could not restore PHY settings\n");
  1425. }
  1426. mutex_unlock(&efx->spi_lock);
  1427. mutex_unlock(&efx->mac_lock);
  1428. if (ok) {
  1429. efx_start_all(efx);
  1430. efx_stats_enable(efx);
  1431. }
  1432. return rc;
  1433. }
  1434. /* Reset the NIC as transparently as possible. Do not reset the PHY
  1435. * Note that the reset may fail, in which case the card will be left
  1436. * in a most-probably-unusable state.
  1437. *
  1438. * This function will sleep. You cannot reset from within an atomic
  1439. * state; use efx_schedule_reset() instead.
  1440. *
  1441. * Grabs the rtnl_lock.
  1442. */
  1443. static int efx_reset(struct efx_nic *efx)
  1444. {
  1445. struct ethtool_cmd ecmd;
  1446. enum reset_type method = efx->reset_pending;
  1447. int rc = 0;
  1448. /* Serialise with kernel interfaces */
  1449. rtnl_lock();
  1450. /* If we're not RUNNING then don't reset. Leave the reset_pending
  1451. * flag set so that efx_pci_probe_main will be retried */
  1452. if (efx->state != STATE_RUNNING) {
  1453. EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n");
  1454. goto out_unlock;
  1455. }
  1456. EFX_INFO(efx, "resetting (%d)\n", method);
  1457. efx_reset_down(efx, method, &ecmd);
  1458. rc = falcon_reset_hw(efx, method);
  1459. if (rc) {
  1460. EFX_ERR(efx, "failed to reset hardware\n");
  1461. goto out_disable;
  1462. }
  1463. /* Allow resets to be rescheduled. */
  1464. efx->reset_pending = RESET_TYPE_NONE;
  1465. /* Reinitialise bus-mastering, which may have been turned off before
  1466. * the reset was scheduled. This is still appropriate, even in the
  1467. * RESET_TYPE_DISABLE since this driver generally assumes the hardware
  1468. * can respond to requests. */
  1469. pci_set_master(efx->pci_dev);
  1470. /* Leave device stopped if necessary */
  1471. if (method == RESET_TYPE_DISABLE) {
  1472. efx_reset_up(efx, method, &ecmd, false);
  1473. rc = -EIO;
  1474. } else {
  1475. rc = efx_reset_up(efx, method, &ecmd, true);
  1476. }
  1477. out_disable:
  1478. if (rc) {
  1479. EFX_ERR(efx, "has been disabled\n");
  1480. efx->state = STATE_DISABLED;
  1481. dev_close(efx->net_dev);
  1482. } else {
  1483. EFX_LOG(efx, "reset complete\n");
  1484. }
  1485. out_unlock:
  1486. rtnl_unlock();
  1487. return rc;
  1488. }
  1489. /* The worker thread exists so that code that cannot sleep can
  1490. * schedule a reset for later.
  1491. */
  1492. static void efx_reset_work(struct work_struct *data)
  1493. {
  1494. struct efx_nic *nic = container_of(data, struct efx_nic, reset_work);
  1495. efx_reset(nic);
  1496. }
  1497. void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
  1498. {
  1499. enum reset_type method;
  1500. if (efx->reset_pending != RESET_TYPE_NONE) {
  1501. EFX_INFO(efx, "quenching already scheduled reset\n");
  1502. return;
  1503. }
  1504. switch (type) {
  1505. case RESET_TYPE_INVISIBLE:
  1506. case RESET_TYPE_ALL:
  1507. case RESET_TYPE_WORLD:
  1508. case RESET_TYPE_DISABLE:
  1509. method = type;
  1510. break;
  1511. case RESET_TYPE_RX_RECOVERY:
  1512. case RESET_TYPE_RX_DESC_FETCH:
  1513. case RESET_TYPE_TX_DESC_FETCH:
  1514. case RESET_TYPE_TX_SKIP:
  1515. method = RESET_TYPE_INVISIBLE;
  1516. break;
  1517. default:
  1518. method = RESET_TYPE_ALL;
  1519. break;
  1520. }
  1521. if (method != type)
  1522. EFX_LOG(efx, "scheduling reset (%d:%d)\n", type, method);
  1523. else
  1524. EFX_LOG(efx, "scheduling reset (%d)\n", method);
  1525. efx->reset_pending = method;
  1526. queue_work(reset_workqueue, &efx->reset_work);
  1527. }
  1528. /**************************************************************************
  1529. *
  1530. * List of NICs we support
  1531. *
  1532. **************************************************************************/
  1533. /* PCI device ID table */
  1534. static struct pci_device_id efx_pci_table[] __devinitdata = {
  1535. {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID),
  1536. .driver_data = (unsigned long) &falcon_a_nic_type},
  1537. {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID),
  1538. .driver_data = (unsigned long) &falcon_b_nic_type},
  1539. {0} /* end of list */
  1540. };
  1541. /**************************************************************************
  1542. *
  1543. * Dummy PHY/MAC/Board operations
  1544. *
  1545. * Can be used for some unimplemented operations
  1546. * Needed so all function pointers are valid and do not have to be tested
  1547. * before use
  1548. *
  1549. **************************************************************************/
  1550. int efx_port_dummy_op_int(struct efx_nic *efx)
  1551. {
  1552. return 0;
  1553. }
  1554. void efx_port_dummy_op_void(struct efx_nic *efx) {}
  1555. void efx_port_dummy_op_blink(struct efx_nic *efx, bool blink) {}
  1556. static struct efx_mac_operations efx_dummy_mac_operations = {
  1557. .reconfigure = efx_port_dummy_op_void,
  1558. .poll = efx_port_dummy_op_void,
  1559. .irq = efx_port_dummy_op_void,
  1560. };
  1561. static struct efx_phy_operations efx_dummy_phy_operations = {
  1562. .init = efx_port_dummy_op_int,
  1563. .reconfigure = efx_port_dummy_op_void,
  1564. .poll = efx_port_dummy_op_void,
  1565. .fini = efx_port_dummy_op_void,
  1566. .clear_interrupt = efx_port_dummy_op_void,
  1567. };
  1568. static struct efx_board efx_dummy_board_info = {
  1569. .init = efx_port_dummy_op_int,
  1570. .init_leds = efx_port_dummy_op_void,
  1571. .set_id_led = efx_port_dummy_op_blink,
  1572. .monitor = efx_port_dummy_op_int,
  1573. .blink = efx_port_dummy_op_blink,
  1574. .fini = efx_port_dummy_op_void,
  1575. };
  1576. /**************************************************************************
  1577. *
  1578. * Data housekeeping
  1579. *
  1580. **************************************************************************/
  1581. /* This zeroes out and then fills in the invariants in a struct
  1582. * efx_nic (including all sub-structures).
  1583. */
  1584. static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type,
  1585. struct pci_dev *pci_dev, struct net_device *net_dev)
  1586. {
  1587. struct efx_channel *channel;
  1588. struct efx_tx_queue *tx_queue;
  1589. struct efx_rx_queue *rx_queue;
  1590. int i;
  1591. /* Initialise common structures */
  1592. memset(efx, 0, sizeof(*efx));
  1593. spin_lock_init(&efx->biu_lock);
  1594. spin_lock_init(&efx->phy_lock);
  1595. mutex_init(&efx->spi_lock);
  1596. INIT_WORK(&efx->reset_work, efx_reset_work);
  1597. INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
  1598. efx->pci_dev = pci_dev;
  1599. efx->state = STATE_INIT;
  1600. efx->reset_pending = RESET_TYPE_NONE;
  1601. strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
  1602. efx->board_info = efx_dummy_board_info;
  1603. efx->net_dev = net_dev;
  1604. efx->rx_checksum_enabled = true;
  1605. spin_lock_init(&efx->netif_stop_lock);
  1606. spin_lock_init(&efx->stats_lock);
  1607. efx->stats_disable_count = 1;
  1608. mutex_init(&efx->mac_lock);
  1609. efx->mac_op = &efx_dummy_mac_operations;
  1610. efx->phy_op = &efx_dummy_phy_operations;
  1611. efx->mdio.dev = net_dev;
  1612. INIT_WORK(&efx->phy_work, efx_phy_work);
  1613. INIT_WORK(&efx->mac_work, efx_mac_work);
  1614. atomic_set(&efx->netif_stop_count, 1);
  1615. for (i = 0; i < EFX_MAX_CHANNELS; i++) {
  1616. channel = &efx->channel[i];
  1617. channel->efx = efx;
  1618. channel->channel = i;
  1619. channel->work_pending = false;
  1620. }
  1621. for (i = 0; i < EFX_TX_QUEUE_COUNT; i++) {
  1622. tx_queue = &efx->tx_queue[i];
  1623. tx_queue->efx = efx;
  1624. tx_queue->queue = i;
  1625. tx_queue->buffer = NULL;
  1626. tx_queue->channel = &efx->channel[0]; /* for safety */
  1627. tx_queue->tso_headers_free = NULL;
  1628. }
  1629. for (i = 0; i < EFX_MAX_RX_QUEUES; i++) {
  1630. rx_queue = &efx->rx_queue[i];
  1631. rx_queue->efx = efx;
  1632. rx_queue->queue = i;
  1633. rx_queue->channel = &efx->channel[0]; /* for safety */
  1634. rx_queue->buffer = NULL;
  1635. spin_lock_init(&rx_queue->add_lock);
  1636. INIT_DELAYED_WORK(&rx_queue->work, efx_rx_work);
  1637. }
  1638. efx->type = type;
  1639. /* Sanity-check NIC type */
  1640. EFX_BUG_ON_PARANOID(efx->type->txd_ring_mask &
  1641. (efx->type->txd_ring_mask + 1));
  1642. EFX_BUG_ON_PARANOID(efx->type->rxd_ring_mask &
  1643. (efx->type->rxd_ring_mask + 1));
  1644. EFX_BUG_ON_PARANOID(efx->type->evq_size &
  1645. (efx->type->evq_size - 1));
  1646. /* As close as we can get to guaranteeing that we don't overflow */
  1647. EFX_BUG_ON_PARANOID(efx->type->evq_size <
  1648. (efx->type->txd_ring_mask + 1 +
  1649. efx->type->rxd_ring_mask + 1));
  1650. EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS);
  1651. /* Higher numbered interrupt modes are less capable! */
  1652. efx->interrupt_mode = max(efx->type->max_interrupt_mode,
  1653. interrupt_mode);
  1654. /* Would be good to use the net_dev name, but we're too early */
  1655. snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
  1656. pci_name(pci_dev));
  1657. efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
  1658. if (!efx->workqueue)
  1659. return -ENOMEM;
  1660. return 0;
  1661. }
  1662. static void efx_fini_struct(struct efx_nic *efx)
  1663. {
  1664. if (efx->workqueue) {
  1665. destroy_workqueue(efx->workqueue);
  1666. efx->workqueue = NULL;
  1667. }
  1668. }
  1669. /**************************************************************************
  1670. *
  1671. * PCI interface
  1672. *
  1673. **************************************************************************/
  1674. /* Main body of final NIC shutdown code
  1675. * This is called only at module unload (or hotplug removal).
  1676. */
  1677. static void efx_pci_remove_main(struct efx_nic *efx)
  1678. {
  1679. EFX_ASSERT_RESET_SERIALISED(efx);
  1680. /* Skip everything if we never obtained a valid membase */
  1681. if (!efx->membase)
  1682. return;
  1683. efx_fini_channels(efx);
  1684. efx_fini_port(efx);
  1685. /* Shutdown the board, then the NIC and board state */
  1686. efx->board_info.fini(efx);
  1687. falcon_fini_interrupt(efx);
  1688. efx_fini_napi(efx);
  1689. efx_remove_all(efx);
  1690. }
  1691. /* Final NIC shutdown
  1692. * This is called only at module unload (or hotplug removal).
  1693. */
  1694. static void efx_pci_remove(struct pci_dev *pci_dev)
  1695. {
  1696. struct efx_nic *efx;
  1697. efx = pci_get_drvdata(pci_dev);
  1698. if (!efx)
  1699. return;
  1700. /* Mark the NIC as fini, then stop the interface */
  1701. rtnl_lock();
  1702. efx->state = STATE_FINI;
  1703. dev_close(efx->net_dev);
  1704. /* Allow any queued efx_resets() to complete */
  1705. rtnl_unlock();
  1706. if (efx->membase == NULL)
  1707. goto out;
  1708. efx_unregister_netdev(efx);
  1709. efx_mtd_remove(efx);
  1710. /* Wait for any scheduled resets to complete. No more will be
  1711. * scheduled from this point because efx_stop_all() has been
  1712. * called, we are no longer registered with driverlink, and
  1713. * the net_device's have been removed. */
  1714. cancel_work_sync(&efx->reset_work);
  1715. efx_pci_remove_main(efx);
  1716. out:
  1717. efx_fini_io(efx);
  1718. EFX_LOG(efx, "shutdown successful\n");
  1719. pci_set_drvdata(pci_dev, NULL);
  1720. efx_fini_struct(efx);
  1721. free_netdev(efx->net_dev);
  1722. };
  1723. /* Main body of NIC initialisation
  1724. * This is called at module load (or hotplug insertion, theoretically).
  1725. */
  1726. static int efx_pci_probe_main(struct efx_nic *efx)
  1727. {
  1728. int rc;
  1729. /* Do start-of-day initialisation */
  1730. rc = efx_probe_all(efx);
  1731. if (rc)
  1732. goto fail1;
  1733. rc = efx_init_napi(efx);
  1734. if (rc)
  1735. goto fail2;
  1736. /* Initialise the board */
  1737. rc = efx->board_info.init(efx);
  1738. if (rc) {
  1739. EFX_ERR(efx, "failed to initialise board\n");
  1740. goto fail3;
  1741. }
  1742. rc = falcon_init_nic(efx);
  1743. if (rc) {
  1744. EFX_ERR(efx, "failed to initialise NIC\n");
  1745. goto fail4;
  1746. }
  1747. rc = efx_init_port(efx);
  1748. if (rc) {
  1749. EFX_ERR(efx, "failed to initialise port\n");
  1750. goto fail5;
  1751. }
  1752. efx_init_channels(efx);
  1753. rc = falcon_init_interrupt(efx);
  1754. if (rc)
  1755. goto fail6;
  1756. return 0;
  1757. fail6:
  1758. efx_fini_channels(efx);
  1759. efx_fini_port(efx);
  1760. fail5:
  1761. fail4:
  1762. efx->board_info.fini(efx);
  1763. fail3:
  1764. efx_fini_napi(efx);
  1765. fail2:
  1766. efx_remove_all(efx);
  1767. fail1:
  1768. return rc;
  1769. }
  1770. /* NIC initialisation
  1771. *
  1772. * This is called at module load (or hotplug insertion,
  1773. * theoretically). It sets up PCI mappings, tests and resets the NIC,
  1774. * sets up and registers the network devices with the kernel and hooks
  1775. * the interrupt service routine. It does not prepare the device for
  1776. * transmission; this is left to the first time one of the network
  1777. * interfaces is brought up (i.e. efx_net_open).
  1778. */
  1779. static int __devinit efx_pci_probe(struct pci_dev *pci_dev,
  1780. const struct pci_device_id *entry)
  1781. {
  1782. struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data;
  1783. struct net_device *net_dev;
  1784. struct efx_nic *efx;
  1785. int i, rc;
  1786. /* Allocate and initialise a struct net_device and struct efx_nic */
  1787. net_dev = alloc_etherdev(sizeof(*efx));
  1788. if (!net_dev)
  1789. return -ENOMEM;
  1790. net_dev->features |= (NETIF_F_IP_CSUM | NETIF_F_SG |
  1791. NETIF_F_HIGHDMA | NETIF_F_TSO |
  1792. NETIF_F_GRO);
  1793. /* Mask for features that also apply to VLAN devices */
  1794. net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG |
  1795. NETIF_F_HIGHDMA | NETIF_F_TSO);
  1796. efx = netdev_priv(net_dev);
  1797. pci_set_drvdata(pci_dev, efx);
  1798. rc = efx_init_struct(efx, type, pci_dev, net_dev);
  1799. if (rc)
  1800. goto fail1;
  1801. EFX_INFO(efx, "Solarflare Communications NIC detected\n");
  1802. /* Set up basic I/O (BAR mappings etc) */
  1803. rc = efx_init_io(efx);
  1804. if (rc)
  1805. goto fail2;
  1806. /* No serialisation is required with the reset path because
  1807. * we're in STATE_INIT. */
  1808. for (i = 0; i < 5; i++) {
  1809. rc = efx_pci_probe_main(efx);
  1810. /* Serialise against efx_reset(). No more resets will be
  1811. * scheduled since efx_stop_all() has been called, and we
  1812. * have not and never have been registered with either
  1813. * the rtnetlink or driverlink layers. */
  1814. cancel_work_sync(&efx->reset_work);
  1815. if (rc == 0) {
  1816. if (efx->reset_pending != RESET_TYPE_NONE) {
  1817. /* If there was a scheduled reset during
  1818. * probe, the NIC is probably hosed anyway */
  1819. efx_pci_remove_main(efx);
  1820. rc = -EIO;
  1821. } else {
  1822. break;
  1823. }
  1824. }
  1825. /* Retry if a recoverably reset event has been scheduled */
  1826. if ((efx->reset_pending != RESET_TYPE_INVISIBLE) &&
  1827. (efx->reset_pending != RESET_TYPE_ALL))
  1828. goto fail3;
  1829. efx->reset_pending = RESET_TYPE_NONE;
  1830. }
  1831. if (rc) {
  1832. EFX_ERR(efx, "Could not reset NIC\n");
  1833. goto fail4;
  1834. }
  1835. /* Switch to the running state before we expose the device to
  1836. * the OS. This is to ensure that the initial gathering of
  1837. * MAC stats succeeds. */
  1838. efx->state = STATE_RUNNING;
  1839. efx_mtd_probe(efx); /* allowed to fail */
  1840. rc = efx_register_netdev(efx);
  1841. if (rc)
  1842. goto fail5;
  1843. EFX_LOG(efx, "initialisation successful\n");
  1844. return 0;
  1845. fail5:
  1846. efx_pci_remove_main(efx);
  1847. fail4:
  1848. fail3:
  1849. efx_fini_io(efx);
  1850. fail2:
  1851. efx_fini_struct(efx);
  1852. fail1:
  1853. EFX_LOG(efx, "initialisation failed. rc=%d\n", rc);
  1854. free_netdev(net_dev);
  1855. return rc;
  1856. }
  1857. static struct pci_driver efx_pci_driver = {
  1858. .name = EFX_DRIVER_NAME,
  1859. .id_table = efx_pci_table,
  1860. .probe = efx_pci_probe,
  1861. .remove = efx_pci_remove,
  1862. };
  1863. /**************************************************************************
  1864. *
  1865. * Kernel module interface
  1866. *
  1867. *************************************************************************/
  1868. module_param(interrupt_mode, uint, 0444);
  1869. MODULE_PARM_DESC(interrupt_mode,
  1870. "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
  1871. static int __init efx_init_module(void)
  1872. {
  1873. int rc;
  1874. printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
  1875. rc = register_netdevice_notifier(&efx_netdev_notifier);
  1876. if (rc)
  1877. goto err_notifier;
  1878. refill_workqueue = create_workqueue("sfc_refill");
  1879. if (!refill_workqueue) {
  1880. rc = -ENOMEM;
  1881. goto err_refill;
  1882. }
  1883. reset_workqueue = create_singlethread_workqueue("sfc_reset");
  1884. if (!reset_workqueue) {
  1885. rc = -ENOMEM;
  1886. goto err_reset;
  1887. }
  1888. rc = pci_register_driver(&efx_pci_driver);
  1889. if (rc < 0)
  1890. goto err_pci;
  1891. return 0;
  1892. err_pci:
  1893. destroy_workqueue(reset_workqueue);
  1894. err_reset:
  1895. destroy_workqueue(refill_workqueue);
  1896. err_refill:
  1897. unregister_netdevice_notifier(&efx_netdev_notifier);
  1898. err_notifier:
  1899. return rc;
  1900. }
  1901. static void __exit efx_exit_module(void)
  1902. {
  1903. printk(KERN_INFO "Solarflare NET driver unloading\n");
  1904. pci_unregister_driver(&efx_pci_driver);
  1905. destroy_workqueue(reset_workqueue);
  1906. destroy_workqueue(refill_workqueue);
  1907. unregister_netdevice_notifier(&efx_netdev_notifier);
  1908. }
  1909. module_init(efx_init_module);
  1910. module_exit(efx_exit_module);
  1911. MODULE_AUTHOR("Michael Brown <mbrown@fensystems.co.uk> and "
  1912. "Solarflare Communications");
  1913. MODULE_DESCRIPTION("Solarflare Communications network driver");
  1914. MODULE_LICENSE("GPL");
  1915. MODULE_DEVICE_TABLE(pci, efx_pci_table);