netxen_nic_init.c 38 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * Copyright (C) 2009 - QLogic Corporation.
  4. * All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  19. * MA 02111-1307, USA.
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.
  23. *
  24. */
  25. #include <linux/netdevice.h>
  26. #include <linux/delay.h>
  27. #include "netxen_nic.h"
  28. #include "netxen_nic_hw.h"
  29. struct crb_addr_pair {
  30. u32 addr;
  31. u32 data;
  32. };
  33. #define NETXEN_MAX_CRB_XFORM 60
  34. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  35. #define NETXEN_ADDR_ERROR (0xffffffff)
  36. #define crb_addr_transform(name) \
  37. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  38. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  39. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  40. static void
  41. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  42. struct nx_host_rds_ring *rds_ring);
  43. static void crb_addr_transform_setup(void)
  44. {
  45. crb_addr_transform(XDMA);
  46. crb_addr_transform(TIMR);
  47. crb_addr_transform(SRE);
  48. crb_addr_transform(SQN3);
  49. crb_addr_transform(SQN2);
  50. crb_addr_transform(SQN1);
  51. crb_addr_transform(SQN0);
  52. crb_addr_transform(SQS3);
  53. crb_addr_transform(SQS2);
  54. crb_addr_transform(SQS1);
  55. crb_addr_transform(SQS0);
  56. crb_addr_transform(RPMX7);
  57. crb_addr_transform(RPMX6);
  58. crb_addr_transform(RPMX5);
  59. crb_addr_transform(RPMX4);
  60. crb_addr_transform(RPMX3);
  61. crb_addr_transform(RPMX2);
  62. crb_addr_transform(RPMX1);
  63. crb_addr_transform(RPMX0);
  64. crb_addr_transform(ROMUSB);
  65. crb_addr_transform(SN);
  66. crb_addr_transform(QMN);
  67. crb_addr_transform(QMS);
  68. crb_addr_transform(PGNI);
  69. crb_addr_transform(PGND);
  70. crb_addr_transform(PGN3);
  71. crb_addr_transform(PGN2);
  72. crb_addr_transform(PGN1);
  73. crb_addr_transform(PGN0);
  74. crb_addr_transform(PGSI);
  75. crb_addr_transform(PGSD);
  76. crb_addr_transform(PGS3);
  77. crb_addr_transform(PGS2);
  78. crb_addr_transform(PGS1);
  79. crb_addr_transform(PGS0);
  80. crb_addr_transform(PS);
  81. crb_addr_transform(PH);
  82. crb_addr_transform(NIU);
  83. crb_addr_transform(I2Q);
  84. crb_addr_transform(EG);
  85. crb_addr_transform(MN);
  86. crb_addr_transform(MS);
  87. crb_addr_transform(CAS2);
  88. crb_addr_transform(CAS1);
  89. crb_addr_transform(CAS0);
  90. crb_addr_transform(CAM);
  91. crb_addr_transform(C2C1);
  92. crb_addr_transform(C2C0);
  93. crb_addr_transform(SMB);
  94. crb_addr_transform(OCM0);
  95. crb_addr_transform(I2C0);
  96. }
  97. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  98. {
  99. struct netxen_recv_context *recv_ctx;
  100. struct nx_host_rds_ring *rds_ring;
  101. struct netxen_rx_buffer *rx_buf;
  102. int i, ring;
  103. recv_ctx = &adapter->recv_ctx;
  104. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  105. rds_ring = &recv_ctx->rds_rings[ring];
  106. for (i = 0; i < rds_ring->num_desc; ++i) {
  107. rx_buf = &(rds_ring->rx_buf_arr[i]);
  108. if (rx_buf->state == NETXEN_BUFFER_FREE)
  109. continue;
  110. pci_unmap_single(adapter->pdev,
  111. rx_buf->dma,
  112. rds_ring->dma_size,
  113. PCI_DMA_FROMDEVICE);
  114. if (rx_buf->skb != NULL)
  115. dev_kfree_skb_any(rx_buf->skb);
  116. }
  117. }
  118. }
  119. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  120. {
  121. struct netxen_cmd_buffer *cmd_buf;
  122. struct netxen_skb_frag *buffrag;
  123. int i, j;
  124. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  125. cmd_buf = tx_ring->cmd_buf_arr;
  126. for (i = 0; i < tx_ring->num_desc; i++) {
  127. buffrag = cmd_buf->frag_array;
  128. if (buffrag->dma) {
  129. pci_unmap_single(adapter->pdev, buffrag->dma,
  130. buffrag->length, PCI_DMA_TODEVICE);
  131. buffrag->dma = 0ULL;
  132. }
  133. for (j = 0; j < cmd_buf->frag_count; j++) {
  134. buffrag++;
  135. if (buffrag->dma) {
  136. pci_unmap_page(adapter->pdev, buffrag->dma,
  137. buffrag->length,
  138. PCI_DMA_TODEVICE);
  139. buffrag->dma = 0ULL;
  140. }
  141. }
  142. if (cmd_buf->skb) {
  143. dev_kfree_skb_any(cmd_buf->skb);
  144. cmd_buf->skb = NULL;
  145. }
  146. cmd_buf++;
  147. }
  148. }
  149. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  150. {
  151. struct netxen_recv_context *recv_ctx;
  152. struct nx_host_rds_ring *rds_ring;
  153. struct nx_host_tx_ring *tx_ring;
  154. int ring;
  155. recv_ctx = &adapter->recv_ctx;
  156. if (recv_ctx->rds_rings == NULL)
  157. goto skip_rds;
  158. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  159. rds_ring = &recv_ctx->rds_rings[ring];
  160. vfree(rds_ring->rx_buf_arr);
  161. rds_ring->rx_buf_arr = NULL;
  162. }
  163. kfree(recv_ctx->rds_rings);
  164. skip_rds:
  165. if (adapter->tx_ring == NULL)
  166. return;
  167. tx_ring = adapter->tx_ring;
  168. vfree(tx_ring->cmd_buf_arr);
  169. }
  170. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  171. {
  172. struct netxen_recv_context *recv_ctx;
  173. struct nx_host_rds_ring *rds_ring;
  174. struct nx_host_sds_ring *sds_ring;
  175. struct nx_host_tx_ring *tx_ring;
  176. struct netxen_rx_buffer *rx_buf;
  177. int ring, i, size;
  178. struct netxen_cmd_buffer *cmd_buf_arr;
  179. struct net_device *netdev = adapter->netdev;
  180. struct pci_dev *pdev = adapter->pdev;
  181. size = sizeof(struct nx_host_tx_ring);
  182. tx_ring = kzalloc(size, GFP_KERNEL);
  183. if (tx_ring == NULL) {
  184. dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
  185. netdev->name);
  186. return -ENOMEM;
  187. }
  188. adapter->tx_ring = tx_ring;
  189. tx_ring->num_desc = adapter->num_txd;
  190. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  191. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  192. if (cmd_buf_arr == NULL) {
  193. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  194. netdev->name);
  195. return -ENOMEM;
  196. }
  197. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  198. tx_ring->cmd_buf_arr = cmd_buf_arr;
  199. recv_ctx = &adapter->recv_ctx;
  200. size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
  201. rds_ring = kzalloc(size, GFP_KERNEL);
  202. if (rds_ring == NULL) {
  203. dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
  204. netdev->name);
  205. return -ENOMEM;
  206. }
  207. recv_ctx->rds_rings = rds_ring;
  208. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  209. rds_ring = &recv_ctx->rds_rings[ring];
  210. switch (ring) {
  211. case RCV_RING_NORMAL:
  212. rds_ring->num_desc = adapter->num_rxd;
  213. if (adapter->ahw.cut_through) {
  214. rds_ring->dma_size =
  215. NX_CT_DEFAULT_RX_BUF_LEN;
  216. rds_ring->skb_size =
  217. NX_CT_DEFAULT_RX_BUF_LEN;
  218. } else {
  219. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  220. rds_ring->dma_size =
  221. NX_P3_RX_BUF_MAX_LEN;
  222. else
  223. rds_ring->dma_size =
  224. NX_P2_RX_BUF_MAX_LEN;
  225. rds_ring->skb_size =
  226. rds_ring->dma_size + NET_IP_ALIGN;
  227. }
  228. break;
  229. case RCV_RING_JUMBO:
  230. rds_ring->num_desc = adapter->num_jumbo_rxd;
  231. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  232. rds_ring->dma_size =
  233. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  234. else
  235. rds_ring->dma_size =
  236. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  237. if (adapter->capabilities & NX_CAP0_HW_LRO)
  238. rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
  239. rds_ring->skb_size =
  240. rds_ring->dma_size + NET_IP_ALIGN;
  241. break;
  242. case RCV_RING_LRO:
  243. rds_ring->num_desc = adapter->num_lro_rxd;
  244. rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
  245. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  246. break;
  247. }
  248. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  249. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  250. if (rds_ring->rx_buf_arr == NULL) {
  251. printk(KERN_ERR "%s: Failed to allocate "
  252. "rx buffer ring %d\n",
  253. netdev->name, ring);
  254. /* free whatever was already allocated */
  255. goto err_out;
  256. }
  257. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  258. INIT_LIST_HEAD(&rds_ring->free_list);
  259. /*
  260. * Now go through all of them, set reference handles
  261. * and put them in the queues.
  262. */
  263. rx_buf = rds_ring->rx_buf_arr;
  264. for (i = 0; i < rds_ring->num_desc; i++) {
  265. list_add_tail(&rx_buf->list,
  266. &rds_ring->free_list);
  267. rx_buf->ref_handle = i;
  268. rx_buf->state = NETXEN_BUFFER_FREE;
  269. rx_buf++;
  270. }
  271. spin_lock_init(&rds_ring->lock);
  272. }
  273. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  274. sds_ring = &recv_ctx->sds_rings[ring];
  275. sds_ring->irq = adapter->msix_entries[ring].vector;
  276. sds_ring->adapter = adapter;
  277. sds_ring->num_desc = adapter->num_rxd;
  278. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  279. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  280. }
  281. return 0;
  282. err_out:
  283. netxen_free_sw_resources(adapter);
  284. return -ENOMEM;
  285. }
  286. /*
  287. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  288. * address to external PCI CRB address.
  289. */
  290. static u32 netxen_decode_crb_addr(u32 addr)
  291. {
  292. int i;
  293. u32 base_addr, offset, pci_base;
  294. crb_addr_transform_setup();
  295. pci_base = NETXEN_ADDR_ERROR;
  296. base_addr = addr & 0xfff00000;
  297. offset = addr & 0x000fffff;
  298. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  299. if (crb_addr_xform[i] == base_addr) {
  300. pci_base = i << 20;
  301. break;
  302. }
  303. }
  304. if (pci_base == NETXEN_ADDR_ERROR)
  305. return pci_base;
  306. else
  307. return (pci_base + offset);
  308. }
  309. #define NETXEN_MAX_ROM_WAIT_USEC 100
  310. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  311. {
  312. long timeout = 0;
  313. long done = 0;
  314. cond_resched();
  315. while (done == 0) {
  316. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  317. done &= 2;
  318. if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
  319. dev_err(&adapter->pdev->dev,
  320. "Timeout reached waiting for rom done");
  321. return -EIO;
  322. }
  323. udelay(1);
  324. }
  325. return 0;
  326. }
  327. static int do_rom_fast_read(struct netxen_adapter *adapter,
  328. int addr, int *valp)
  329. {
  330. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  331. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  332. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  333. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  334. if (netxen_wait_rom_done(adapter)) {
  335. printk("Error waiting for rom done\n");
  336. return -EIO;
  337. }
  338. /* reset abyte_cnt and dummy_byte_cnt */
  339. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  340. udelay(10);
  341. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  342. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  343. return 0;
  344. }
  345. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  346. u8 *bytes, size_t size)
  347. {
  348. int addridx;
  349. int ret = 0;
  350. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  351. int v;
  352. ret = do_rom_fast_read(adapter, addridx, &v);
  353. if (ret != 0)
  354. break;
  355. *(__le32 *)bytes = cpu_to_le32(v);
  356. bytes += 4;
  357. }
  358. return ret;
  359. }
  360. int
  361. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  362. u8 *bytes, size_t size)
  363. {
  364. int ret;
  365. ret = netxen_rom_lock(adapter);
  366. if (ret < 0)
  367. return ret;
  368. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  369. netxen_rom_unlock(adapter);
  370. return ret;
  371. }
  372. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  373. {
  374. int ret;
  375. if (netxen_rom_lock(adapter) != 0)
  376. return -EIO;
  377. ret = do_rom_fast_read(adapter, addr, valp);
  378. netxen_rom_unlock(adapter);
  379. return ret;
  380. }
  381. #define NETXEN_BOARDTYPE 0x4008
  382. #define NETXEN_BOARDNUM 0x400c
  383. #define NETXEN_CHIPNUM 0x4010
  384. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  385. {
  386. int addr, val;
  387. int i, n, init_delay = 0;
  388. struct crb_addr_pair *buf;
  389. unsigned offset;
  390. u32 off;
  391. /* resetall */
  392. netxen_rom_lock(adapter);
  393. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
  394. netxen_rom_unlock(adapter);
  395. if (verbose) {
  396. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  397. printk("P2 ROM board type: 0x%08x\n", val);
  398. else
  399. printk("Could not read board type\n");
  400. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  401. printk("P2 ROM board num: 0x%08x\n", val);
  402. else
  403. printk("Could not read board number\n");
  404. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  405. printk("P2 ROM chip num: 0x%08x\n", val);
  406. else
  407. printk("Could not read chip number\n");
  408. }
  409. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  410. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  411. (n != 0xcafecafe) ||
  412. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  413. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  414. "n: %08x\n", netxen_nic_driver_name, n);
  415. return -EIO;
  416. }
  417. offset = n & 0xffffU;
  418. n = (n >> 16) & 0xffffU;
  419. } else {
  420. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  421. !(n & 0x80000000)) {
  422. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  423. "n: %08x\n", netxen_nic_driver_name, n);
  424. return -EIO;
  425. }
  426. offset = 1;
  427. n &= ~0x80000000;
  428. }
  429. if (n < 1024) {
  430. if (verbose)
  431. printk(KERN_DEBUG "%s: %d CRB init values found"
  432. " in ROM.\n", netxen_nic_driver_name, n);
  433. } else {
  434. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  435. " initialized.\n", __func__, n);
  436. return -EIO;
  437. }
  438. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  439. if (buf == NULL) {
  440. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  441. netxen_nic_driver_name);
  442. return -ENOMEM;
  443. }
  444. for (i = 0; i < n; i++) {
  445. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  446. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  447. kfree(buf);
  448. return -EIO;
  449. }
  450. buf[i].addr = addr;
  451. buf[i].data = val;
  452. if (verbose)
  453. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  454. netxen_nic_driver_name,
  455. (u32)netxen_decode_crb_addr(addr), val);
  456. }
  457. for (i = 0; i < n; i++) {
  458. off = netxen_decode_crb_addr(buf[i].addr);
  459. if (off == NETXEN_ADDR_ERROR) {
  460. printk(KERN_ERR"CRB init value out of range %x\n",
  461. buf[i].addr);
  462. continue;
  463. }
  464. off += NETXEN_PCI_CRBSPACE;
  465. /* skipping cold reboot MAGIC */
  466. if (off == NETXEN_CAM_RAM(0x1fc))
  467. continue;
  468. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  469. /* do not reset PCI */
  470. if (off == (ROMUSB_GLB + 0xbc))
  471. continue;
  472. if (off == (ROMUSB_GLB + 0xa8))
  473. continue;
  474. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  475. continue;
  476. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  477. continue;
  478. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  479. continue;
  480. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  481. buf[i].data = 0x1020;
  482. /* skip the function enable register */
  483. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  484. continue;
  485. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  486. continue;
  487. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  488. continue;
  489. }
  490. if (off == NETXEN_ADDR_ERROR) {
  491. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  492. netxen_nic_driver_name, buf[i].addr);
  493. continue;
  494. }
  495. init_delay = 1;
  496. /* After writing this register, HW needs time for CRB */
  497. /* to quiet down (else crb_window returns 0xffffffff) */
  498. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  499. init_delay = 1000;
  500. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  501. /* hold xdma in reset also */
  502. buf[i].data = NETXEN_NIC_XDMA_RESET;
  503. buf[i].data = 0x8000ff;
  504. }
  505. }
  506. NXWR32(adapter, off, buf[i].data);
  507. msleep(init_delay);
  508. }
  509. kfree(buf);
  510. /* disable_peg_cache_all */
  511. /* unreset_net_cache */
  512. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  513. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  514. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  515. }
  516. /* p2dn replyCount */
  517. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  518. /* disable_peg_cache 0 */
  519. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  520. /* disable_peg_cache 1 */
  521. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  522. /* peg_clr_all */
  523. /* peg_clr 0 */
  524. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  525. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  526. /* peg_clr 1 */
  527. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  528. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  529. /* peg_clr 2 */
  530. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  531. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  532. /* peg_clr 3 */
  533. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  534. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  535. return 0;
  536. }
  537. int
  538. netxen_need_fw_reset(struct netxen_adapter *adapter)
  539. {
  540. u32 count, old_count;
  541. u32 val, version, major, minor, build;
  542. int i, timeout;
  543. u8 fw_type;
  544. /* NX2031 firmware doesn't support heartbit */
  545. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  546. return 1;
  547. /* last attempt had failed */
  548. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  549. return 1;
  550. old_count = count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  551. for (i = 0; i < 10; i++) {
  552. timeout = msleep_interruptible(200);
  553. if (timeout) {
  554. NXWR32(adapter, CRB_CMDPEG_STATE,
  555. PHAN_INITIALIZE_FAILED);
  556. return -EINTR;
  557. }
  558. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  559. if (count != old_count)
  560. break;
  561. }
  562. /* firmware is dead */
  563. if (count == old_count)
  564. return 1;
  565. /* check if we have got newer or different file firmware */
  566. if (adapter->fw) {
  567. const struct firmware *fw = adapter->fw;
  568. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  569. version = NETXEN_DECODE_VERSION(val);
  570. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  571. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  572. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  573. if (version > NETXEN_VERSION_CODE(major, minor, build))
  574. return 1;
  575. if (version == NETXEN_VERSION_CODE(major, minor, build)) {
  576. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  577. fw_type = (val & 0x4) ?
  578. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  579. if (adapter->fw_type != fw_type)
  580. return 1;
  581. }
  582. }
  583. return 0;
  584. }
  585. static char *fw_name[] = {
  586. "nxromimg.bin", "nx3fwct.bin", "nx3fwmn.bin", "flash",
  587. };
  588. int
  589. netxen_load_firmware(struct netxen_adapter *adapter)
  590. {
  591. u64 *ptr64;
  592. u32 i, flashaddr, size;
  593. const struct firmware *fw = adapter->fw;
  594. struct pci_dev *pdev = adapter->pdev;
  595. dev_info(&pdev->dev, "loading firmware from %s\n",
  596. fw_name[adapter->fw_type]);
  597. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  598. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  599. if (fw) {
  600. __le64 data;
  601. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  602. ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START];
  603. flashaddr = NETXEN_BOOTLD_START;
  604. for (i = 0; i < size; i++) {
  605. data = cpu_to_le64(ptr64[i]);
  606. adapter->pci_mem_write(adapter, flashaddr, &data, 8);
  607. flashaddr += 8;
  608. }
  609. size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET];
  610. size = (__force u32)cpu_to_le32(size) / 8;
  611. ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START];
  612. flashaddr = NETXEN_IMAGE_START;
  613. for (i = 0; i < size; i++) {
  614. data = cpu_to_le64(ptr64[i]);
  615. if (adapter->pci_mem_write(adapter,
  616. flashaddr, &data, 8))
  617. return -EIO;
  618. flashaddr += 8;
  619. }
  620. } else {
  621. u64 data;
  622. u32 hi, lo;
  623. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  624. flashaddr = NETXEN_BOOTLD_START;
  625. for (i = 0; i < size; i++) {
  626. if (netxen_rom_fast_read(adapter,
  627. flashaddr, &lo) != 0)
  628. return -EIO;
  629. if (netxen_rom_fast_read(adapter,
  630. flashaddr + 4, &hi) != 0)
  631. return -EIO;
  632. /* hi, lo are already in host endian byteorder */
  633. data = (((u64)hi << 32) | lo);
  634. if (adapter->pci_mem_write(adapter,
  635. flashaddr, &data, 8))
  636. return -EIO;
  637. flashaddr += 8;
  638. }
  639. }
  640. msleep(1);
  641. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  642. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  643. else {
  644. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  645. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  646. }
  647. return 0;
  648. }
  649. static int
  650. netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname)
  651. {
  652. __le32 val;
  653. u32 ver, min_ver, bios;
  654. struct pci_dev *pdev = adapter->pdev;
  655. const struct firmware *fw = adapter->fw;
  656. if (fw->size < NX_FW_MIN_SIZE)
  657. return -EINVAL;
  658. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  659. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  660. return -EINVAL;
  661. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  662. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  663. min_ver = NETXEN_VERSION_CODE(4, 0, 216);
  664. else
  665. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  666. ver = NETXEN_DECODE_VERSION(val);
  667. if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
  668. dev_err(&pdev->dev,
  669. "%s: firmware version %d.%d.%d unsupported\n",
  670. fwname, _major(ver), _minor(ver), _build(ver));
  671. return -EINVAL;
  672. }
  673. val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  674. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  675. if ((__force u32)val != bios) {
  676. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  677. fwname);
  678. return -EINVAL;
  679. }
  680. /* check if flashed firmware is newer */
  681. if (netxen_rom_fast_read(adapter,
  682. NX_FW_VERSION_OFFSET, (int *)&val))
  683. return -EIO;
  684. val = NETXEN_DECODE_VERSION(val);
  685. if (val > ver) {
  686. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  687. fwname);
  688. return -EINVAL;
  689. }
  690. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  691. return 0;
  692. }
  693. static int
  694. netxen_p3_has_mn(struct netxen_adapter *adapter)
  695. {
  696. u32 capability, flashed_ver;
  697. capability = 0;
  698. netxen_rom_fast_read(adapter,
  699. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  700. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  701. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  702. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  703. if (capability & NX_PEG_TUNE_MN_PRESENT)
  704. return 1;
  705. }
  706. return 0;
  707. }
  708. void netxen_request_firmware(struct netxen_adapter *adapter)
  709. {
  710. u8 fw_type;
  711. struct pci_dev *pdev = adapter->pdev;
  712. int rc = 0;
  713. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  714. fw_type = NX_P2_MN_ROMIMAGE;
  715. goto request_fw;
  716. }
  717. fw_type = netxen_p3_has_mn(adapter) ?
  718. NX_P3_MN_ROMIMAGE : NX_P3_CT_ROMIMAGE;
  719. request_fw:
  720. rc = request_firmware(&adapter->fw, fw_name[fw_type], &pdev->dev);
  721. if (rc != 0) {
  722. if (fw_type == NX_P3_MN_ROMIMAGE) {
  723. msleep(1);
  724. fw_type = NX_P3_CT_ROMIMAGE;
  725. goto request_fw;
  726. }
  727. fw_type = NX_FLASH_ROMIMAGE;
  728. adapter->fw = NULL;
  729. goto done;
  730. }
  731. rc = netxen_validate_firmware(adapter, fw_name[fw_type]);
  732. if (rc != 0) {
  733. release_firmware(adapter->fw);
  734. if (fw_type == NX_P3_MN_ROMIMAGE) {
  735. msleep(1);
  736. fw_type = NX_P3_CT_ROMIMAGE;
  737. goto request_fw;
  738. }
  739. fw_type = NX_FLASH_ROMIMAGE;
  740. adapter->fw = NULL;
  741. goto done;
  742. }
  743. done:
  744. adapter->fw_type = fw_type;
  745. }
  746. void
  747. netxen_release_firmware(struct netxen_adapter *adapter)
  748. {
  749. if (adapter->fw)
  750. release_firmware(adapter->fw);
  751. adapter->fw = NULL;
  752. }
  753. int netxen_init_dummy_dma(struct netxen_adapter *adapter)
  754. {
  755. u64 addr;
  756. u32 hi, lo;
  757. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  758. return 0;
  759. adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
  760. NETXEN_HOST_DUMMY_DMA_SIZE,
  761. &adapter->dummy_dma.phys_addr);
  762. if (adapter->dummy_dma.addr == NULL) {
  763. dev_err(&adapter->pdev->dev,
  764. "ERROR: Could not allocate dummy DMA memory\n");
  765. return -ENOMEM;
  766. }
  767. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  768. hi = (addr >> 32) & 0xffffffff;
  769. lo = addr & 0xffffffff;
  770. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  771. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  772. return 0;
  773. }
  774. /*
  775. * NetXen DMA watchdog control:
  776. *
  777. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  778. * Bit 1 : disable_request => 1 req disable dma watchdog
  779. * Bit 2 : enable_request => 1 req enable dma watchdog
  780. * Bit 3-31 : unused
  781. */
  782. void netxen_free_dummy_dma(struct netxen_adapter *adapter)
  783. {
  784. int i = 100;
  785. u32 ctrl;
  786. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  787. return;
  788. if (!adapter->dummy_dma.addr)
  789. return;
  790. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  791. if ((ctrl & 0x1) != 0) {
  792. NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
  793. while ((ctrl & 0x1) != 0) {
  794. msleep(50);
  795. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  796. if (--i == 0)
  797. break;
  798. };
  799. }
  800. if (i) {
  801. pci_free_consistent(adapter->pdev,
  802. NETXEN_HOST_DUMMY_DMA_SIZE,
  803. adapter->dummy_dma.addr,
  804. adapter->dummy_dma.phys_addr);
  805. adapter->dummy_dma.addr = NULL;
  806. } else
  807. dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
  808. }
  809. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  810. {
  811. u32 val = 0;
  812. int retries = 60;
  813. if (pegtune_val)
  814. return 0;
  815. do {
  816. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  817. switch (val) {
  818. case PHAN_INITIALIZE_COMPLETE:
  819. case PHAN_INITIALIZE_ACK:
  820. return 0;
  821. case PHAN_INITIALIZE_FAILED:
  822. goto out_err;
  823. default:
  824. break;
  825. }
  826. msleep(500);
  827. } while (--retries);
  828. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  829. out_err:
  830. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  831. return -EIO;
  832. }
  833. static int
  834. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  835. {
  836. u32 val = 0;
  837. int retries = 2000;
  838. do {
  839. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  840. if (val == PHAN_PEG_RCV_INITIALIZED)
  841. return 0;
  842. msleep(10);
  843. } while (--retries);
  844. if (!retries) {
  845. printk(KERN_ERR "Receive Peg initialization not "
  846. "complete, state: 0x%x.\n", val);
  847. return -EIO;
  848. }
  849. return 0;
  850. }
  851. int netxen_init_firmware(struct netxen_adapter *adapter)
  852. {
  853. int err;
  854. err = netxen_receive_peg_ready(adapter);
  855. if (err)
  856. return err;
  857. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  858. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  859. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  860. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  861. return err;
  862. }
  863. static void
  864. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  865. {
  866. u32 cable_OUI;
  867. u16 cable_len;
  868. u16 link_speed;
  869. u8 link_status, module, duplex, autoneg;
  870. struct net_device *netdev = adapter->netdev;
  871. adapter->has_link_events = 1;
  872. cable_OUI = msg->body[1] & 0xffffffff;
  873. cable_len = (msg->body[1] >> 32) & 0xffff;
  874. link_speed = (msg->body[1] >> 48) & 0xffff;
  875. link_status = msg->body[2] & 0xff;
  876. duplex = (msg->body[2] >> 16) & 0xff;
  877. autoneg = (msg->body[2] >> 24) & 0xff;
  878. module = (msg->body[2] >> 8) & 0xff;
  879. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  880. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  881. netdev->name, cable_OUI, cable_len);
  882. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  883. printk(KERN_INFO "%s: unsupported cable length %d\n",
  884. netdev->name, cable_len);
  885. }
  886. netxen_advert_link_change(adapter, link_status);
  887. /* update link parameters */
  888. if (duplex == LINKEVENT_FULL_DUPLEX)
  889. adapter->link_duplex = DUPLEX_FULL;
  890. else
  891. adapter->link_duplex = DUPLEX_HALF;
  892. adapter->module_type = module;
  893. adapter->link_autoneg = autoneg;
  894. adapter->link_speed = link_speed;
  895. }
  896. static void
  897. netxen_handle_fw_message(int desc_cnt, int index,
  898. struct nx_host_sds_ring *sds_ring)
  899. {
  900. nx_fw_msg_t msg;
  901. struct status_desc *desc;
  902. int i = 0, opcode;
  903. while (desc_cnt > 0 && i < 8) {
  904. desc = &sds_ring->desc_head[index];
  905. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  906. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  907. index = get_next_index(index, sds_ring->num_desc);
  908. desc_cnt--;
  909. }
  910. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  911. switch (opcode) {
  912. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  913. netxen_handle_linkevent(sds_ring->adapter, &msg);
  914. break;
  915. default:
  916. break;
  917. }
  918. }
  919. static int
  920. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  921. struct nx_host_rds_ring *rds_ring,
  922. struct netxen_rx_buffer *buffer)
  923. {
  924. struct sk_buff *skb;
  925. dma_addr_t dma;
  926. struct pci_dev *pdev = adapter->pdev;
  927. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  928. if (!buffer->skb)
  929. return 1;
  930. skb = buffer->skb;
  931. if (!adapter->ahw.cut_through)
  932. skb_reserve(skb, 2);
  933. dma = pci_map_single(pdev, skb->data,
  934. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  935. if (pci_dma_mapping_error(pdev, dma)) {
  936. dev_kfree_skb_any(skb);
  937. buffer->skb = NULL;
  938. return 1;
  939. }
  940. buffer->skb = skb;
  941. buffer->dma = dma;
  942. buffer->state = NETXEN_BUFFER_BUSY;
  943. return 0;
  944. }
  945. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  946. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  947. {
  948. struct netxen_rx_buffer *buffer;
  949. struct sk_buff *skb;
  950. buffer = &rds_ring->rx_buf_arr[index];
  951. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  952. PCI_DMA_FROMDEVICE);
  953. skb = buffer->skb;
  954. if (!skb)
  955. goto no_skb;
  956. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  957. adapter->stats.csummed++;
  958. skb->ip_summed = CHECKSUM_UNNECESSARY;
  959. } else
  960. skb->ip_summed = CHECKSUM_NONE;
  961. skb->dev = adapter->netdev;
  962. buffer->skb = NULL;
  963. no_skb:
  964. buffer->state = NETXEN_BUFFER_FREE;
  965. return skb;
  966. }
  967. static struct netxen_rx_buffer *
  968. netxen_process_rcv(struct netxen_adapter *adapter,
  969. struct nx_host_sds_ring *sds_ring,
  970. int ring, u64 sts_data0)
  971. {
  972. struct net_device *netdev = adapter->netdev;
  973. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  974. struct netxen_rx_buffer *buffer;
  975. struct sk_buff *skb;
  976. struct nx_host_rds_ring *rds_ring;
  977. int index, length, cksum, pkt_offset;
  978. if (unlikely(ring >= adapter->max_rds_rings))
  979. return NULL;
  980. rds_ring = &recv_ctx->rds_rings[ring];
  981. index = netxen_get_sts_refhandle(sts_data0);
  982. if (unlikely(index >= rds_ring->num_desc))
  983. return NULL;
  984. buffer = &rds_ring->rx_buf_arr[index];
  985. length = netxen_get_sts_totallength(sts_data0);
  986. cksum = netxen_get_sts_status(sts_data0);
  987. pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
  988. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  989. if (!skb)
  990. return buffer;
  991. if (length > rds_ring->skb_size)
  992. skb_put(skb, rds_ring->skb_size);
  993. else
  994. skb_put(skb, length);
  995. if (pkt_offset)
  996. skb_pull(skb, pkt_offset);
  997. skb->truesize = skb->len + sizeof(struct sk_buff);
  998. skb->protocol = eth_type_trans(skb, netdev);
  999. napi_gro_receive(&sds_ring->napi, skb);
  1000. adapter->stats.rx_pkts++;
  1001. adapter->stats.rxbytes += length;
  1002. return buffer;
  1003. }
  1004. #define TCP_HDR_SIZE 20
  1005. #define TCP_TS_OPTION_SIZE 12
  1006. #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
  1007. static struct netxen_rx_buffer *
  1008. netxen_process_lro(struct netxen_adapter *adapter,
  1009. struct nx_host_sds_ring *sds_ring,
  1010. int ring, u64 sts_data0, u64 sts_data1)
  1011. {
  1012. struct net_device *netdev = adapter->netdev;
  1013. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1014. struct netxen_rx_buffer *buffer;
  1015. struct sk_buff *skb;
  1016. struct nx_host_rds_ring *rds_ring;
  1017. struct iphdr *iph;
  1018. struct tcphdr *th;
  1019. bool push, timestamp;
  1020. int l2_hdr_offset, l4_hdr_offset;
  1021. int index;
  1022. u16 lro_length, length, data_offset;
  1023. u32 seq_number;
  1024. if (unlikely(ring > adapter->max_rds_rings))
  1025. return NULL;
  1026. rds_ring = &recv_ctx->rds_rings[ring];
  1027. index = netxen_get_lro_sts_refhandle(sts_data0);
  1028. if (unlikely(index > rds_ring->num_desc))
  1029. return NULL;
  1030. buffer = &rds_ring->rx_buf_arr[index];
  1031. timestamp = netxen_get_lro_sts_timestamp(sts_data0);
  1032. lro_length = netxen_get_lro_sts_length(sts_data0);
  1033. l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
  1034. l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
  1035. push = netxen_get_lro_sts_push_flag(sts_data0);
  1036. seq_number = netxen_get_lro_sts_seq_number(sts_data1);
  1037. skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1038. if (!skb)
  1039. return buffer;
  1040. if (timestamp)
  1041. data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
  1042. else
  1043. data_offset = l4_hdr_offset + TCP_HDR_SIZE;
  1044. skb_put(skb, lro_length + data_offset);
  1045. skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb);
  1046. skb_pull(skb, l2_hdr_offset);
  1047. skb->protocol = eth_type_trans(skb, netdev);
  1048. iph = (struct iphdr *)skb->data;
  1049. th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
  1050. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1051. iph->tot_len = htons(length);
  1052. iph->check = 0;
  1053. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1054. th->psh = push;
  1055. th->seq = htonl(seq_number);
  1056. length = skb->len;
  1057. netif_receive_skb(skb);
  1058. adapter->stats.lro_pkts++;
  1059. adapter->stats.rxbytes += length;
  1060. return buffer;
  1061. }
  1062. #define netxen_merge_rx_buffers(list, head) \
  1063. do { list_splice_tail_init(list, head); } while (0);
  1064. int
  1065. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1066. {
  1067. struct netxen_adapter *adapter = sds_ring->adapter;
  1068. struct list_head *cur;
  1069. struct status_desc *desc;
  1070. struct netxen_rx_buffer *rxbuf;
  1071. u32 consumer = sds_ring->consumer;
  1072. int count = 0;
  1073. u64 sts_data0, sts_data1;
  1074. int opcode, ring = 0, desc_cnt;
  1075. while (count < max) {
  1076. desc = &sds_ring->desc_head[consumer];
  1077. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1078. if (!(sts_data0 & STATUS_OWNER_HOST))
  1079. break;
  1080. desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
  1081. opcode = netxen_get_sts_opcode(sts_data0);
  1082. switch (opcode) {
  1083. case NETXEN_NIC_RXPKT_DESC:
  1084. case NETXEN_OLD_RXPKT_DESC:
  1085. case NETXEN_NIC_SYN_OFFLOAD:
  1086. ring = netxen_get_sts_type(sts_data0);
  1087. rxbuf = netxen_process_rcv(adapter, sds_ring,
  1088. ring, sts_data0);
  1089. break;
  1090. case NETXEN_NIC_LRO_DESC:
  1091. ring = netxen_get_lro_sts_type(sts_data0);
  1092. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1093. rxbuf = netxen_process_lro(adapter, sds_ring,
  1094. ring, sts_data0, sts_data1);
  1095. break;
  1096. case NETXEN_NIC_RESPONSE_DESC:
  1097. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1098. default:
  1099. goto skip;
  1100. }
  1101. WARN_ON(desc_cnt > 1);
  1102. if (rxbuf)
  1103. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1104. skip:
  1105. for (; desc_cnt > 0; desc_cnt--) {
  1106. desc = &sds_ring->desc_head[consumer];
  1107. desc->status_desc_data[0] =
  1108. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1109. consumer = get_next_index(consumer, sds_ring->num_desc);
  1110. }
  1111. count++;
  1112. }
  1113. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1114. struct nx_host_rds_ring *rds_ring =
  1115. &adapter->recv_ctx.rds_rings[ring];
  1116. if (!list_empty(&sds_ring->free_list[ring])) {
  1117. list_for_each(cur, &sds_ring->free_list[ring]) {
  1118. rxbuf = list_entry(cur,
  1119. struct netxen_rx_buffer, list);
  1120. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1121. }
  1122. spin_lock(&rds_ring->lock);
  1123. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1124. &rds_ring->free_list);
  1125. spin_unlock(&rds_ring->lock);
  1126. }
  1127. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1128. }
  1129. if (count) {
  1130. sds_ring->consumer = consumer;
  1131. NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
  1132. }
  1133. return count;
  1134. }
  1135. /* Process Command status ring */
  1136. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1137. {
  1138. u32 sw_consumer, hw_consumer;
  1139. int count = 0, i;
  1140. struct netxen_cmd_buffer *buffer;
  1141. struct pci_dev *pdev = adapter->pdev;
  1142. struct net_device *netdev = adapter->netdev;
  1143. struct netxen_skb_frag *frag;
  1144. int done = 0;
  1145. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1146. if (!spin_trylock(&adapter->tx_clean_lock))
  1147. return 1;
  1148. sw_consumer = tx_ring->sw_consumer;
  1149. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1150. while (sw_consumer != hw_consumer) {
  1151. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1152. if (buffer->skb) {
  1153. frag = &buffer->frag_array[0];
  1154. pci_unmap_single(pdev, frag->dma, frag->length,
  1155. PCI_DMA_TODEVICE);
  1156. frag->dma = 0ULL;
  1157. for (i = 1; i < buffer->frag_count; i++) {
  1158. frag++; /* Get the next frag */
  1159. pci_unmap_page(pdev, frag->dma, frag->length,
  1160. PCI_DMA_TODEVICE);
  1161. frag->dma = 0ULL;
  1162. }
  1163. adapter->stats.xmitfinished++;
  1164. dev_kfree_skb_any(buffer->skb);
  1165. buffer->skb = NULL;
  1166. }
  1167. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1168. if (++count >= MAX_STATUS_HANDLE)
  1169. break;
  1170. }
  1171. if (count && netif_running(netdev)) {
  1172. tx_ring->sw_consumer = sw_consumer;
  1173. smp_mb();
  1174. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
  1175. __netif_tx_lock(tx_ring->txq, smp_processor_id());
  1176. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH) {
  1177. netif_wake_queue(netdev);
  1178. adapter->tx_timeo_cnt = 0;
  1179. }
  1180. __netif_tx_unlock(tx_ring->txq);
  1181. }
  1182. }
  1183. /*
  1184. * If everything is freed up to consumer then check if the ring is full
  1185. * If the ring is full then check if more needs to be freed and
  1186. * schedule the call back again.
  1187. *
  1188. * This happens when there are 2 CPUs. One could be freeing and the
  1189. * other filling it. If the ring is full when we get out of here and
  1190. * the card has already interrupted the host then the host can miss the
  1191. * interrupt.
  1192. *
  1193. * There is still a possible race condition and the host could miss an
  1194. * interrupt. The card has to take care of this.
  1195. */
  1196. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1197. done = (sw_consumer == hw_consumer);
  1198. spin_unlock(&adapter->tx_clean_lock);
  1199. return (done);
  1200. }
  1201. void
  1202. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1203. struct nx_host_rds_ring *rds_ring)
  1204. {
  1205. struct rcv_desc *pdesc;
  1206. struct netxen_rx_buffer *buffer;
  1207. int producer, count = 0;
  1208. netxen_ctx_msg msg = 0;
  1209. struct list_head *head;
  1210. producer = rds_ring->producer;
  1211. spin_lock(&rds_ring->lock);
  1212. head = &rds_ring->free_list;
  1213. while (!list_empty(head)) {
  1214. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1215. if (!buffer->skb) {
  1216. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1217. break;
  1218. }
  1219. count++;
  1220. list_del(&buffer->list);
  1221. /* make a rcv descriptor */
  1222. pdesc = &rds_ring->desc_head[producer];
  1223. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1224. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1225. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1226. producer = get_next_index(producer, rds_ring->num_desc);
  1227. }
  1228. spin_unlock(&rds_ring->lock);
  1229. if (count) {
  1230. rds_ring->producer = producer;
  1231. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1232. (producer-1) & (rds_ring->num_desc-1));
  1233. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  1234. /*
  1235. * Write a doorbell msg to tell phanmon of change in
  1236. * receive ring producer
  1237. * Only for firmware version < 4.0.0
  1238. */
  1239. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1240. netxen_set_msg_privid(msg);
  1241. netxen_set_msg_count(msg,
  1242. ((producer - 1) &
  1243. (rds_ring->num_desc - 1)));
  1244. netxen_set_msg_ctxid(msg, adapter->portnum);
  1245. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1246. read_lock(&adapter->adapter_lock);
  1247. writel(msg, DB_NORMALIZE(adapter,
  1248. NETXEN_RCV_PRODUCER_OFFSET));
  1249. read_unlock(&adapter->adapter_lock);
  1250. }
  1251. }
  1252. }
  1253. static void
  1254. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1255. struct nx_host_rds_ring *rds_ring)
  1256. {
  1257. struct rcv_desc *pdesc;
  1258. struct netxen_rx_buffer *buffer;
  1259. int producer, count = 0;
  1260. struct list_head *head;
  1261. producer = rds_ring->producer;
  1262. if (!spin_trylock(&rds_ring->lock))
  1263. return;
  1264. head = &rds_ring->free_list;
  1265. while (!list_empty(head)) {
  1266. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1267. if (!buffer->skb) {
  1268. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1269. break;
  1270. }
  1271. count++;
  1272. list_del(&buffer->list);
  1273. /* make a rcv descriptor */
  1274. pdesc = &rds_ring->desc_head[producer];
  1275. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1276. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1277. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1278. producer = get_next_index(producer, rds_ring->num_desc);
  1279. }
  1280. if (count) {
  1281. rds_ring->producer = producer;
  1282. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1283. (producer - 1) & (rds_ring->num_desc - 1));
  1284. }
  1285. spin_unlock(&rds_ring->lock);
  1286. }
  1287. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1288. {
  1289. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1290. return;
  1291. }