wm8350-core.c 43 KB

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  1. /*
  2. * wm8350-core.c -- Device access for Wolfson WM8350
  3. *
  4. * Copyright 2007, 2008 Wolfson Microelectronics PLC.
  5. *
  6. * Author: Liam Girdwood, Mark Brown
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/init.h>
  17. #include <linux/bug.h>
  18. #include <linux/device.h>
  19. #include <linux/delay.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/workqueue.h>
  22. #include <linux/mfd/wm8350/core.h>
  23. #include <linux/mfd/wm8350/audio.h>
  24. #include <linux/mfd/wm8350/comparator.h>
  25. #include <linux/mfd/wm8350/gpio.h>
  26. #include <linux/mfd/wm8350/pmic.h>
  27. #include <linux/mfd/wm8350/rtc.h>
  28. #include <linux/mfd/wm8350/supply.h>
  29. #include <linux/mfd/wm8350/wdt.h>
  30. #define WM8350_UNLOCK_KEY 0x0013
  31. #define WM8350_LOCK_KEY 0x0000
  32. #define WM8350_CLOCK_CONTROL_1 0x28
  33. #define WM8350_AIF_TEST 0x74
  34. /* debug */
  35. #define WM8350_BUS_DEBUG 0
  36. #if WM8350_BUS_DEBUG
  37. #define dump(regs, src) do { \
  38. int i_; \
  39. u16 *src_ = src; \
  40. printk(KERN_DEBUG); \
  41. for (i_ = 0; i_ < regs; i_++) \
  42. printk(" 0x%4.4x", *src_++); \
  43. printk("\n"); \
  44. } while (0);
  45. #else
  46. #define dump(bytes, src)
  47. #endif
  48. #define WM8350_LOCK_DEBUG 0
  49. #if WM8350_LOCK_DEBUG
  50. #define ldbg(format, arg...) printk(format, ## arg)
  51. #else
  52. #define ldbg(format, arg...)
  53. #endif
  54. /*
  55. * WM8350 Device IO
  56. */
  57. static DEFINE_MUTEX(io_mutex);
  58. static DEFINE_MUTEX(reg_lock_mutex);
  59. /* Perform a physical read from the device.
  60. */
  61. static int wm8350_phys_read(struct wm8350 *wm8350, u8 reg, int num_regs,
  62. u16 *dest)
  63. {
  64. int i, ret;
  65. int bytes = num_regs * 2;
  66. dev_dbg(wm8350->dev, "volatile read\n");
  67. ret = wm8350->read_dev(wm8350, reg, bytes, (char *)dest);
  68. for (i = reg; i < reg + num_regs; i++) {
  69. /* Cache is CPU endian */
  70. dest[i - reg] = be16_to_cpu(dest[i - reg]);
  71. /* Mask out non-readable bits */
  72. dest[i - reg] &= wm8350_reg_io_map[i].readable;
  73. }
  74. dump(num_regs, dest);
  75. return ret;
  76. }
  77. static int wm8350_read(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *dest)
  78. {
  79. int i;
  80. int end = reg + num_regs;
  81. int ret = 0;
  82. int bytes = num_regs * 2;
  83. if (wm8350->read_dev == NULL)
  84. return -ENODEV;
  85. if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
  86. dev_err(wm8350->dev, "invalid reg %x\n",
  87. reg + num_regs - 1);
  88. return -EINVAL;
  89. }
  90. dev_dbg(wm8350->dev,
  91. "%s R%d(0x%2.2x) %d regs\n", __func__, reg, reg, num_regs);
  92. #if WM8350_BUS_DEBUG
  93. /* we can _safely_ read any register, but warn if read not supported */
  94. for (i = reg; i < end; i++) {
  95. if (!wm8350_reg_io_map[i].readable)
  96. dev_warn(wm8350->dev,
  97. "reg R%d is not readable\n", i);
  98. }
  99. #endif
  100. /* if any volatile registers are required, then read back all */
  101. for (i = reg; i < end; i++)
  102. if (wm8350_reg_io_map[i].vol)
  103. return wm8350_phys_read(wm8350, reg, num_regs, dest);
  104. /* no volatiles, then cache is good */
  105. dev_dbg(wm8350->dev, "cache read\n");
  106. memcpy(dest, &wm8350->reg_cache[reg], bytes);
  107. dump(num_regs, dest);
  108. return ret;
  109. }
  110. static inline int is_reg_locked(struct wm8350 *wm8350, u8 reg)
  111. {
  112. if (reg == WM8350_SECURITY ||
  113. wm8350->reg_cache[WM8350_SECURITY] == WM8350_UNLOCK_KEY)
  114. return 0;
  115. if ((reg == WM8350_GPIO_CONFIGURATION_I_O) ||
  116. (reg >= WM8350_GPIO_FUNCTION_SELECT_1 &&
  117. reg <= WM8350_GPIO_FUNCTION_SELECT_4) ||
  118. (reg >= WM8350_BATTERY_CHARGER_CONTROL_1 &&
  119. reg <= WM8350_BATTERY_CHARGER_CONTROL_3))
  120. return 1;
  121. return 0;
  122. }
  123. static int wm8350_write(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *src)
  124. {
  125. int i;
  126. int end = reg + num_regs;
  127. int bytes = num_regs * 2;
  128. if (wm8350->write_dev == NULL)
  129. return -ENODEV;
  130. if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
  131. dev_err(wm8350->dev, "invalid reg %x\n",
  132. reg + num_regs - 1);
  133. return -EINVAL;
  134. }
  135. /* it's generally not a good idea to write to RO or locked registers */
  136. for (i = reg; i < end; i++) {
  137. if (!wm8350_reg_io_map[i].writable) {
  138. dev_err(wm8350->dev,
  139. "attempted write to read only reg R%d\n", i);
  140. return -EINVAL;
  141. }
  142. if (is_reg_locked(wm8350, i)) {
  143. dev_err(wm8350->dev,
  144. "attempted write to locked reg R%d\n", i);
  145. return -EINVAL;
  146. }
  147. src[i - reg] &= wm8350_reg_io_map[i].writable;
  148. wm8350->reg_cache[i] =
  149. (wm8350->reg_cache[i] & ~wm8350_reg_io_map[i].writable)
  150. | src[i - reg];
  151. src[i - reg] = cpu_to_be16(src[i - reg]);
  152. }
  153. /* Actually write it out */
  154. return wm8350->write_dev(wm8350, reg, bytes, (char *)src);
  155. }
  156. /*
  157. * Safe read, modify, write methods
  158. */
  159. int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
  160. {
  161. u16 data;
  162. int err;
  163. mutex_lock(&io_mutex);
  164. err = wm8350_read(wm8350, reg, 1, &data);
  165. if (err) {
  166. dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
  167. goto out;
  168. }
  169. data &= ~mask;
  170. err = wm8350_write(wm8350, reg, 1, &data);
  171. if (err)
  172. dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
  173. out:
  174. mutex_unlock(&io_mutex);
  175. return err;
  176. }
  177. EXPORT_SYMBOL_GPL(wm8350_clear_bits);
  178. int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
  179. {
  180. u16 data;
  181. int err;
  182. mutex_lock(&io_mutex);
  183. err = wm8350_read(wm8350, reg, 1, &data);
  184. if (err) {
  185. dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
  186. goto out;
  187. }
  188. data |= mask;
  189. err = wm8350_write(wm8350, reg, 1, &data);
  190. if (err)
  191. dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
  192. out:
  193. mutex_unlock(&io_mutex);
  194. return err;
  195. }
  196. EXPORT_SYMBOL_GPL(wm8350_set_bits);
  197. u16 wm8350_reg_read(struct wm8350 *wm8350, int reg)
  198. {
  199. u16 data;
  200. int err;
  201. mutex_lock(&io_mutex);
  202. err = wm8350_read(wm8350, reg, 1, &data);
  203. if (err)
  204. dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
  205. mutex_unlock(&io_mutex);
  206. return data;
  207. }
  208. EXPORT_SYMBOL_GPL(wm8350_reg_read);
  209. int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val)
  210. {
  211. int ret;
  212. u16 data = val;
  213. mutex_lock(&io_mutex);
  214. ret = wm8350_write(wm8350, reg, 1, &data);
  215. if (ret)
  216. dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
  217. mutex_unlock(&io_mutex);
  218. return ret;
  219. }
  220. EXPORT_SYMBOL_GPL(wm8350_reg_write);
  221. int wm8350_block_read(struct wm8350 *wm8350, int start_reg, int regs,
  222. u16 *dest)
  223. {
  224. int err = 0;
  225. mutex_lock(&io_mutex);
  226. err = wm8350_read(wm8350, start_reg, regs, dest);
  227. if (err)
  228. dev_err(wm8350->dev, "block read starting from R%d failed\n",
  229. start_reg);
  230. mutex_unlock(&io_mutex);
  231. return err;
  232. }
  233. EXPORT_SYMBOL_GPL(wm8350_block_read);
  234. int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs,
  235. u16 *src)
  236. {
  237. int ret = 0;
  238. mutex_lock(&io_mutex);
  239. ret = wm8350_write(wm8350, start_reg, regs, src);
  240. if (ret)
  241. dev_err(wm8350->dev, "block write starting at R%d failed\n",
  242. start_reg);
  243. mutex_unlock(&io_mutex);
  244. return ret;
  245. }
  246. EXPORT_SYMBOL_GPL(wm8350_block_write);
  247. /**
  248. * wm8350_reg_lock()
  249. *
  250. * The WM8350 has a hardware lock which can be used to prevent writes to
  251. * some registers (generally those which can cause particularly serious
  252. * problems if misused). This function enables that lock.
  253. */
  254. int wm8350_reg_lock(struct wm8350 *wm8350)
  255. {
  256. u16 key = WM8350_LOCK_KEY;
  257. int ret;
  258. ldbg(__func__);
  259. mutex_lock(&io_mutex);
  260. ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
  261. if (ret)
  262. dev_err(wm8350->dev, "lock failed\n");
  263. mutex_unlock(&io_mutex);
  264. return ret;
  265. }
  266. EXPORT_SYMBOL_GPL(wm8350_reg_lock);
  267. /**
  268. * wm8350_reg_unlock()
  269. *
  270. * The WM8350 has a hardware lock which can be used to prevent writes to
  271. * some registers (generally those which can cause particularly serious
  272. * problems if misused). This function disables that lock so updates
  273. * can be performed. For maximum safety this should be done only when
  274. * required.
  275. */
  276. int wm8350_reg_unlock(struct wm8350 *wm8350)
  277. {
  278. u16 key = WM8350_UNLOCK_KEY;
  279. int ret;
  280. ldbg(__func__);
  281. mutex_lock(&io_mutex);
  282. ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
  283. if (ret)
  284. dev_err(wm8350->dev, "unlock failed\n");
  285. mutex_unlock(&io_mutex);
  286. return ret;
  287. }
  288. EXPORT_SYMBOL_GPL(wm8350_reg_unlock);
  289. static void wm8350_irq_call_handler(struct wm8350 *wm8350, int irq)
  290. {
  291. mutex_lock(&wm8350->irq_mutex);
  292. if (wm8350->irq[irq].handler)
  293. wm8350->irq[irq].handler(wm8350, irq, wm8350->irq[irq].data);
  294. else {
  295. dev_err(wm8350->dev, "irq %d nobody cared. now masked.\n",
  296. irq);
  297. wm8350_mask_irq(wm8350, irq);
  298. }
  299. mutex_unlock(&wm8350->irq_mutex);
  300. }
  301. /*
  302. * This is a threaded IRQ handler so can access I2C/SPI. Since all
  303. * interrupts are clear on read the IRQ line will be reasserted and
  304. * the physical IRQ will be handled again if another interrupt is
  305. * asserted while we run - in the normal course of events this is a
  306. * rare occurrence so we save I2C/SPI reads.
  307. */
  308. static irqreturn_t wm8350_irq(int irq, void *data)
  309. {
  310. struct wm8350 *wm8350 = data;
  311. u16 level_one, status1, status2, comp;
  312. /* TODO: Use block reads to improve performance? */
  313. level_one = wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS)
  314. & ~wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK);
  315. status1 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_1)
  316. & ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_1_MASK);
  317. status2 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_2)
  318. & ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_2_MASK);
  319. comp = wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS)
  320. & ~wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS_MASK);
  321. /* over current */
  322. if (level_one & WM8350_OC_INT) {
  323. u16 oc;
  324. oc = wm8350_reg_read(wm8350, WM8350_OVER_CURRENT_INT_STATUS);
  325. oc &= ~wm8350_reg_read(wm8350,
  326. WM8350_OVER_CURRENT_INT_STATUS_MASK);
  327. if (oc & WM8350_OC_LS_EINT) /* limit switch */
  328. wm8350_irq_call_handler(wm8350, WM8350_IRQ_OC_LS);
  329. }
  330. /* under voltage */
  331. if (level_one & WM8350_UV_INT) {
  332. u16 uv;
  333. uv = wm8350_reg_read(wm8350, WM8350_UNDER_VOLTAGE_INT_STATUS);
  334. uv &= ~wm8350_reg_read(wm8350,
  335. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK);
  336. if (uv & WM8350_UV_DC1_EINT)
  337. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC1);
  338. if (uv & WM8350_UV_DC2_EINT)
  339. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC2);
  340. if (uv & WM8350_UV_DC3_EINT)
  341. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC3);
  342. if (uv & WM8350_UV_DC4_EINT)
  343. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC4);
  344. if (uv & WM8350_UV_DC5_EINT)
  345. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC5);
  346. if (uv & WM8350_UV_DC6_EINT)
  347. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC6);
  348. if (uv & WM8350_UV_LDO1_EINT)
  349. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO1);
  350. if (uv & WM8350_UV_LDO2_EINT)
  351. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO2);
  352. if (uv & WM8350_UV_LDO3_EINT)
  353. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO3);
  354. if (uv & WM8350_UV_LDO4_EINT)
  355. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO4);
  356. }
  357. /* charger, RTC */
  358. if (status1) {
  359. if (status1 & WM8350_CHG_BAT_HOT_EINT)
  360. wm8350_irq_call_handler(wm8350,
  361. WM8350_IRQ_CHG_BAT_HOT);
  362. if (status1 & WM8350_CHG_BAT_COLD_EINT)
  363. wm8350_irq_call_handler(wm8350,
  364. WM8350_IRQ_CHG_BAT_COLD);
  365. if (status1 & WM8350_CHG_BAT_FAIL_EINT)
  366. wm8350_irq_call_handler(wm8350,
  367. WM8350_IRQ_CHG_BAT_FAIL);
  368. if (status1 & WM8350_CHG_TO_EINT)
  369. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_TO);
  370. if (status1 & WM8350_CHG_END_EINT)
  371. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_END);
  372. if (status1 & WM8350_CHG_START_EINT)
  373. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_START);
  374. if (status1 & WM8350_CHG_FAST_RDY_EINT)
  375. wm8350_irq_call_handler(wm8350,
  376. WM8350_IRQ_CHG_FAST_RDY);
  377. if (status1 & WM8350_CHG_VBATT_LT_3P9_EINT)
  378. wm8350_irq_call_handler(wm8350,
  379. WM8350_IRQ_CHG_VBATT_LT_3P9);
  380. if (status1 & WM8350_CHG_VBATT_LT_3P1_EINT)
  381. wm8350_irq_call_handler(wm8350,
  382. WM8350_IRQ_CHG_VBATT_LT_3P1);
  383. if (status1 & WM8350_CHG_VBATT_LT_2P85_EINT)
  384. wm8350_irq_call_handler(wm8350,
  385. WM8350_IRQ_CHG_VBATT_LT_2P85);
  386. if (status1 & WM8350_RTC_ALM_EINT)
  387. wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_ALM);
  388. if (status1 & WM8350_RTC_SEC_EINT)
  389. wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_SEC);
  390. if (status1 & WM8350_RTC_PER_EINT)
  391. wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_PER);
  392. }
  393. /* current sink, system, aux adc */
  394. if (status2) {
  395. if (status2 & WM8350_CS1_EINT)
  396. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS1);
  397. if (status2 & WM8350_CS2_EINT)
  398. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS2);
  399. if (status2 & WM8350_SYS_HYST_COMP_FAIL_EINT)
  400. wm8350_irq_call_handler(wm8350,
  401. WM8350_IRQ_SYS_HYST_COMP_FAIL);
  402. if (status2 & WM8350_SYS_CHIP_GT115_EINT)
  403. wm8350_irq_call_handler(wm8350,
  404. WM8350_IRQ_SYS_CHIP_GT115);
  405. if (status2 & WM8350_SYS_CHIP_GT140_EINT)
  406. wm8350_irq_call_handler(wm8350,
  407. WM8350_IRQ_SYS_CHIP_GT140);
  408. if (status2 & WM8350_SYS_WDOG_TO_EINT)
  409. wm8350_irq_call_handler(wm8350,
  410. WM8350_IRQ_SYS_WDOG_TO);
  411. if (status2 & WM8350_AUXADC_DATARDY_EINT)
  412. wm8350_irq_call_handler(wm8350,
  413. WM8350_IRQ_AUXADC_DATARDY);
  414. if (status2 & WM8350_AUXADC_DCOMP4_EINT)
  415. wm8350_irq_call_handler(wm8350,
  416. WM8350_IRQ_AUXADC_DCOMP4);
  417. if (status2 & WM8350_AUXADC_DCOMP3_EINT)
  418. wm8350_irq_call_handler(wm8350,
  419. WM8350_IRQ_AUXADC_DCOMP3);
  420. if (status2 & WM8350_AUXADC_DCOMP2_EINT)
  421. wm8350_irq_call_handler(wm8350,
  422. WM8350_IRQ_AUXADC_DCOMP2);
  423. if (status2 & WM8350_AUXADC_DCOMP1_EINT)
  424. wm8350_irq_call_handler(wm8350,
  425. WM8350_IRQ_AUXADC_DCOMP1);
  426. if (status2 & WM8350_USB_LIMIT_EINT)
  427. wm8350_irq_call_handler(wm8350, WM8350_IRQ_USB_LIMIT);
  428. }
  429. /* wake, codec, ext */
  430. if (comp) {
  431. if (comp & WM8350_WKUP_OFF_STATE_EINT)
  432. wm8350_irq_call_handler(wm8350,
  433. WM8350_IRQ_WKUP_OFF_STATE);
  434. if (comp & WM8350_WKUP_HIB_STATE_EINT)
  435. wm8350_irq_call_handler(wm8350,
  436. WM8350_IRQ_WKUP_HIB_STATE);
  437. if (comp & WM8350_WKUP_CONV_FAULT_EINT)
  438. wm8350_irq_call_handler(wm8350,
  439. WM8350_IRQ_WKUP_CONV_FAULT);
  440. if (comp & WM8350_WKUP_WDOG_RST_EINT)
  441. wm8350_irq_call_handler(wm8350,
  442. WM8350_IRQ_WKUP_WDOG_RST);
  443. if (comp & WM8350_WKUP_GP_PWR_ON_EINT)
  444. wm8350_irq_call_handler(wm8350,
  445. WM8350_IRQ_WKUP_GP_PWR_ON);
  446. if (comp & WM8350_WKUP_ONKEY_EINT)
  447. wm8350_irq_call_handler(wm8350, WM8350_IRQ_WKUP_ONKEY);
  448. if (comp & WM8350_WKUP_GP_WAKEUP_EINT)
  449. wm8350_irq_call_handler(wm8350,
  450. WM8350_IRQ_WKUP_GP_WAKEUP);
  451. if (comp & WM8350_CODEC_JCK_DET_L_EINT)
  452. wm8350_irq_call_handler(wm8350,
  453. WM8350_IRQ_CODEC_JCK_DET_L);
  454. if (comp & WM8350_CODEC_JCK_DET_R_EINT)
  455. wm8350_irq_call_handler(wm8350,
  456. WM8350_IRQ_CODEC_JCK_DET_R);
  457. if (comp & WM8350_CODEC_MICSCD_EINT)
  458. wm8350_irq_call_handler(wm8350,
  459. WM8350_IRQ_CODEC_MICSCD);
  460. if (comp & WM8350_CODEC_MICD_EINT)
  461. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CODEC_MICD);
  462. if (comp & WM8350_EXT_USB_FB_EINT)
  463. wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_USB_FB);
  464. if (comp & WM8350_EXT_WALL_FB_EINT)
  465. wm8350_irq_call_handler(wm8350,
  466. WM8350_IRQ_EXT_WALL_FB);
  467. if (comp & WM8350_EXT_BAT_FB_EINT)
  468. wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_BAT_FB);
  469. }
  470. if (level_one & WM8350_GP_INT) {
  471. int i;
  472. u16 gpio;
  473. gpio = wm8350_reg_read(wm8350, WM8350_GPIO_INT_STATUS);
  474. gpio &= ~wm8350_reg_read(wm8350,
  475. WM8350_GPIO_INT_STATUS_MASK);
  476. for (i = 0; i < 12; i++) {
  477. if (gpio & (1 << i))
  478. wm8350_irq_call_handler(wm8350,
  479. WM8350_IRQ_GPIO(i));
  480. }
  481. }
  482. return IRQ_HANDLED;
  483. }
  484. int wm8350_register_irq(struct wm8350 *wm8350, int irq,
  485. void (*handler) (struct wm8350 *, int, void *),
  486. void *data)
  487. {
  488. if (irq < 0 || irq > WM8350_NUM_IRQ || !handler)
  489. return -EINVAL;
  490. if (wm8350->irq[irq].handler)
  491. return -EBUSY;
  492. mutex_lock(&wm8350->irq_mutex);
  493. wm8350->irq[irq].handler = handler;
  494. wm8350->irq[irq].data = data;
  495. mutex_unlock(&wm8350->irq_mutex);
  496. return 0;
  497. }
  498. EXPORT_SYMBOL_GPL(wm8350_register_irq);
  499. int wm8350_free_irq(struct wm8350 *wm8350, int irq)
  500. {
  501. if (irq < 0 || irq > WM8350_NUM_IRQ)
  502. return -EINVAL;
  503. mutex_lock(&wm8350->irq_mutex);
  504. wm8350->irq[irq].handler = NULL;
  505. mutex_unlock(&wm8350->irq_mutex);
  506. return 0;
  507. }
  508. EXPORT_SYMBOL_GPL(wm8350_free_irq);
  509. int wm8350_mask_irq(struct wm8350 *wm8350, int irq)
  510. {
  511. switch (irq) {
  512. case WM8350_IRQ_CHG_BAT_HOT:
  513. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  514. WM8350_IM_CHG_BAT_HOT_EINT);
  515. case WM8350_IRQ_CHG_BAT_COLD:
  516. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  517. WM8350_IM_CHG_BAT_COLD_EINT);
  518. case WM8350_IRQ_CHG_BAT_FAIL:
  519. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  520. WM8350_IM_CHG_BAT_FAIL_EINT);
  521. case WM8350_IRQ_CHG_TO:
  522. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  523. WM8350_IM_CHG_TO_EINT);
  524. case WM8350_IRQ_CHG_END:
  525. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  526. WM8350_IM_CHG_END_EINT);
  527. case WM8350_IRQ_CHG_START:
  528. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  529. WM8350_IM_CHG_START_EINT);
  530. case WM8350_IRQ_CHG_FAST_RDY:
  531. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  532. WM8350_IM_CHG_FAST_RDY_EINT);
  533. case WM8350_IRQ_RTC_PER:
  534. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  535. WM8350_IM_RTC_PER_EINT);
  536. case WM8350_IRQ_RTC_SEC:
  537. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  538. WM8350_IM_RTC_SEC_EINT);
  539. case WM8350_IRQ_RTC_ALM:
  540. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  541. WM8350_IM_RTC_ALM_EINT);
  542. case WM8350_IRQ_CHG_VBATT_LT_3P9:
  543. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  544. WM8350_IM_CHG_VBATT_LT_3P9_EINT);
  545. case WM8350_IRQ_CHG_VBATT_LT_3P1:
  546. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  547. WM8350_IM_CHG_VBATT_LT_3P1_EINT);
  548. case WM8350_IRQ_CHG_VBATT_LT_2P85:
  549. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  550. WM8350_IM_CHG_VBATT_LT_2P85_EINT);
  551. case WM8350_IRQ_CS1:
  552. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  553. WM8350_IM_CS1_EINT);
  554. case WM8350_IRQ_CS2:
  555. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  556. WM8350_IM_CS2_EINT);
  557. case WM8350_IRQ_USB_LIMIT:
  558. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  559. WM8350_IM_USB_LIMIT_EINT);
  560. case WM8350_IRQ_AUXADC_DATARDY:
  561. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  562. WM8350_IM_AUXADC_DATARDY_EINT);
  563. case WM8350_IRQ_AUXADC_DCOMP4:
  564. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  565. WM8350_IM_AUXADC_DCOMP4_EINT);
  566. case WM8350_IRQ_AUXADC_DCOMP3:
  567. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  568. WM8350_IM_AUXADC_DCOMP3_EINT);
  569. case WM8350_IRQ_AUXADC_DCOMP2:
  570. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  571. WM8350_IM_AUXADC_DCOMP2_EINT);
  572. case WM8350_IRQ_AUXADC_DCOMP1:
  573. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  574. WM8350_IM_AUXADC_DCOMP1_EINT);
  575. case WM8350_IRQ_SYS_HYST_COMP_FAIL:
  576. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  577. WM8350_IM_SYS_HYST_COMP_FAIL_EINT);
  578. case WM8350_IRQ_SYS_CHIP_GT115:
  579. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  580. WM8350_IM_SYS_CHIP_GT115_EINT);
  581. case WM8350_IRQ_SYS_CHIP_GT140:
  582. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  583. WM8350_IM_SYS_CHIP_GT140_EINT);
  584. case WM8350_IRQ_SYS_WDOG_TO:
  585. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  586. WM8350_IM_SYS_WDOG_TO_EINT);
  587. case WM8350_IRQ_UV_LDO4:
  588. return wm8350_set_bits(wm8350,
  589. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  590. WM8350_IM_UV_LDO4_EINT);
  591. case WM8350_IRQ_UV_LDO3:
  592. return wm8350_set_bits(wm8350,
  593. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  594. WM8350_IM_UV_LDO3_EINT);
  595. case WM8350_IRQ_UV_LDO2:
  596. return wm8350_set_bits(wm8350,
  597. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  598. WM8350_IM_UV_LDO2_EINT);
  599. case WM8350_IRQ_UV_LDO1:
  600. return wm8350_set_bits(wm8350,
  601. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  602. WM8350_IM_UV_LDO1_EINT);
  603. case WM8350_IRQ_UV_DC6:
  604. return wm8350_set_bits(wm8350,
  605. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  606. WM8350_IM_UV_DC6_EINT);
  607. case WM8350_IRQ_UV_DC5:
  608. return wm8350_set_bits(wm8350,
  609. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  610. WM8350_IM_UV_DC5_EINT);
  611. case WM8350_IRQ_UV_DC4:
  612. return wm8350_set_bits(wm8350,
  613. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  614. WM8350_IM_UV_DC4_EINT);
  615. case WM8350_IRQ_UV_DC3:
  616. return wm8350_set_bits(wm8350,
  617. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  618. WM8350_IM_UV_DC3_EINT);
  619. case WM8350_IRQ_UV_DC2:
  620. return wm8350_set_bits(wm8350,
  621. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  622. WM8350_IM_UV_DC2_EINT);
  623. case WM8350_IRQ_UV_DC1:
  624. return wm8350_set_bits(wm8350,
  625. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  626. WM8350_IM_UV_DC1_EINT);
  627. case WM8350_IRQ_OC_LS:
  628. return wm8350_set_bits(wm8350,
  629. WM8350_OVER_CURRENT_INT_STATUS_MASK,
  630. WM8350_IM_OC_LS_EINT);
  631. case WM8350_IRQ_EXT_USB_FB:
  632. return wm8350_set_bits(wm8350,
  633. WM8350_COMPARATOR_INT_STATUS_MASK,
  634. WM8350_IM_EXT_USB_FB_EINT);
  635. case WM8350_IRQ_EXT_WALL_FB:
  636. return wm8350_set_bits(wm8350,
  637. WM8350_COMPARATOR_INT_STATUS_MASK,
  638. WM8350_IM_EXT_WALL_FB_EINT);
  639. case WM8350_IRQ_EXT_BAT_FB:
  640. return wm8350_set_bits(wm8350,
  641. WM8350_COMPARATOR_INT_STATUS_MASK,
  642. WM8350_IM_EXT_BAT_FB_EINT);
  643. case WM8350_IRQ_CODEC_JCK_DET_L:
  644. return wm8350_set_bits(wm8350,
  645. WM8350_COMPARATOR_INT_STATUS_MASK,
  646. WM8350_IM_CODEC_JCK_DET_L_EINT);
  647. case WM8350_IRQ_CODEC_JCK_DET_R:
  648. return wm8350_set_bits(wm8350,
  649. WM8350_COMPARATOR_INT_STATUS_MASK,
  650. WM8350_IM_CODEC_JCK_DET_R_EINT);
  651. case WM8350_IRQ_CODEC_MICSCD:
  652. return wm8350_set_bits(wm8350,
  653. WM8350_COMPARATOR_INT_STATUS_MASK,
  654. WM8350_IM_CODEC_MICSCD_EINT);
  655. case WM8350_IRQ_CODEC_MICD:
  656. return wm8350_set_bits(wm8350,
  657. WM8350_COMPARATOR_INT_STATUS_MASK,
  658. WM8350_IM_CODEC_MICD_EINT);
  659. case WM8350_IRQ_WKUP_OFF_STATE:
  660. return wm8350_set_bits(wm8350,
  661. WM8350_COMPARATOR_INT_STATUS_MASK,
  662. WM8350_IM_WKUP_OFF_STATE_EINT);
  663. case WM8350_IRQ_WKUP_HIB_STATE:
  664. return wm8350_set_bits(wm8350,
  665. WM8350_COMPARATOR_INT_STATUS_MASK,
  666. WM8350_IM_WKUP_HIB_STATE_EINT);
  667. case WM8350_IRQ_WKUP_CONV_FAULT:
  668. return wm8350_set_bits(wm8350,
  669. WM8350_COMPARATOR_INT_STATUS_MASK,
  670. WM8350_IM_WKUP_CONV_FAULT_EINT);
  671. case WM8350_IRQ_WKUP_WDOG_RST:
  672. return wm8350_set_bits(wm8350,
  673. WM8350_COMPARATOR_INT_STATUS_MASK,
  674. WM8350_IM_WKUP_OFF_STATE_EINT);
  675. case WM8350_IRQ_WKUP_GP_PWR_ON:
  676. return wm8350_set_bits(wm8350,
  677. WM8350_COMPARATOR_INT_STATUS_MASK,
  678. WM8350_IM_WKUP_GP_PWR_ON_EINT);
  679. case WM8350_IRQ_WKUP_ONKEY:
  680. return wm8350_set_bits(wm8350,
  681. WM8350_COMPARATOR_INT_STATUS_MASK,
  682. WM8350_IM_WKUP_ONKEY_EINT);
  683. case WM8350_IRQ_WKUP_GP_WAKEUP:
  684. return wm8350_set_bits(wm8350,
  685. WM8350_COMPARATOR_INT_STATUS_MASK,
  686. WM8350_IM_WKUP_GP_WAKEUP_EINT);
  687. case WM8350_IRQ_GPIO(0):
  688. return wm8350_set_bits(wm8350,
  689. WM8350_GPIO_INT_STATUS_MASK,
  690. WM8350_IM_GP0_EINT);
  691. case WM8350_IRQ_GPIO(1):
  692. return wm8350_set_bits(wm8350,
  693. WM8350_GPIO_INT_STATUS_MASK,
  694. WM8350_IM_GP1_EINT);
  695. case WM8350_IRQ_GPIO(2):
  696. return wm8350_set_bits(wm8350,
  697. WM8350_GPIO_INT_STATUS_MASK,
  698. WM8350_IM_GP2_EINT);
  699. case WM8350_IRQ_GPIO(3):
  700. return wm8350_set_bits(wm8350,
  701. WM8350_GPIO_INT_STATUS_MASK,
  702. WM8350_IM_GP3_EINT);
  703. case WM8350_IRQ_GPIO(4):
  704. return wm8350_set_bits(wm8350,
  705. WM8350_GPIO_INT_STATUS_MASK,
  706. WM8350_IM_GP4_EINT);
  707. case WM8350_IRQ_GPIO(5):
  708. return wm8350_set_bits(wm8350,
  709. WM8350_GPIO_INT_STATUS_MASK,
  710. WM8350_IM_GP5_EINT);
  711. case WM8350_IRQ_GPIO(6):
  712. return wm8350_set_bits(wm8350,
  713. WM8350_GPIO_INT_STATUS_MASK,
  714. WM8350_IM_GP6_EINT);
  715. case WM8350_IRQ_GPIO(7):
  716. return wm8350_set_bits(wm8350,
  717. WM8350_GPIO_INT_STATUS_MASK,
  718. WM8350_IM_GP7_EINT);
  719. case WM8350_IRQ_GPIO(8):
  720. return wm8350_set_bits(wm8350,
  721. WM8350_GPIO_INT_STATUS_MASK,
  722. WM8350_IM_GP8_EINT);
  723. case WM8350_IRQ_GPIO(9):
  724. return wm8350_set_bits(wm8350,
  725. WM8350_GPIO_INT_STATUS_MASK,
  726. WM8350_IM_GP9_EINT);
  727. case WM8350_IRQ_GPIO(10):
  728. return wm8350_set_bits(wm8350,
  729. WM8350_GPIO_INT_STATUS_MASK,
  730. WM8350_IM_GP10_EINT);
  731. case WM8350_IRQ_GPIO(11):
  732. return wm8350_set_bits(wm8350,
  733. WM8350_GPIO_INT_STATUS_MASK,
  734. WM8350_IM_GP11_EINT);
  735. case WM8350_IRQ_GPIO(12):
  736. return wm8350_set_bits(wm8350,
  737. WM8350_GPIO_INT_STATUS_MASK,
  738. WM8350_IM_GP12_EINT);
  739. default:
  740. dev_warn(wm8350->dev, "Attempting to mask unknown IRQ %d\n",
  741. irq);
  742. return -EINVAL;
  743. }
  744. return 0;
  745. }
  746. EXPORT_SYMBOL_GPL(wm8350_mask_irq);
  747. int wm8350_unmask_irq(struct wm8350 *wm8350, int irq)
  748. {
  749. switch (irq) {
  750. case WM8350_IRQ_CHG_BAT_HOT:
  751. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  752. WM8350_IM_CHG_BAT_HOT_EINT);
  753. case WM8350_IRQ_CHG_BAT_COLD:
  754. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  755. WM8350_IM_CHG_BAT_COLD_EINT);
  756. case WM8350_IRQ_CHG_BAT_FAIL:
  757. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  758. WM8350_IM_CHG_BAT_FAIL_EINT);
  759. case WM8350_IRQ_CHG_TO:
  760. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  761. WM8350_IM_CHG_TO_EINT);
  762. case WM8350_IRQ_CHG_END:
  763. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  764. WM8350_IM_CHG_END_EINT);
  765. case WM8350_IRQ_CHG_START:
  766. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  767. WM8350_IM_CHG_START_EINT);
  768. case WM8350_IRQ_CHG_FAST_RDY:
  769. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  770. WM8350_IM_CHG_FAST_RDY_EINT);
  771. case WM8350_IRQ_RTC_PER:
  772. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  773. WM8350_IM_RTC_PER_EINT);
  774. case WM8350_IRQ_RTC_SEC:
  775. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  776. WM8350_IM_RTC_SEC_EINT);
  777. case WM8350_IRQ_RTC_ALM:
  778. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  779. WM8350_IM_RTC_ALM_EINT);
  780. case WM8350_IRQ_CHG_VBATT_LT_3P9:
  781. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  782. WM8350_IM_CHG_VBATT_LT_3P9_EINT);
  783. case WM8350_IRQ_CHG_VBATT_LT_3P1:
  784. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  785. WM8350_IM_CHG_VBATT_LT_3P1_EINT);
  786. case WM8350_IRQ_CHG_VBATT_LT_2P85:
  787. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  788. WM8350_IM_CHG_VBATT_LT_2P85_EINT);
  789. case WM8350_IRQ_CS1:
  790. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  791. WM8350_IM_CS1_EINT);
  792. case WM8350_IRQ_CS2:
  793. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  794. WM8350_IM_CS2_EINT);
  795. case WM8350_IRQ_USB_LIMIT:
  796. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  797. WM8350_IM_USB_LIMIT_EINT);
  798. case WM8350_IRQ_AUXADC_DATARDY:
  799. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  800. WM8350_IM_AUXADC_DATARDY_EINT);
  801. case WM8350_IRQ_AUXADC_DCOMP4:
  802. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  803. WM8350_IM_AUXADC_DCOMP4_EINT);
  804. case WM8350_IRQ_AUXADC_DCOMP3:
  805. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  806. WM8350_IM_AUXADC_DCOMP3_EINT);
  807. case WM8350_IRQ_AUXADC_DCOMP2:
  808. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  809. WM8350_IM_AUXADC_DCOMP2_EINT);
  810. case WM8350_IRQ_AUXADC_DCOMP1:
  811. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  812. WM8350_IM_AUXADC_DCOMP1_EINT);
  813. case WM8350_IRQ_SYS_HYST_COMP_FAIL:
  814. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  815. WM8350_IM_SYS_HYST_COMP_FAIL_EINT);
  816. case WM8350_IRQ_SYS_CHIP_GT115:
  817. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  818. WM8350_IM_SYS_CHIP_GT115_EINT);
  819. case WM8350_IRQ_SYS_CHIP_GT140:
  820. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  821. WM8350_IM_SYS_CHIP_GT140_EINT);
  822. case WM8350_IRQ_SYS_WDOG_TO:
  823. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  824. WM8350_IM_SYS_WDOG_TO_EINT);
  825. case WM8350_IRQ_UV_LDO4:
  826. return wm8350_clear_bits(wm8350,
  827. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  828. WM8350_IM_UV_LDO4_EINT);
  829. case WM8350_IRQ_UV_LDO3:
  830. return wm8350_clear_bits(wm8350,
  831. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  832. WM8350_IM_UV_LDO3_EINT);
  833. case WM8350_IRQ_UV_LDO2:
  834. return wm8350_clear_bits(wm8350,
  835. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  836. WM8350_IM_UV_LDO2_EINT);
  837. case WM8350_IRQ_UV_LDO1:
  838. return wm8350_clear_bits(wm8350,
  839. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  840. WM8350_IM_UV_LDO1_EINT);
  841. case WM8350_IRQ_UV_DC6:
  842. return wm8350_clear_bits(wm8350,
  843. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  844. WM8350_IM_UV_DC6_EINT);
  845. case WM8350_IRQ_UV_DC5:
  846. return wm8350_clear_bits(wm8350,
  847. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  848. WM8350_IM_UV_DC5_EINT);
  849. case WM8350_IRQ_UV_DC4:
  850. return wm8350_clear_bits(wm8350,
  851. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  852. WM8350_IM_UV_DC4_EINT);
  853. case WM8350_IRQ_UV_DC3:
  854. return wm8350_clear_bits(wm8350,
  855. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  856. WM8350_IM_UV_DC3_EINT);
  857. case WM8350_IRQ_UV_DC2:
  858. return wm8350_clear_bits(wm8350,
  859. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  860. WM8350_IM_UV_DC2_EINT);
  861. case WM8350_IRQ_UV_DC1:
  862. return wm8350_clear_bits(wm8350,
  863. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  864. WM8350_IM_UV_DC1_EINT);
  865. case WM8350_IRQ_OC_LS:
  866. return wm8350_clear_bits(wm8350,
  867. WM8350_OVER_CURRENT_INT_STATUS_MASK,
  868. WM8350_IM_OC_LS_EINT);
  869. case WM8350_IRQ_EXT_USB_FB:
  870. return wm8350_clear_bits(wm8350,
  871. WM8350_COMPARATOR_INT_STATUS_MASK,
  872. WM8350_IM_EXT_USB_FB_EINT);
  873. case WM8350_IRQ_EXT_WALL_FB:
  874. return wm8350_clear_bits(wm8350,
  875. WM8350_COMPARATOR_INT_STATUS_MASK,
  876. WM8350_IM_EXT_WALL_FB_EINT);
  877. case WM8350_IRQ_EXT_BAT_FB:
  878. return wm8350_clear_bits(wm8350,
  879. WM8350_COMPARATOR_INT_STATUS_MASK,
  880. WM8350_IM_EXT_BAT_FB_EINT);
  881. case WM8350_IRQ_CODEC_JCK_DET_L:
  882. return wm8350_clear_bits(wm8350,
  883. WM8350_COMPARATOR_INT_STATUS_MASK,
  884. WM8350_IM_CODEC_JCK_DET_L_EINT);
  885. case WM8350_IRQ_CODEC_JCK_DET_R:
  886. return wm8350_clear_bits(wm8350,
  887. WM8350_COMPARATOR_INT_STATUS_MASK,
  888. WM8350_IM_CODEC_JCK_DET_R_EINT);
  889. case WM8350_IRQ_CODEC_MICSCD:
  890. return wm8350_clear_bits(wm8350,
  891. WM8350_COMPARATOR_INT_STATUS_MASK,
  892. WM8350_IM_CODEC_MICSCD_EINT);
  893. case WM8350_IRQ_CODEC_MICD:
  894. return wm8350_clear_bits(wm8350,
  895. WM8350_COMPARATOR_INT_STATUS_MASK,
  896. WM8350_IM_CODEC_MICD_EINT);
  897. case WM8350_IRQ_WKUP_OFF_STATE:
  898. return wm8350_clear_bits(wm8350,
  899. WM8350_COMPARATOR_INT_STATUS_MASK,
  900. WM8350_IM_WKUP_OFF_STATE_EINT);
  901. case WM8350_IRQ_WKUP_HIB_STATE:
  902. return wm8350_clear_bits(wm8350,
  903. WM8350_COMPARATOR_INT_STATUS_MASK,
  904. WM8350_IM_WKUP_HIB_STATE_EINT);
  905. case WM8350_IRQ_WKUP_CONV_FAULT:
  906. return wm8350_clear_bits(wm8350,
  907. WM8350_COMPARATOR_INT_STATUS_MASK,
  908. WM8350_IM_WKUP_CONV_FAULT_EINT);
  909. case WM8350_IRQ_WKUP_WDOG_RST:
  910. return wm8350_clear_bits(wm8350,
  911. WM8350_COMPARATOR_INT_STATUS_MASK,
  912. WM8350_IM_WKUP_OFF_STATE_EINT);
  913. case WM8350_IRQ_WKUP_GP_PWR_ON:
  914. return wm8350_clear_bits(wm8350,
  915. WM8350_COMPARATOR_INT_STATUS_MASK,
  916. WM8350_IM_WKUP_GP_PWR_ON_EINT);
  917. case WM8350_IRQ_WKUP_ONKEY:
  918. return wm8350_clear_bits(wm8350,
  919. WM8350_COMPARATOR_INT_STATUS_MASK,
  920. WM8350_IM_WKUP_ONKEY_EINT);
  921. case WM8350_IRQ_WKUP_GP_WAKEUP:
  922. return wm8350_clear_bits(wm8350,
  923. WM8350_COMPARATOR_INT_STATUS_MASK,
  924. WM8350_IM_WKUP_GP_WAKEUP_EINT);
  925. case WM8350_IRQ_GPIO(0):
  926. return wm8350_clear_bits(wm8350,
  927. WM8350_GPIO_INT_STATUS_MASK,
  928. WM8350_IM_GP0_EINT);
  929. case WM8350_IRQ_GPIO(1):
  930. return wm8350_clear_bits(wm8350,
  931. WM8350_GPIO_INT_STATUS_MASK,
  932. WM8350_IM_GP1_EINT);
  933. case WM8350_IRQ_GPIO(2):
  934. return wm8350_clear_bits(wm8350,
  935. WM8350_GPIO_INT_STATUS_MASK,
  936. WM8350_IM_GP2_EINT);
  937. case WM8350_IRQ_GPIO(3):
  938. return wm8350_clear_bits(wm8350,
  939. WM8350_GPIO_INT_STATUS_MASK,
  940. WM8350_IM_GP3_EINT);
  941. case WM8350_IRQ_GPIO(4):
  942. return wm8350_clear_bits(wm8350,
  943. WM8350_GPIO_INT_STATUS_MASK,
  944. WM8350_IM_GP4_EINT);
  945. case WM8350_IRQ_GPIO(5):
  946. return wm8350_clear_bits(wm8350,
  947. WM8350_GPIO_INT_STATUS_MASK,
  948. WM8350_IM_GP5_EINT);
  949. case WM8350_IRQ_GPIO(6):
  950. return wm8350_clear_bits(wm8350,
  951. WM8350_GPIO_INT_STATUS_MASK,
  952. WM8350_IM_GP6_EINT);
  953. case WM8350_IRQ_GPIO(7):
  954. return wm8350_clear_bits(wm8350,
  955. WM8350_GPIO_INT_STATUS_MASK,
  956. WM8350_IM_GP7_EINT);
  957. case WM8350_IRQ_GPIO(8):
  958. return wm8350_clear_bits(wm8350,
  959. WM8350_GPIO_INT_STATUS_MASK,
  960. WM8350_IM_GP8_EINT);
  961. case WM8350_IRQ_GPIO(9):
  962. return wm8350_clear_bits(wm8350,
  963. WM8350_GPIO_INT_STATUS_MASK,
  964. WM8350_IM_GP9_EINT);
  965. case WM8350_IRQ_GPIO(10):
  966. return wm8350_clear_bits(wm8350,
  967. WM8350_GPIO_INT_STATUS_MASK,
  968. WM8350_IM_GP10_EINT);
  969. case WM8350_IRQ_GPIO(11):
  970. return wm8350_clear_bits(wm8350,
  971. WM8350_GPIO_INT_STATUS_MASK,
  972. WM8350_IM_GP11_EINT);
  973. case WM8350_IRQ_GPIO(12):
  974. return wm8350_clear_bits(wm8350,
  975. WM8350_GPIO_INT_STATUS_MASK,
  976. WM8350_IM_GP12_EINT);
  977. default:
  978. dev_warn(wm8350->dev, "Attempting to unmask unknown IRQ %d\n",
  979. irq);
  980. return -EINVAL;
  981. }
  982. return 0;
  983. }
  984. EXPORT_SYMBOL_GPL(wm8350_unmask_irq);
  985. int wm8350_read_auxadc(struct wm8350 *wm8350, int channel, int scale, int vref)
  986. {
  987. u16 reg, result = 0;
  988. int tries = 5;
  989. if (channel < WM8350_AUXADC_AUX1 || channel > WM8350_AUXADC_TEMP)
  990. return -EINVAL;
  991. if (channel >= WM8350_AUXADC_USB && channel <= WM8350_AUXADC_TEMP
  992. && (scale != 0 || vref != 0))
  993. return -EINVAL;
  994. mutex_lock(&wm8350->auxadc_mutex);
  995. /* Turn on the ADC */
  996. reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5);
  997. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5, reg | WM8350_AUXADC_ENA);
  998. if (scale || vref) {
  999. reg = scale << 13;
  1000. reg |= vref << 12;
  1001. wm8350_reg_write(wm8350, WM8350_AUX1_READBACK + channel, reg);
  1002. }
  1003. reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1);
  1004. reg |= 1 << channel | WM8350_AUXADC_POLL;
  1005. wm8350_reg_write(wm8350, WM8350_DIGITISER_CONTROL_1, reg);
  1006. do {
  1007. schedule_timeout_interruptible(1);
  1008. reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1);
  1009. } while ((reg & WM8350_AUXADC_POLL) && --tries);
  1010. if (!tries)
  1011. dev_err(wm8350->dev, "adc chn %d read timeout\n", channel);
  1012. else
  1013. result = wm8350_reg_read(wm8350,
  1014. WM8350_AUX1_READBACK + channel);
  1015. /* Turn off the ADC */
  1016. reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5);
  1017. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5,
  1018. reg & ~WM8350_AUXADC_ENA);
  1019. mutex_unlock(&wm8350->auxadc_mutex);
  1020. return result & WM8350_AUXADC_DATA1_MASK;
  1021. }
  1022. EXPORT_SYMBOL_GPL(wm8350_read_auxadc);
  1023. /*
  1024. * Cache is always host endian.
  1025. */
  1026. static int wm8350_create_cache(struct wm8350 *wm8350, int type, int mode)
  1027. {
  1028. int i, ret = 0;
  1029. u16 value;
  1030. const u16 *reg_map;
  1031. switch (type) {
  1032. case 0:
  1033. switch (mode) {
  1034. #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0
  1035. case 0:
  1036. reg_map = wm8350_mode0_defaults;
  1037. break;
  1038. #endif
  1039. #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1
  1040. case 1:
  1041. reg_map = wm8350_mode1_defaults;
  1042. break;
  1043. #endif
  1044. #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2
  1045. case 2:
  1046. reg_map = wm8350_mode2_defaults;
  1047. break;
  1048. #endif
  1049. #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3
  1050. case 3:
  1051. reg_map = wm8350_mode3_defaults;
  1052. break;
  1053. #endif
  1054. default:
  1055. dev_err(wm8350->dev,
  1056. "WM8350 configuration mode %d not supported\n",
  1057. mode);
  1058. return -EINVAL;
  1059. }
  1060. break;
  1061. case 1:
  1062. switch (mode) {
  1063. #ifdef CONFIG_MFD_WM8351_CONFIG_MODE_0
  1064. case 0:
  1065. reg_map = wm8351_mode0_defaults;
  1066. break;
  1067. #endif
  1068. #ifdef CONFIG_MFD_WM8351_CONFIG_MODE_1
  1069. case 1:
  1070. reg_map = wm8351_mode1_defaults;
  1071. break;
  1072. #endif
  1073. #ifdef CONFIG_MFD_WM8351_CONFIG_MODE_2
  1074. case 2:
  1075. reg_map = wm8351_mode2_defaults;
  1076. break;
  1077. #endif
  1078. #ifdef CONFIG_MFD_WM8351_CONFIG_MODE_3
  1079. case 3:
  1080. reg_map = wm8351_mode3_defaults;
  1081. break;
  1082. #endif
  1083. default:
  1084. dev_err(wm8350->dev,
  1085. "WM8351 configuration mode %d not supported\n",
  1086. mode);
  1087. return -EINVAL;
  1088. }
  1089. break;
  1090. case 2:
  1091. switch (mode) {
  1092. #ifdef CONFIG_MFD_WM8352_CONFIG_MODE_0
  1093. case 0:
  1094. reg_map = wm8352_mode0_defaults;
  1095. break;
  1096. #endif
  1097. #ifdef CONFIG_MFD_WM8352_CONFIG_MODE_1
  1098. case 1:
  1099. reg_map = wm8352_mode1_defaults;
  1100. break;
  1101. #endif
  1102. #ifdef CONFIG_MFD_WM8352_CONFIG_MODE_2
  1103. case 2:
  1104. reg_map = wm8352_mode2_defaults;
  1105. break;
  1106. #endif
  1107. #ifdef CONFIG_MFD_WM8352_CONFIG_MODE_3
  1108. case 3:
  1109. reg_map = wm8352_mode3_defaults;
  1110. break;
  1111. #endif
  1112. default:
  1113. dev_err(wm8350->dev,
  1114. "WM8352 configuration mode %d not supported\n",
  1115. mode);
  1116. return -EINVAL;
  1117. }
  1118. break;
  1119. default:
  1120. dev_err(wm8350->dev,
  1121. "WM835x configuration mode %d not supported\n",
  1122. mode);
  1123. return -EINVAL;
  1124. }
  1125. wm8350->reg_cache =
  1126. kmalloc(sizeof(u16) * (WM8350_MAX_REGISTER + 1), GFP_KERNEL);
  1127. if (wm8350->reg_cache == NULL)
  1128. return -ENOMEM;
  1129. /* Read the initial cache state back from the device - this is
  1130. * a PMIC so the device many not be in a virgin state and we
  1131. * can't rely on the silicon values.
  1132. */
  1133. ret = wm8350->read_dev(wm8350, 0,
  1134. sizeof(u16) * (WM8350_MAX_REGISTER + 1),
  1135. wm8350->reg_cache);
  1136. if (ret < 0) {
  1137. dev_err(wm8350->dev,
  1138. "failed to read initial cache values\n");
  1139. goto out;
  1140. }
  1141. /* Mask out uncacheable/unreadable bits and the audio. */
  1142. for (i = 0; i < WM8350_MAX_REGISTER; i++) {
  1143. if (wm8350_reg_io_map[i].readable &&
  1144. (i < WM8350_CLOCK_CONTROL_1 || i > WM8350_AIF_TEST)) {
  1145. value = be16_to_cpu(wm8350->reg_cache[i]);
  1146. value &= wm8350_reg_io_map[i].readable;
  1147. wm8350->reg_cache[i] = value;
  1148. } else
  1149. wm8350->reg_cache[i] = reg_map[i];
  1150. }
  1151. out:
  1152. return ret;
  1153. }
  1154. /*
  1155. * Register a client device. This is non-fatal since there is no need to
  1156. * fail the entire device init due to a single platform device failing.
  1157. */
  1158. static void wm8350_client_dev_register(struct wm8350 *wm8350,
  1159. const char *name,
  1160. struct platform_device **pdev)
  1161. {
  1162. int ret;
  1163. *pdev = platform_device_alloc(name, -1);
  1164. if (pdev == NULL) {
  1165. dev_err(wm8350->dev, "Failed to allocate %s\n", name);
  1166. return;
  1167. }
  1168. (*pdev)->dev.parent = wm8350->dev;
  1169. platform_set_drvdata(*pdev, wm8350);
  1170. ret = platform_device_add(*pdev);
  1171. if (ret != 0) {
  1172. dev_err(wm8350->dev, "Failed to register %s: %d\n", name, ret);
  1173. platform_device_put(*pdev);
  1174. *pdev = NULL;
  1175. }
  1176. }
  1177. int wm8350_device_init(struct wm8350 *wm8350, int irq,
  1178. struct wm8350_platform_data *pdata)
  1179. {
  1180. int ret;
  1181. u16 id1, id2, mask_rev;
  1182. u16 cust_id, mode, chip_rev;
  1183. /* get WM8350 revision and config mode */
  1184. ret = wm8350->read_dev(wm8350, WM8350_RESET_ID, sizeof(id1), &id1);
  1185. if (ret != 0) {
  1186. dev_err(wm8350->dev, "Failed to read ID: %d\n", ret);
  1187. goto err;
  1188. }
  1189. ret = wm8350->read_dev(wm8350, WM8350_ID, sizeof(id2), &id2);
  1190. if (ret != 0) {
  1191. dev_err(wm8350->dev, "Failed to read ID: %d\n", ret);
  1192. goto err;
  1193. }
  1194. ret = wm8350->read_dev(wm8350, WM8350_REVISION, sizeof(mask_rev),
  1195. &mask_rev);
  1196. if (ret != 0) {
  1197. dev_err(wm8350->dev, "Failed to read revision: %d\n", ret);
  1198. goto err;
  1199. }
  1200. id1 = be16_to_cpu(id1);
  1201. id2 = be16_to_cpu(id2);
  1202. mask_rev = be16_to_cpu(mask_rev);
  1203. if (id1 != 0x6143) {
  1204. dev_err(wm8350->dev,
  1205. "Device with ID %x is not a WM8350\n", id1);
  1206. ret = -ENODEV;
  1207. goto err;
  1208. }
  1209. mode = id2 & WM8350_CONF_STS_MASK >> 10;
  1210. cust_id = id2 & WM8350_CUST_ID_MASK;
  1211. chip_rev = (id2 & WM8350_CHIP_REV_MASK) >> 12;
  1212. dev_info(wm8350->dev,
  1213. "CONF_STS %d, CUST_ID %d, MASK_REV %d, CHIP_REV %d\n",
  1214. mode, cust_id, mask_rev, chip_rev);
  1215. if (cust_id != 0) {
  1216. dev_err(wm8350->dev, "Unsupported CUST_ID\n");
  1217. ret = -ENODEV;
  1218. goto err;
  1219. }
  1220. switch (mask_rev) {
  1221. case 0:
  1222. wm8350->pmic.max_dcdc = WM8350_DCDC_6;
  1223. wm8350->pmic.max_isink = WM8350_ISINK_B;
  1224. switch (chip_rev) {
  1225. case WM8350_REV_E:
  1226. dev_info(wm8350->dev, "WM8350 Rev E\n");
  1227. break;
  1228. case WM8350_REV_F:
  1229. dev_info(wm8350->dev, "WM8350 Rev F\n");
  1230. break;
  1231. case WM8350_REV_G:
  1232. dev_info(wm8350->dev, "WM8350 Rev G\n");
  1233. wm8350->power.rev_g_coeff = 1;
  1234. break;
  1235. case WM8350_REV_H:
  1236. dev_info(wm8350->dev, "WM8350 Rev H\n");
  1237. wm8350->power.rev_g_coeff = 1;
  1238. break;
  1239. default:
  1240. /* For safety we refuse to run on unknown hardware */
  1241. dev_err(wm8350->dev, "Unknown WM8350 CHIP_REV\n");
  1242. ret = -ENODEV;
  1243. goto err;
  1244. }
  1245. break;
  1246. case 1:
  1247. wm8350->pmic.max_dcdc = WM8350_DCDC_4;
  1248. wm8350->pmic.max_isink = WM8350_ISINK_A;
  1249. switch (chip_rev) {
  1250. case 0:
  1251. dev_info(wm8350->dev, "WM8351 Rev A\n");
  1252. wm8350->power.rev_g_coeff = 1;
  1253. break;
  1254. case 1:
  1255. dev_info(wm8350->dev, "WM8351 Rev B\n");
  1256. wm8350->power.rev_g_coeff = 1;
  1257. break;
  1258. default:
  1259. dev_err(wm8350->dev, "Unknown WM8351 CHIP_REV\n");
  1260. ret = -ENODEV;
  1261. goto err;
  1262. }
  1263. break;
  1264. case 2:
  1265. wm8350->pmic.max_dcdc = WM8350_DCDC_6;
  1266. wm8350->pmic.max_isink = WM8350_ISINK_B;
  1267. switch (chip_rev) {
  1268. case 0:
  1269. dev_info(wm8350->dev, "WM8352 Rev A\n");
  1270. wm8350->power.rev_g_coeff = 1;
  1271. break;
  1272. default:
  1273. dev_err(wm8350->dev, "Unknown WM8352 CHIP_REV\n");
  1274. ret = -ENODEV;
  1275. goto err;
  1276. }
  1277. break;
  1278. default:
  1279. dev_err(wm8350->dev, "Unknown MASK_REV\n");
  1280. ret = -ENODEV;
  1281. goto err;
  1282. }
  1283. ret = wm8350_create_cache(wm8350, mask_rev, mode);
  1284. if (ret < 0) {
  1285. dev_err(wm8350->dev, "Failed to create register cache\n");
  1286. return ret;
  1287. }
  1288. wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0xFFFF);
  1289. wm8350_reg_write(wm8350, WM8350_INT_STATUS_1_MASK, 0xFFFF);
  1290. wm8350_reg_write(wm8350, WM8350_INT_STATUS_2_MASK, 0xFFFF);
  1291. wm8350_reg_write(wm8350, WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 0xFFFF);
  1292. wm8350_reg_write(wm8350, WM8350_GPIO_INT_STATUS_MASK, 0xFFFF);
  1293. wm8350_reg_write(wm8350, WM8350_COMPARATOR_INT_STATUS_MASK, 0xFFFF);
  1294. mutex_init(&wm8350->auxadc_mutex);
  1295. mutex_init(&wm8350->irq_mutex);
  1296. if (irq) {
  1297. int flags = IRQF_ONESHOT;
  1298. if (pdata && pdata->irq_high) {
  1299. flags |= IRQF_TRIGGER_HIGH;
  1300. wm8350_set_bits(wm8350, WM8350_SYSTEM_CONTROL_1,
  1301. WM8350_IRQ_POL);
  1302. } else {
  1303. flags |= IRQF_TRIGGER_LOW;
  1304. wm8350_clear_bits(wm8350, WM8350_SYSTEM_CONTROL_1,
  1305. WM8350_IRQ_POL);
  1306. }
  1307. ret = request_threaded_irq(irq, NULL, wm8350_irq, flags,
  1308. "wm8350", wm8350);
  1309. if (ret != 0) {
  1310. dev_err(wm8350->dev, "Failed to request IRQ: %d\n",
  1311. ret);
  1312. goto err;
  1313. }
  1314. } else {
  1315. dev_err(wm8350->dev, "No IRQ configured\n");
  1316. goto err;
  1317. }
  1318. wm8350->chip_irq = irq;
  1319. if (pdata && pdata->init) {
  1320. ret = pdata->init(wm8350);
  1321. if (ret != 0) {
  1322. dev_err(wm8350->dev, "Platform init() failed: %d\n",
  1323. ret);
  1324. goto err;
  1325. }
  1326. }
  1327. wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x0);
  1328. wm8350_client_dev_register(wm8350, "wm8350-codec",
  1329. &(wm8350->codec.pdev));
  1330. wm8350_client_dev_register(wm8350, "wm8350-gpio",
  1331. &(wm8350->gpio.pdev));
  1332. wm8350_client_dev_register(wm8350, "wm8350-hwmon",
  1333. &(wm8350->hwmon.pdev));
  1334. wm8350_client_dev_register(wm8350, "wm8350-power",
  1335. &(wm8350->power.pdev));
  1336. wm8350_client_dev_register(wm8350, "wm8350-rtc", &(wm8350->rtc.pdev));
  1337. wm8350_client_dev_register(wm8350, "wm8350-wdt", &(wm8350->wdt.pdev));
  1338. return 0;
  1339. err:
  1340. kfree(wm8350->reg_cache);
  1341. return ret;
  1342. }
  1343. EXPORT_SYMBOL_GPL(wm8350_device_init);
  1344. void wm8350_device_exit(struct wm8350 *wm8350)
  1345. {
  1346. int i;
  1347. for (i = 0; i < ARRAY_SIZE(wm8350->pmic.led); i++)
  1348. platform_device_unregister(wm8350->pmic.led[i].pdev);
  1349. for (i = 0; i < ARRAY_SIZE(wm8350->pmic.pdev); i++)
  1350. platform_device_unregister(wm8350->pmic.pdev[i]);
  1351. platform_device_unregister(wm8350->wdt.pdev);
  1352. platform_device_unregister(wm8350->rtc.pdev);
  1353. platform_device_unregister(wm8350->power.pdev);
  1354. platform_device_unregister(wm8350->hwmon.pdev);
  1355. platform_device_unregister(wm8350->gpio.pdev);
  1356. platform_device_unregister(wm8350->codec.pdev);
  1357. free_irq(wm8350->chip_irq, wm8350);
  1358. kfree(wm8350->reg_cache);
  1359. }
  1360. EXPORT_SYMBOL_GPL(wm8350_device_exit);
  1361. MODULE_DESCRIPTION("WM8350 AudioPlus PMIC core driver");
  1362. MODULE_LICENSE("GPL");