radeon_ttm.c 19 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30. * Dave Airlie
  31. */
  32. #include <ttm/ttm_bo_api.h>
  33. #include <ttm/ttm_bo_driver.h>
  34. #include <ttm/ttm_placement.h>
  35. #include <ttm/ttm_module.h>
  36. #include <drm/drmP.h>
  37. #include <drm/radeon_drm.h>
  38. #include <linux/seq_file.h>
  39. #include "radeon_reg.h"
  40. #include "radeon.h"
  41. #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  42. static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
  43. static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
  44. {
  45. struct radeon_mman *mman;
  46. struct radeon_device *rdev;
  47. mman = container_of(bdev, struct radeon_mman, bdev);
  48. rdev = container_of(mman, struct radeon_device, mman);
  49. return rdev;
  50. }
  51. /*
  52. * Global memory.
  53. */
  54. static int radeon_ttm_mem_global_init(struct ttm_global_reference *ref)
  55. {
  56. return ttm_mem_global_init(ref->object);
  57. }
  58. static void radeon_ttm_mem_global_release(struct ttm_global_reference *ref)
  59. {
  60. ttm_mem_global_release(ref->object);
  61. }
  62. static int radeon_ttm_global_init(struct radeon_device *rdev)
  63. {
  64. struct ttm_global_reference *global_ref;
  65. int r;
  66. rdev->mman.mem_global_referenced = false;
  67. global_ref = &rdev->mman.mem_global_ref;
  68. global_ref->global_type = TTM_GLOBAL_TTM_MEM;
  69. global_ref->size = sizeof(struct ttm_mem_global);
  70. global_ref->init = &radeon_ttm_mem_global_init;
  71. global_ref->release = &radeon_ttm_mem_global_release;
  72. r = ttm_global_item_ref(global_ref);
  73. if (r != 0) {
  74. DRM_ERROR("Failed setting up TTM memory accounting "
  75. "subsystem.\n");
  76. return r;
  77. }
  78. rdev->mman.bo_global_ref.mem_glob =
  79. rdev->mman.mem_global_ref.object;
  80. global_ref = &rdev->mman.bo_global_ref.ref;
  81. global_ref->global_type = TTM_GLOBAL_TTM_BO;
  82. global_ref->size = sizeof(struct ttm_bo_global);
  83. global_ref->init = &ttm_bo_global_init;
  84. global_ref->release = &ttm_bo_global_release;
  85. r = ttm_global_item_ref(global_ref);
  86. if (r != 0) {
  87. DRM_ERROR("Failed setting up TTM BO subsystem.\n");
  88. ttm_global_item_unref(&rdev->mman.mem_global_ref);
  89. return r;
  90. }
  91. rdev->mman.mem_global_referenced = true;
  92. return 0;
  93. }
  94. static void radeon_ttm_global_fini(struct radeon_device *rdev)
  95. {
  96. if (rdev->mman.mem_global_referenced) {
  97. ttm_global_item_unref(&rdev->mman.bo_global_ref.ref);
  98. ttm_global_item_unref(&rdev->mman.mem_global_ref);
  99. rdev->mman.mem_global_referenced = false;
  100. }
  101. }
  102. struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev);
  103. static struct ttm_backend*
  104. radeon_create_ttm_backend_entry(struct ttm_bo_device *bdev)
  105. {
  106. struct radeon_device *rdev;
  107. rdev = radeon_get_rdev(bdev);
  108. #if __OS_HAS_AGP
  109. if (rdev->flags & RADEON_IS_AGP) {
  110. return ttm_agp_backend_init(bdev, rdev->ddev->agp->bridge);
  111. } else
  112. #endif
  113. {
  114. return radeon_ttm_backend_create(rdev);
  115. }
  116. }
  117. static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
  118. {
  119. return 0;
  120. }
  121. static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  122. struct ttm_mem_type_manager *man)
  123. {
  124. struct radeon_device *rdev;
  125. rdev = radeon_get_rdev(bdev);
  126. switch (type) {
  127. case TTM_PL_SYSTEM:
  128. /* System memory */
  129. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  130. man->available_caching = TTM_PL_MASK_CACHING;
  131. man->default_caching = TTM_PL_FLAG_CACHED;
  132. break;
  133. case TTM_PL_TT:
  134. man->gpu_offset = 0;
  135. man->available_caching = TTM_PL_MASK_CACHING;
  136. man->default_caching = TTM_PL_FLAG_CACHED;
  137. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
  138. #if __OS_HAS_AGP
  139. if (rdev->flags & RADEON_IS_AGP) {
  140. if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) {
  141. DRM_ERROR("AGP is not enabled for memory type %u\n",
  142. (unsigned)type);
  143. return -EINVAL;
  144. }
  145. man->io_offset = rdev->mc.agp_base;
  146. man->io_size = rdev->mc.gtt_size;
  147. man->io_addr = NULL;
  148. if (!rdev->ddev->agp->cant_use_aperture)
  149. man->flags = TTM_MEMTYPE_FLAG_NEEDS_IOREMAP |
  150. TTM_MEMTYPE_FLAG_MAPPABLE;
  151. man->available_caching = TTM_PL_FLAG_UNCACHED |
  152. TTM_PL_FLAG_WC;
  153. man->default_caching = TTM_PL_FLAG_WC;
  154. } else
  155. #endif
  156. {
  157. man->io_offset = 0;
  158. man->io_size = 0;
  159. man->io_addr = NULL;
  160. }
  161. break;
  162. case TTM_PL_VRAM:
  163. /* "On-card" video ram */
  164. man->gpu_offset = 0;
  165. man->flags = TTM_MEMTYPE_FLAG_FIXED |
  166. TTM_MEMTYPE_FLAG_NEEDS_IOREMAP |
  167. TTM_MEMTYPE_FLAG_MAPPABLE;
  168. man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
  169. man->default_caching = TTM_PL_FLAG_WC;
  170. man->io_addr = NULL;
  171. man->io_offset = rdev->mc.aper_base;
  172. man->io_size = rdev->mc.aper_size;
  173. break;
  174. default:
  175. DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
  176. return -EINVAL;
  177. }
  178. return 0;
  179. }
  180. static uint32_t radeon_evict_flags(struct ttm_buffer_object *bo)
  181. {
  182. uint32_t cur_placement = bo->mem.placement & ~TTM_PL_MASK_MEMTYPE;
  183. switch (bo->mem.mem_type) {
  184. default:
  185. return (cur_placement & ~TTM_PL_MASK_CACHING) |
  186. TTM_PL_FLAG_SYSTEM |
  187. TTM_PL_FLAG_CACHED;
  188. }
  189. }
  190. static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
  191. {
  192. return 0;
  193. }
  194. static void radeon_move_null(struct ttm_buffer_object *bo,
  195. struct ttm_mem_reg *new_mem)
  196. {
  197. struct ttm_mem_reg *old_mem = &bo->mem;
  198. BUG_ON(old_mem->mm_node != NULL);
  199. *old_mem = *new_mem;
  200. new_mem->mm_node = NULL;
  201. }
  202. static int radeon_move_blit(struct ttm_buffer_object *bo,
  203. bool evict, int no_wait,
  204. struct ttm_mem_reg *new_mem,
  205. struct ttm_mem_reg *old_mem)
  206. {
  207. struct radeon_device *rdev;
  208. uint64_t old_start, new_start;
  209. struct radeon_fence *fence;
  210. int r;
  211. rdev = radeon_get_rdev(bo->bdev);
  212. r = radeon_fence_create(rdev, &fence);
  213. if (unlikely(r)) {
  214. return r;
  215. }
  216. old_start = old_mem->mm_node->start << PAGE_SHIFT;
  217. new_start = new_mem->mm_node->start << PAGE_SHIFT;
  218. switch (old_mem->mem_type) {
  219. case TTM_PL_VRAM:
  220. old_start += rdev->mc.vram_location;
  221. break;
  222. case TTM_PL_TT:
  223. old_start += rdev->mc.gtt_location;
  224. break;
  225. default:
  226. DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
  227. return -EINVAL;
  228. }
  229. switch (new_mem->mem_type) {
  230. case TTM_PL_VRAM:
  231. new_start += rdev->mc.vram_location;
  232. break;
  233. case TTM_PL_TT:
  234. new_start += rdev->mc.gtt_location;
  235. break;
  236. default:
  237. DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
  238. return -EINVAL;
  239. }
  240. if (!rdev->cp.ready) {
  241. DRM_ERROR("Trying to move memory with CP turned off.\n");
  242. return -EINVAL;
  243. }
  244. r = radeon_copy(rdev, old_start, new_start, new_mem->num_pages, fence);
  245. /* FIXME: handle copy error */
  246. r = ttm_bo_move_accel_cleanup(bo, (void *)fence, NULL,
  247. evict, no_wait, new_mem);
  248. radeon_fence_unref(&fence);
  249. return r;
  250. }
  251. static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
  252. bool evict, bool interruptible, bool no_wait,
  253. struct ttm_mem_reg *new_mem)
  254. {
  255. struct radeon_device *rdev;
  256. struct ttm_mem_reg *old_mem = &bo->mem;
  257. struct ttm_mem_reg tmp_mem;
  258. uint32_t proposed_placement;
  259. int r;
  260. rdev = radeon_get_rdev(bo->bdev);
  261. tmp_mem = *new_mem;
  262. tmp_mem.mm_node = NULL;
  263. proposed_placement = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
  264. r = ttm_bo_mem_space(bo, proposed_placement, &tmp_mem,
  265. interruptible, no_wait);
  266. if (unlikely(r)) {
  267. return r;
  268. }
  269. r = ttm_tt_bind(bo->ttm, &tmp_mem);
  270. if (unlikely(r)) {
  271. goto out_cleanup;
  272. }
  273. r = radeon_move_blit(bo, true, no_wait, &tmp_mem, old_mem);
  274. if (unlikely(r)) {
  275. goto out_cleanup;
  276. }
  277. r = ttm_bo_move_ttm(bo, true, no_wait, new_mem);
  278. out_cleanup:
  279. if (tmp_mem.mm_node) {
  280. struct ttm_bo_global *glob = rdev->mman.bdev.glob;
  281. spin_lock(&glob->lru_lock);
  282. drm_mm_put_block(tmp_mem.mm_node);
  283. spin_unlock(&glob->lru_lock);
  284. return r;
  285. }
  286. return r;
  287. }
  288. static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
  289. bool evict, bool interruptible, bool no_wait,
  290. struct ttm_mem_reg *new_mem)
  291. {
  292. struct radeon_device *rdev;
  293. struct ttm_mem_reg *old_mem = &bo->mem;
  294. struct ttm_mem_reg tmp_mem;
  295. uint32_t proposed_flags;
  296. int r;
  297. rdev = radeon_get_rdev(bo->bdev);
  298. tmp_mem = *new_mem;
  299. tmp_mem.mm_node = NULL;
  300. proposed_flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
  301. r = ttm_bo_mem_space(bo, proposed_flags, &tmp_mem,
  302. interruptible, no_wait);
  303. if (unlikely(r)) {
  304. return r;
  305. }
  306. r = ttm_bo_move_ttm(bo, true, no_wait, &tmp_mem);
  307. if (unlikely(r)) {
  308. goto out_cleanup;
  309. }
  310. r = radeon_move_blit(bo, true, no_wait, new_mem, old_mem);
  311. if (unlikely(r)) {
  312. goto out_cleanup;
  313. }
  314. out_cleanup:
  315. if (tmp_mem.mm_node) {
  316. struct ttm_bo_global *glob = rdev->mman.bdev.glob;
  317. spin_lock(&glob->lru_lock);
  318. drm_mm_put_block(tmp_mem.mm_node);
  319. spin_unlock(&glob->lru_lock);
  320. return r;
  321. }
  322. return r;
  323. }
  324. static int radeon_bo_move(struct ttm_buffer_object *bo,
  325. bool evict, bool interruptible, bool no_wait,
  326. struct ttm_mem_reg *new_mem)
  327. {
  328. struct radeon_device *rdev;
  329. struct ttm_mem_reg *old_mem = &bo->mem;
  330. int r;
  331. rdev = radeon_get_rdev(bo->bdev);
  332. if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
  333. radeon_move_null(bo, new_mem);
  334. return 0;
  335. }
  336. if ((old_mem->mem_type == TTM_PL_TT &&
  337. new_mem->mem_type == TTM_PL_SYSTEM) ||
  338. (old_mem->mem_type == TTM_PL_SYSTEM &&
  339. new_mem->mem_type == TTM_PL_TT)) {
  340. /* bind is enought */
  341. radeon_move_null(bo, new_mem);
  342. return 0;
  343. }
  344. if (!rdev->cp.ready || rdev->asic->copy == NULL) {
  345. /* use memcpy */
  346. goto memcpy;
  347. }
  348. if (old_mem->mem_type == TTM_PL_VRAM &&
  349. new_mem->mem_type == TTM_PL_SYSTEM) {
  350. r = radeon_move_vram_ram(bo, evict, interruptible,
  351. no_wait, new_mem);
  352. } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
  353. new_mem->mem_type == TTM_PL_VRAM) {
  354. r = radeon_move_ram_vram(bo, evict, interruptible,
  355. no_wait, new_mem);
  356. } else {
  357. r = radeon_move_blit(bo, evict, no_wait, new_mem, old_mem);
  358. }
  359. if (r) {
  360. memcpy:
  361. r = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
  362. }
  363. return r;
  364. }
  365. const uint32_t radeon_mem_prios[] = {
  366. TTM_PL_VRAM,
  367. TTM_PL_TT,
  368. TTM_PL_SYSTEM,
  369. };
  370. const uint32_t radeon_busy_prios[] = {
  371. TTM_PL_TT,
  372. TTM_PL_VRAM,
  373. TTM_PL_SYSTEM,
  374. };
  375. static int radeon_sync_obj_wait(void *sync_obj, void *sync_arg,
  376. bool lazy, bool interruptible)
  377. {
  378. return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible);
  379. }
  380. static int radeon_sync_obj_flush(void *sync_obj, void *sync_arg)
  381. {
  382. return 0;
  383. }
  384. static void radeon_sync_obj_unref(void **sync_obj)
  385. {
  386. radeon_fence_unref((struct radeon_fence **)sync_obj);
  387. }
  388. static void *radeon_sync_obj_ref(void *sync_obj)
  389. {
  390. return radeon_fence_ref((struct radeon_fence *)sync_obj);
  391. }
  392. static bool radeon_sync_obj_signaled(void *sync_obj, void *sync_arg)
  393. {
  394. return radeon_fence_signaled((struct radeon_fence *)sync_obj);
  395. }
  396. static struct ttm_bo_driver radeon_bo_driver = {
  397. .mem_type_prio = radeon_mem_prios,
  398. .mem_busy_prio = radeon_busy_prios,
  399. .num_mem_type_prio = ARRAY_SIZE(radeon_mem_prios),
  400. .num_mem_busy_prio = ARRAY_SIZE(radeon_busy_prios),
  401. .create_ttm_backend_entry = &radeon_create_ttm_backend_entry,
  402. .invalidate_caches = &radeon_invalidate_caches,
  403. .init_mem_type = &radeon_init_mem_type,
  404. .evict_flags = &radeon_evict_flags,
  405. .move = &radeon_bo_move,
  406. .verify_access = &radeon_verify_access,
  407. .sync_obj_signaled = &radeon_sync_obj_signaled,
  408. .sync_obj_wait = &radeon_sync_obj_wait,
  409. .sync_obj_flush = &radeon_sync_obj_flush,
  410. .sync_obj_unref = &radeon_sync_obj_unref,
  411. .sync_obj_ref = &radeon_sync_obj_ref,
  412. .move_notify = &radeon_bo_move_notify,
  413. .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
  414. };
  415. int radeon_ttm_init(struct radeon_device *rdev)
  416. {
  417. int r;
  418. r = radeon_ttm_global_init(rdev);
  419. if (r) {
  420. return r;
  421. }
  422. /* No others user of address space so set it to 0 */
  423. r = ttm_bo_device_init(&rdev->mman.bdev,
  424. rdev->mman.bo_global_ref.ref.object,
  425. &radeon_bo_driver, DRM_FILE_PAGE_OFFSET,
  426. rdev->need_dma32);
  427. if (r) {
  428. DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
  429. return r;
  430. }
  431. r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, 0,
  432. ((rdev->mc.real_vram_size) >> PAGE_SHIFT));
  433. if (r) {
  434. DRM_ERROR("Failed initializing VRAM heap.\n");
  435. return r;
  436. }
  437. r = radeon_object_create(rdev, NULL, 256 * 1024, true,
  438. RADEON_GEM_DOMAIN_VRAM, false,
  439. &rdev->stollen_vga_memory);
  440. if (r) {
  441. return r;
  442. }
  443. r = radeon_object_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
  444. if (r) {
  445. radeon_object_unref(&rdev->stollen_vga_memory);
  446. return r;
  447. }
  448. DRM_INFO("radeon: %uM of VRAM memory ready\n",
  449. (unsigned)rdev->mc.real_vram_size / (1024 * 1024));
  450. r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 0,
  451. ((rdev->mc.gtt_size) >> PAGE_SHIFT));
  452. if (r) {
  453. DRM_ERROR("Failed initializing GTT heap.\n");
  454. return r;
  455. }
  456. DRM_INFO("radeon: %uM of GTT memory ready.\n",
  457. (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
  458. if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
  459. rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
  460. }
  461. r = radeon_ttm_debugfs_init(rdev);
  462. if (r) {
  463. DRM_ERROR("Failed to init debugfs\n");
  464. return r;
  465. }
  466. return 0;
  467. }
  468. void radeon_ttm_fini(struct radeon_device *rdev)
  469. {
  470. if (rdev->stollen_vga_memory) {
  471. radeon_object_unpin(rdev->stollen_vga_memory);
  472. radeon_object_unref(&rdev->stollen_vga_memory);
  473. }
  474. ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
  475. ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
  476. ttm_bo_device_release(&rdev->mman.bdev);
  477. radeon_gart_fini(rdev);
  478. radeon_ttm_global_fini(rdev);
  479. DRM_INFO("radeon: ttm finalized\n");
  480. }
  481. static struct vm_operations_struct radeon_ttm_vm_ops;
  482. static struct vm_operations_struct *ttm_vm_ops = NULL;
  483. static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
  484. {
  485. struct ttm_buffer_object *bo;
  486. int r;
  487. bo = (struct ttm_buffer_object *)vma->vm_private_data;
  488. if (bo == NULL) {
  489. return VM_FAULT_NOPAGE;
  490. }
  491. r = ttm_vm_ops->fault(vma, vmf);
  492. return r;
  493. }
  494. int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
  495. {
  496. struct drm_file *file_priv;
  497. struct radeon_device *rdev;
  498. int r;
  499. if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
  500. return drm_mmap(filp, vma);
  501. }
  502. file_priv = (struct drm_file *)filp->private_data;
  503. rdev = file_priv->minor->dev->dev_private;
  504. if (rdev == NULL) {
  505. return -EINVAL;
  506. }
  507. r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
  508. if (unlikely(r != 0)) {
  509. return r;
  510. }
  511. if (unlikely(ttm_vm_ops == NULL)) {
  512. ttm_vm_ops = vma->vm_ops;
  513. radeon_ttm_vm_ops = *ttm_vm_ops;
  514. radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
  515. }
  516. vma->vm_ops = &radeon_ttm_vm_ops;
  517. return 0;
  518. }
  519. /*
  520. * TTM backend functions.
  521. */
  522. struct radeon_ttm_backend {
  523. struct ttm_backend backend;
  524. struct radeon_device *rdev;
  525. unsigned long num_pages;
  526. struct page **pages;
  527. struct page *dummy_read_page;
  528. bool populated;
  529. bool bound;
  530. unsigned offset;
  531. };
  532. static int radeon_ttm_backend_populate(struct ttm_backend *backend,
  533. unsigned long num_pages,
  534. struct page **pages,
  535. struct page *dummy_read_page)
  536. {
  537. struct radeon_ttm_backend *gtt;
  538. gtt = container_of(backend, struct radeon_ttm_backend, backend);
  539. gtt->pages = pages;
  540. gtt->num_pages = num_pages;
  541. gtt->dummy_read_page = dummy_read_page;
  542. gtt->populated = true;
  543. return 0;
  544. }
  545. static void radeon_ttm_backend_clear(struct ttm_backend *backend)
  546. {
  547. struct radeon_ttm_backend *gtt;
  548. gtt = container_of(backend, struct radeon_ttm_backend, backend);
  549. gtt->pages = NULL;
  550. gtt->num_pages = 0;
  551. gtt->dummy_read_page = NULL;
  552. gtt->populated = false;
  553. gtt->bound = false;
  554. }
  555. static int radeon_ttm_backend_bind(struct ttm_backend *backend,
  556. struct ttm_mem_reg *bo_mem)
  557. {
  558. struct radeon_ttm_backend *gtt;
  559. int r;
  560. gtt = container_of(backend, struct radeon_ttm_backend, backend);
  561. gtt->offset = bo_mem->mm_node->start << PAGE_SHIFT;
  562. if (!gtt->num_pages) {
  563. WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", gtt->num_pages, bo_mem, backend);
  564. }
  565. r = radeon_gart_bind(gtt->rdev, gtt->offset,
  566. gtt->num_pages, gtt->pages);
  567. if (r) {
  568. DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
  569. gtt->num_pages, gtt->offset);
  570. return r;
  571. }
  572. gtt->bound = true;
  573. return 0;
  574. }
  575. static int radeon_ttm_backend_unbind(struct ttm_backend *backend)
  576. {
  577. struct radeon_ttm_backend *gtt;
  578. gtt = container_of(backend, struct radeon_ttm_backend, backend);
  579. radeon_gart_unbind(gtt->rdev, gtt->offset, gtt->num_pages);
  580. gtt->bound = false;
  581. return 0;
  582. }
  583. static void radeon_ttm_backend_destroy(struct ttm_backend *backend)
  584. {
  585. struct radeon_ttm_backend *gtt;
  586. gtt = container_of(backend, struct radeon_ttm_backend, backend);
  587. if (gtt->bound) {
  588. radeon_ttm_backend_unbind(backend);
  589. }
  590. kfree(gtt);
  591. }
  592. static struct ttm_backend_func radeon_backend_func = {
  593. .populate = &radeon_ttm_backend_populate,
  594. .clear = &radeon_ttm_backend_clear,
  595. .bind = &radeon_ttm_backend_bind,
  596. .unbind = &radeon_ttm_backend_unbind,
  597. .destroy = &radeon_ttm_backend_destroy,
  598. };
  599. struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev)
  600. {
  601. struct radeon_ttm_backend *gtt;
  602. gtt = kzalloc(sizeof(struct radeon_ttm_backend), GFP_KERNEL);
  603. if (gtt == NULL) {
  604. return NULL;
  605. }
  606. gtt->backend.bdev = &rdev->mman.bdev;
  607. gtt->backend.flags = 0;
  608. gtt->backend.func = &radeon_backend_func;
  609. gtt->rdev = rdev;
  610. gtt->pages = NULL;
  611. gtt->num_pages = 0;
  612. gtt->dummy_read_page = NULL;
  613. gtt->populated = false;
  614. gtt->bound = false;
  615. return &gtt->backend;
  616. }
  617. #define RADEON_DEBUGFS_MEM_TYPES 2
  618. static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES];
  619. static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES][32];
  620. #if defined(CONFIG_DEBUG_FS)
  621. static int radeon_mm_dump_table(struct seq_file *m, void *data)
  622. {
  623. struct drm_info_node *node = (struct drm_info_node *)m->private;
  624. struct drm_mm *mm = (struct drm_mm *)node->info_ent->data;
  625. struct drm_device *dev = node->minor->dev;
  626. struct radeon_device *rdev = dev->dev_private;
  627. int ret;
  628. struct ttm_bo_global *glob = rdev->mman.bdev.glob;
  629. spin_lock(&glob->lru_lock);
  630. ret = drm_mm_dump_table(m, mm);
  631. spin_unlock(&glob->lru_lock);
  632. return ret;
  633. }
  634. #endif
  635. static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
  636. {
  637. unsigned i;
  638. #if defined(CONFIG_DEBUG_FS)
  639. for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) {
  640. if (i == 0)
  641. sprintf(radeon_mem_types_names[i], "radeon_vram_mm");
  642. else
  643. sprintf(radeon_mem_types_names[i], "radeon_gtt_mm");
  644. radeon_mem_types_list[i].name = radeon_mem_types_names[i];
  645. radeon_mem_types_list[i].show = &radeon_mm_dump_table;
  646. radeon_mem_types_list[i].driver_features = 0;
  647. if (i == 0)
  648. radeon_mem_types_list[i].data = &rdev->mman.bdev.man[TTM_PL_VRAM].manager;
  649. else
  650. radeon_mem_types_list[i].data = &rdev->mman.bdev.man[TTM_PL_TT].manager;
  651. }
  652. return radeon_debugfs_add_files(rdev, radeon_mem_types_list, RADEON_DEBUGFS_MEM_TYPES);
  653. #endif
  654. return 0;
  655. }