radeon_fence.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426
  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Dave Airlie
  30. */
  31. #include <linux/seq_file.h>
  32. #include <asm/atomic.h>
  33. #include <linux/wait.h>
  34. #include <linux/list.h>
  35. #include <linux/kref.h>
  36. #include "drmP.h"
  37. #include "drm.h"
  38. #include "radeon_reg.h"
  39. #include "radeon.h"
  40. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
  41. {
  42. unsigned long irq_flags;
  43. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  44. if (fence->emited) {
  45. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  46. return 0;
  47. }
  48. fence->seq = atomic_add_return(1, &rdev->fence_drv.seq);
  49. if (!rdev->cp.ready) {
  50. /* FIXME: cp is not running assume everythings is done right
  51. * away
  52. */
  53. WREG32(rdev->fence_drv.scratch_reg, fence->seq);
  54. } else
  55. radeon_fence_ring_emit(rdev, fence);
  56. fence->emited = true;
  57. fence->timeout = jiffies + ((2000 * HZ) / 1000);
  58. list_del(&fence->list);
  59. list_add_tail(&fence->list, &rdev->fence_drv.emited);
  60. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  61. return 0;
  62. }
  63. static bool radeon_fence_poll_locked(struct radeon_device *rdev)
  64. {
  65. struct radeon_fence *fence;
  66. struct list_head *i, *n;
  67. uint32_t seq;
  68. bool wake = false;
  69. if (rdev == NULL) {
  70. return true;
  71. }
  72. if (rdev->shutdown) {
  73. return true;
  74. }
  75. seq = RREG32(rdev->fence_drv.scratch_reg);
  76. rdev->fence_drv.last_seq = seq;
  77. n = NULL;
  78. list_for_each(i, &rdev->fence_drv.emited) {
  79. fence = list_entry(i, struct radeon_fence, list);
  80. if (fence->seq == seq) {
  81. n = i;
  82. break;
  83. }
  84. }
  85. /* all fence previous to this one are considered as signaled */
  86. if (n) {
  87. i = n;
  88. do {
  89. n = i->prev;
  90. list_del(i);
  91. list_add_tail(i, &rdev->fence_drv.signaled);
  92. fence = list_entry(i, struct radeon_fence, list);
  93. fence->signaled = true;
  94. i = n;
  95. } while (i != &rdev->fence_drv.emited);
  96. wake = true;
  97. }
  98. return wake;
  99. }
  100. static void radeon_fence_destroy(struct kref *kref)
  101. {
  102. unsigned long irq_flags;
  103. struct radeon_fence *fence;
  104. fence = container_of(kref, struct radeon_fence, kref);
  105. write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
  106. list_del(&fence->list);
  107. fence->emited = false;
  108. write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
  109. kfree(fence);
  110. }
  111. int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence)
  112. {
  113. unsigned long irq_flags;
  114. *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
  115. if ((*fence) == NULL) {
  116. return -ENOMEM;
  117. }
  118. kref_init(&((*fence)->kref));
  119. (*fence)->rdev = rdev;
  120. (*fence)->emited = false;
  121. (*fence)->signaled = false;
  122. (*fence)->seq = 0;
  123. INIT_LIST_HEAD(&(*fence)->list);
  124. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  125. list_add_tail(&(*fence)->list, &rdev->fence_drv.created);
  126. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  127. return 0;
  128. }
  129. bool radeon_fence_signaled(struct radeon_fence *fence)
  130. {
  131. struct radeon_device *rdev = fence->rdev;
  132. unsigned long irq_flags;
  133. bool signaled = false;
  134. if (rdev->gpu_lockup) {
  135. return true;
  136. }
  137. if (fence == NULL) {
  138. return true;
  139. }
  140. write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
  141. signaled = fence->signaled;
  142. /* if we are shuting down report all fence as signaled */
  143. if (fence->rdev->shutdown) {
  144. signaled = true;
  145. }
  146. if (!fence->emited) {
  147. WARN(1, "Querying an unemited fence : %p !\n", fence);
  148. signaled = true;
  149. }
  150. if (!signaled) {
  151. radeon_fence_poll_locked(fence->rdev);
  152. signaled = fence->signaled;
  153. }
  154. write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
  155. return signaled;
  156. }
  157. int r600_fence_wait(struct radeon_fence *fence, bool intr, bool lazy)
  158. {
  159. struct radeon_device *rdev;
  160. int ret = 0;
  161. rdev = fence->rdev;
  162. __set_current_state(intr ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
  163. while (1) {
  164. if (radeon_fence_signaled(fence))
  165. break;
  166. if (time_after_eq(jiffies, fence->timeout)) {
  167. ret = -EBUSY;
  168. break;
  169. }
  170. if (lazy)
  171. schedule_timeout(1);
  172. if (intr && signal_pending(current)) {
  173. ret = -ERESTARTSYS;
  174. break;
  175. }
  176. }
  177. __set_current_state(TASK_RUNNING);
  178. return ret;
  179. }
  180. int radeon_fence_wait(struct radeon_fence *fence, bool intr)
  181. {
  182. struct radeon_device *rdev;
  183. unsigned long cur_jiffies;
  184. unsigned long timeout;
  185. bool expired = false;
  186. int r;
  187. if (fence == NULL) {
  188. WARN(1, "Querying an invalid fence : %p !\n", fence);
  189. return 0;
  190. }
  191. rdev = fence->rdev;
  192. if (radeon_fence_signaled(fence)) {
  193. return 0;
  194. }
  195. if (rdev->family >= CHIP_R600) {
  196. r = r600_fence_wait(fence, intr, 0);
  197. if (r == -ERESTARTSYS)
  198. return -EBUSY;
  199. return r;
  200. }
  201. retry:
  202. cur_jiffies = jiffies;
  203. timeout = HZ / 100;
  204. if (time_after(fence->timeout, cur_jiffies)) {
  205. timeout = fence->timeout - cur_jiffies;
  206. }
  207. if (intr) {
  208. r = wait_event_interruptible_timeout(rdev->fence_drv.queue,
  209. radeon_fence_signaled(fence), timeout);
  210. if (unlikely(r == -ERESTARTSYS)) {
  211. return -EBUSY;
  212. }
  213. } else {
  214. r = wait_event_timeout(rdev->fence_drv.queue,
  215. radeon_fence_signaled(fence), timeout);
  216. }
  217. if (unlikely(!radeon_fence_signaled(fence))) {
  218. if (unlikely(r == 0)) {
  219. expired = true;
  220. }
  221. if (unlikely(expired)) {
  222. timeout = 1;
  223. if (time_after(cur_jiffies, fence->timeout)) {
  224. timeout = cur_jiffies - fence->timeout;
  225. }
  226. timeout = jiffies_to_msecs(timeout);
  227. if (timeout > 500) {
  228. DRM_ERROR("fence(%p:0x%08X) %lums timeout "
  229. "going to reset GPU\n",
  230. fence, fence->seq, timeout);
  231. radeon_gpu_reset(rdev);
  232. WREG32(rdev->fence_drv.scratch_reg, fence->seq);
  233. }
  234. }
  235. goto retry;
  236. }
  237. if (unlikely(expired)) {
  238. rdev->fence_drv.count_timeout++;
  239. cur_jiffies = jiffies;
  240. timeout = 1;
  241. if (time_after(cur_jiffies, fence->timeout)) {
  242. timeout = cur_jiffies - fence->timeout;
  243. }
  244. timeout = jiffies_to_msecs(timeout);
  245. DRM_ERROR("fence(%p:0x%08X) %lums timeout\n",
  246. fence, fence->seq, timeout);
  247. DRM_ERROR("last signaled fence(0x%08X)\n",
  248. rdev->fence_drv.last_seq);
  249. }
  250. return 0;
  251. }
  252. int radeon_fence_wait_next(struct radeon_device *rdev)
  253. {
  254. unsigned long irq_flags;
  255. struct radeon_fence *fence;
  256. int r;
  257. if (rdev->gpu_lockup) {
  258. return 0;
  259. }
  260. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  261. if (list_empty(&rdev->fence_drv.emited)) {
  262. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  263. return 0;
  264. }
  265. fence = list_entry(rdev->fence_drv.emited.next,
  266. struct radeon_fence, list);
  267. radeon_fence_ref(fence);
  268. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  269. r = radeon_fence_wait(fence, false);
  270. radeon_fence_unref(&fence);
  271. return r;
  272. }
  273. int radeon_fence_wait_last(struct radeon_device *rdev)
  274. {
  275. unsigned long irq_flags;
  276. struct radeon_fence *fence;
  277. int r;
  278. if (rdev->gpu_lockup) {
  279. return 0;
  280. }
  281. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  282. if (list_empty(&rdev->fence_drv.emited)) {
  283. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  284. return 0;
  285. }
  286. fence = list_entry(rdev->fence_drv.emited.prev,
  287. struct radeon_fence, list);
  288. radeon_fence_ref(fence);
  289. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  290. r = radeon_fence_wait(fence, false);
  291. radeon_fence_unref(&fence);
  292. return r;
  293. }
  294. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
  295. {
  296. kref_get(&fence->kref);
  297. return fence;
  298. }
  299. void radeon_fence_unref(struct radeon_fence **fence)
  300. {
  301. struct radeon_fence *tmp = *fence;
  302. *fence = NULL;
  303. if (tmp) {
  304. kref_put(&tmp->kref, &radeon_fence_destroy);
  305. }
  306. }
  307. void radeon_fence_process(struct radeon_device *rdev)
  308. {
  309. unsigned long irq_flags;
  310. bool wake;
  311. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  312. wake = radeon_fence_poll_locked(rdev);
  313. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  314. if (wake) {
  315. wake_up_all(&rdev->fence_drv.queue);
  316. }
  317. }
  318. int radeon_fence_driver_init(struct radeon_device *rdev)
  319. {
  320. unsigned long irq_flags;
  321. int r;
  322. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  323. r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg);
  324. if (r) {
  325. DRM_ERROR("Fence failed to get a scratch register.");
  326. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  327. return r;
  328. }
  329. WREG32(rdev->fence_drv.scratch_reg, 0);
  330. atomic_set(&rdev->fence_drv.seq, 0);
  331. INIT_LIST_HEAD(&rdev->fence_drv.created);
  332. INIT_LIST_HEAD(&rdev->fence_drv.emited);
  333. INIT_LIST_HEAD(&rdev->fence_drv.signaled);
  334. rdev->fence_drv.count_timeout = 0;
  335. init_waitqueue_head(&rdev->fence_drv.queue);
  336. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  337. if (radeon_debugfs_fence_init(rdev)) {
  338. DRM_ERROR("Failed to register debugfs file for fence !\n");
  339. }
  340. return 0;
  341. }
  342. void radeon_fence_driver_fini(struct radeon_device *rdev)
  343. {
  344. unsigned long irq_flags;
  345. wake_up_all(&rdev->fence_drv.queue);
  346. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  347. radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg);
  348. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  349. DRM_INFO("radeon: fence finalized\n");
  350. }
  351. /*
  352. * Fence debugfs
  353. */
  354. #if defined(CONFIG_DEBUG_FS)
  355. static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
  356. {
  357. struct drm_info_node *node = (struct drm_info_node *)m->private;
  358. struct drm_device *dev = node->minor->dev;
  359. struct radeon_device *rdev = dev->dev_private;
  360. struct radeon_fence *fence;
  361. seq_printf(m, "Last signaled fence 0x%08X\n",
  362. RREG32(rdev->fence_drv.scratch_reg));
  363. if (!list_empty(&rdev->fence_drv.emited)) {
  364. fence = list_entry(rdev->fence_drv.emited.prev,
  365. struct radeon_fence, list);
  366. seq_printf(m, "Last emited fence %p with 0x%08X\n",
  367. fence, fence->seq);
  368. }
  369. return 0;
  370. }
  371. static struct drm_info_list radeon_debugfs_fence_list[] = {
  372. {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
  373. };
  374. #endif
  375. int radeon_debugfs_fence_init(struct radeon_device *rdev)
  376. {
  377. #if defined(CONFIG_DEBUG_FS)
  378. return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
  379. #else
  380. return 0;
  381. #endif
  382. }