radeon_device.c 22 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <linux/console.h>
  29. #include <drm/drmP.h>
  30. #include <drm/drm_crtc_helper.h>
  31. #include <drm/radeon_drm.h>
  32. #include <linux/vgaarb.h>
  33. #include "radeon_reg.h"
  34. #include "radeon.h"
  35. #include "radeon_asic.h"
  36. #include "atom.h"
  37. /*
  38. * Clear GPU surface registers.
  39. */
  40. void radeon_surface_init(struct radeon_device *rdev)
  41. {
  42. /* FIXME: check this out */
  43. if (rdev->family < CHIP_R600) {
  44. int i;
  45. for (i = 0; i < 8; i++) {
  46. WREG32(RADEON_SURFACE0_INFO +
  47. i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
  48. 0);
  49. }
  50. /* enable surfaces */
  51. WREG32(RADEON_SURFACE_CNTL, 0);
  52. }
  53. }
  54. /*
  55. * GPU scratch registers helpers function.
  56. */
  57. void radeon_scratch_init(struct radeon_device *rdev)
  58. {
  59. int i;
  60. /* FIXME: check this out */
  61. if (rdev->family < CHIP_R300) {
  62. rdev->scratch.num_reg = 5;
  63. } else {
  64. rdev->scratch.num_reg = 7;
  65. }
  66. for (i = 0; i < rdev->scratch.num_reg; i++) {
  67. rdev->scratch.free[i] = true;
  68. rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
  69. }
  70. }
  71. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
  72. {
  73. int i;
  74. for (i = 0; i < rdev->scratch.num_reg; i++) {
  75. if (rdev->scratch.free[i]) {
  76. rdev->scratch.free[i] = false;
  77. *reg = rdev->scratch.reg[i];
  78. return 0;
  79. }
  80. }
  81. return -EINVAL;
  82. }
  83. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
  84. {
  85. int i;
  86. for (i = 0; i < rdev->scratch.num_reg; i++) {
  87. if (rdev->scratch.reg[i] == reg) {
  88. rdev->scratch.free[i] = true;
  89. return;
  90. }
  91. }
  92. }
  93. /*
  94. * MC common functions
  95. */
  96. int radeon_mc_setup(struct radeon_device *rdev)
  97. {
  98. uint32_t tmp;
  99. /* Some chips have an "issue" with the memory controller, the
  100. * location must be aligned to the size. We just align it down,
  101. * too bad if we walk over the top of system memory, we don't
  102. * use DMA without a remapped anyway.
  103. * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
  104. */
  105. /* FGLRX seems to setup like this, VRAM a 0, then GART.
  106. */
  107. /*
  108. * Note: from R6xx the address space is 40bits but here we only
  109. * use 32bits (still have to see a card which would exhaust 4G
  110. * address space).
  111. */
  112. if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
  113. /* vram location was already setup try to put gtt after
  114. * if it fits */
  115. tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
  116. tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
  117. if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
  118. rdev->mc.gtt_location = tmp;
  119. } else {
  120. if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
  121. printk(KERN_ERR "[drm] GTT too big to fit "
  122. "before or after vram location.\n");
  123. return -EINVAL;
  124. }
  125. rdev->mc.gtt_location = 0;
  126. }
  127. } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
  128. /* gtt location was already setup try to put vram before
  129. * if it fits */
  130. if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
  131. rdev->mc.vram_location = 0;
  132. } else {
  133. tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
  134. tmp += (rdev->mc.mc_vram_size - 1);
  135. tmp &= ~(rdev->mc.mc_vram_size - 1);
  136. if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
  137. rdev->mc.vram_location = tmp;
  138. } else {
  139. printk(KERN_ERR "[drm] vram too big to fit "
  140. "before or after GTT location.\n");
  141. return -EINVAL;
  142. }
  143. }
  144. } else {
  145. rdev->mc.vram_location = 0;
  146. tmp = rdev->mc.mc_vram_size;
  147. tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
  148. rdev->mc.gtt_location = tmp;
  149. }
  150. rdev->mc.vram_start = rdev->mc.vram_location;
  151. rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
  152. rdev->mc.gtt_start = rdev->mc.gtt_location;
  153. rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
  154. DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
  155. DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
  156. (unsigned)rdev->mc.vram_location,
  157. (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
  158. DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
  159. DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
  160. (unsigned)rdev->mc.gtt_location,
  161. (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
  162. return 0;
  163. }
  164. /*
  165. * GPU helpers function.
  166. */
  167. bool radeon_card_posted(struct radeon_device *rdev)
  168. {
  169. uint32_t reg;
  170. /* first check CRTCs */
  171. if (ASIC_IS_AVIVO(rdev)) {
  172. reg = RREG32(AVIVO_D1CRTC_CONTROL) |
  173. RREG32(AVIVO_D2CRTC_CONTROL);
  174. if (reg & AVIVO_CRTC_EN) {
  175. return true;
  176. }
  177. } else {
  178. reg = RREG32(RADEON_CRTC_GEN_CNTL) |
  179. RREG32(RADEON_CRTC2_GEN_CNTL);
  180. if (reg & RADEON_CRTC_EN) {
  181. return true;
  182. }
  183. }
  184. /* then check MEM_SIZE, in case the crtcs are off */
  185. if (rdev->family >= CHIP_R600)
  186. reg = RREG32(R600_CONFIG_MEMSIZE);
  187. else
  188. reg = RREG32(RADEON_CONFIG_MEMSIZE);
  189. if (reg)
  190. return true;
  191. return false;
  192. }
  193. int radeon_dummy_page_init(struct radeon_device *rdev)
  194. {
  195. rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
  196. if (rdev->dummy_page.page == NULL)
  197. return -ENOMEM;
  198. rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
  199. 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  200. if (!rdev->dummy_page.addr) {
  201. __free_page(rdev->dummy_page.page);
  202. rdev->dummy_page.page = NULL;
  203. return -ENOMEM;
  204. }
  205. return 0;
  206. }
  207. void radeon_dummy_page_fini(struct radeon_device *rdev)
  208. {
  209. if (rdev->dummy_page.page == NULL)
  210. return;
  211. pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
  212. PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  213. __free_page(rdev->dummy_page.page);
  214. rdev->dummy_page.page = NULL;
  215. }
  216. /*
  217. * Registers accessors functions.
  218. */
  219. uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  220. {
  221. DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  222. BUG_ON(1);
  223. return 0;
  224. }
  225. void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  226. {
  227. DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  228. reg, v);
  229. BUG_ON(1);
  230. }
  231. void radeon_register_accessor_init(struct radeon_device *rdev)
  232. {
  233. rdev->mc_rreg = &radeon_invalid_rreg;
  234. rdev->mc_wreg = &radeon_invalid_wreg;
  235. rdev->pll_rreg = &radeon_invalid_rreg;
  236. rdev->pll_wreg = &radeon_invalid_wreg;
  237. rdev->pciep_rreg = &radeon_invalid_rreg;
  238. rdev->pciep_wreg = &radeon_invalid_wreg;
  239. /* Don't change order as we are overridding accessor. */
  240. if (rdev->family < CHIP_RV515) {
  241. rdev->pcie_reg_mask = 0xff;
  242. } else {
  243. rdev->pcie_reg_mask = 0x7ff;
  244. }
  245. /* FIXME: not sure here */
  246. if (rdev->family <= CHIP_R580) {
  247. rdev->pll_rreg = &r100_pll_rreg;
  248. rdev->pll_wreg = &r100_pll_wreg;
  249. }
  250. if (rdev->family >= CHIP_R420) {
  251. rdev->mc_rreg = &r420_mc_rreg;
  252. rdev->mc_wreg = &r420_mc_wreg;
  253. }
  254. if (rdev->family >= CHIP_RV515) {
  255. rdev->mc_rreg = &rv515_mc_rreg;
  256. rdev->mc_wreg = &rv515_mc_wreg;
  257. }
  258. if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
  259. rdev->mc_rreg = &rs400_mc_rreg;
  260. rdev->mc_wreg = &rs400_mc_wreg;
  261. }
  262. if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  263. rdev->mc_rreg = &rs690_mc_rreg;
  264. rdev->mc_wreg = &rs690_mc_wreg;
  265. }
  266. if (rdev->family == CHIP_RS600) {
  267. rdev->mc_rreg = &rs600_mc_rreg;
  268. rdev->mc_wreg = &rs600_mc_wreg;
  269. }
  270. if (rdev->family >= CHIP_R600) {
  271. rdev->pciep_rreg = &r600_pciep_rreg;
  272. rdev->pciep_wreg = &r600_pciep_wreg;
  273. }
  274. }
  275. /*
  276. * ASIC
  277. */
  278. int radeon_asic_init(struct radeon_device *rdev)
  279. {
  280. radeon_register_accessor_init(rdev);
  281. switch (rdev->family) {
  282. case CHIP_R100:
  283. case CHIP_RV100:
  284. case CHIP_RS100:
  285. case CHIP_RV200:
  286. case CHIP_RS200:
  287. case CHIP_R200:
  288. case CHIP_RV250:
  289. case CHIP_RS300:
  290. case CHIP_RV280:
  291. rdev->asic = &r100_asic;
  292. break;
  293. case CHIP_R300:
  294. case CHIP_R350:
  295. case CHIP_RV350:
  296. case CHIP_RV380:
  297. rdev->asic = &r300_asic;
  298. if (rdev->flags & RADEON_IS_PCIE) {
  299. rdev->asic->gart_init = &rv370_pcie_gart_init;
  300. rdev->asic->gart_fini = &rv370_pcie_gart_fini;
  301. rdev->asic->gart_enable = &rv370_pcie_gart_enable;
  302. rdev->asic->gart_disable = &rv370_pcie_gart_disable;
  303. rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
  304. rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
  305. }
  306. break;
  307. case CHIP_R420:
  308. case CHIP_R423:
  309. case CHIP_RV410:
  310. rdev->asic = &r420_asic;
  311. break;
  312. case CHIP_RS400:
  313. case CHIP_RS480:
  314. rdev->asic = &rs400_asic;
  315. break;
  316. case CHIP_RS600:
  317. rdev->asic = &rs600_asic;
  318. break;
  319. case CHIP_RS690:
  320. case CHIP_RS740:
  321. rdev->asic = &rs690_asic;
  322. break;
  323. case CHIP_RV515:
  324. rdev->asic = &rv515_asic;
  325. break;
  326. case CHIP_R520:
  327. case CHIP_RV530:
  328. case CHIP_RV560:
  329. case CHIP_RV570:
  330. case CHIP_R580:
  331. rdev->asic = &r520_asic;
  332. break;
  333. case CHIP_R600:
  334. case CHIP_RV610:
  335. case CHIP_RV630:
  336. case CHIP_RV620:
  337. case CHIP_RV635:
  338. case CHIP_RV670:
  339. case CHIP_RS780:
  340. case CHIP_RS880:
  341. rdev->asic = &r600_asic;
  342. break;
  343. case CHIP_RV770:
  344. case CHIP_RV730:
  345. case CHIP_RV710:
  346. case CHIP_RV740:
  347. rdev->asic = &rv770_asic;
  348. break;
  349. default:
  350. /* FIXME: not supported yet */
  351. return -EINVAL;
  352. }
  353. return 0;
  354. }
  355. /*
  356. * Wrapper around modesetting bits.
  357. */
  358. int radeon_clocks_init(struct radeon_device *rdev)
  359. {
  360. int r;
  361. r = radeon_static_clocks_init(rdev->ddev);
  362. if (r) {
  363. return r;
  364. }
  365. DRM_INFO("Clocks initialized !\n");
  366. return 0;
  367. }
  368. void radeon_clocks_fini(struct radeon_device *rdev)
  369. {
  370. }
  371. /* ATOM accessor methods */
  372. static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
  373. {
  374. struct radeon_device *rdev = info->dev->dev_private;
  375. uint32_t r;
  376. r = rdev->pll_rreg(rdev, reg);
  377. return r;
  378. }
  379. static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
  380. {
  381. struct radeon_device *rdev = info->dev->dev_private;
  382. rdev->pll_wreg(rdev, reg, val);
  383. }
  384. static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
  385. {
  386. struct radeon_device *rdev = info->dev->dev_private;
  387. uint32_t r;
  388. r = rdev->mc_rreg(rdev, reg);
  389. return r;
  390. }
  391. static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
  392. {
  393. struct radeon_device *rdev = info->dev->dev_private;
  394. rdev->mc_wreg(rdev, reg, val);
  395. }
  396. static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
  397. {
  398. struct radeon_device *rdev = info->dev->dev_private;
  399. WREG32(reg*4, val);
  400. }
  401. static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
  402. {
  403. struct radeon_device *rdev = info->dev->dev_private;
  404. uint32_t r;
  405. r = RREG32(reg*4);
  406. return r;
  407. }
  408. static struct card_info atom_card_info = {
  409. .dev = NULL,
  410. .reg_read = cail_reg_read,
  411. .reg_write = cail_reg_write,
  412. .mc_read = cail_mc_read,
  413. .mc_write = cail_mc_write,
  414. .pll_read = cail_pll_read,
  415. .pll_write = cail_pll_write,
  416. };
  417. int radeon_atombios_init(struct radeon_device *rdev)
  418. {
  419. atom_card_info.dev = rdev->ddev;
  420. rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
  421. radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
  422. return 0;
  423. }
  424. void radeon_atombios_fini(struct radeon_device *rdev)
  425. {
  426. kfree(rdev->mode_info.atom_context);
  427. }
  428. int radeon_combios_init(struct radeon_device *rdev)
  429. {
  430. radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
  431. return 0;
  432. }
  433. void radeon_combios_fini(struct radeon_device *rdev)
  434. {
  435. }
  436. /* if we get transitioned to only one device, tak VGA back */
  437. static unsigned int radeon_vga_set_decode(void *cookie, bool state)
  438. {
  439. struct radeon_device *rdev = cookie;
  440. radeon_vga_set_state(rdev, state);
  441. if (state)
  442. return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
  443. VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  444. else
  445. return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  446. }
  447. /*
  448. * Radeon device.
  449. */
  450. int radeon_device_init(struct radeon_device *rdev,
  451. struct drm_device *ddev,
  452. struct pci_dev *pdev,
  453. uint32_t flags)
  454. {
  455. int r;
  456. int dma_bits;
  457. DRM_INFO("radeon: Initializing kernel modesetting.\n");
  458. rdev->shutdown = false;
  459. rdev->dev = &pdev->dev;
  460. rdev->ddev = ddev;
  461. rdev->pdev = pdev;
  462. rdev->flags = flags;
  463. rdev->family = flags & RADEON_FAMILY_MASK;
  464. rdev->is_atom_bios = false;
  465. rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
  466. rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  467. rdev->gpu_lockup = false;
  468. rdev->accel_working = false;
  469. /* mutex initialization are all done here so we
  470. * can recall function without having locking issues */
  471. mutex_init(&rdev->cs_mutex);
  472. mutex_init(&rdev->ib_pool.mutex);
  473. mutex_init(&rdev->cp.mutex);
  474. rwlock_init(&rdev->fence_drv.lock);
  475. INIT_LIST_HEAD(&rdev->gem.objects);
  476. /* Set asic functions */
  477. r = radeon_asic_init(rdev);
  478. if (r) {
  479. return r;
  480. }
  481. if (radeon_agpmode == -1) {
  482. rdev->flags &= ~RADEON_IS_AGP;
  483. if (rdev->family >= CHIP_RV515 ||
  484. rdev->family == CHIP_RV380 ||
  485. rdev->family == CHIP_RV410 ||
  486. rdev->family == CHIP_R423) {
  487. DRM_INFO("Forcing AGP to PCIE mode\n");
  488. rdev->flags |= RADEON_IS_PCIE;
  489. rdev->asic->gart_init = &rv370_pcie_gart_init;
  490. rdev->asic->gart_fini = &rv370_pcie_gart_fini;
  491. rdev->asic->gart_enable = &rv370_pcie_gart_enable;
  492. rdev->asic->gart_disable = &rv370_pcie_gart_disable;
  493. rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
  494. rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
  495. } else {
  496. DRM_INFO("Forcing AGP to PCI mode\n");
  497. rdev->flags |= RADEON_IS_PCI;
  498. rdev->asic->gart_init = &r100_pci_gart_init;
  499. rdev->asic->gart_fini = &r100_pci_gart_fini;
  500. rdev->asic->gart_enable = &r100_pci_gart_enable;
  501. rdev->asic->gart_disable = &r100_pci_gart_disable;
  502. rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
  503. rdev->asic->gart_set_page = &r100_pci_gart_set_page;
  504. }
  505. }
  506. /* set DMA mask + need_dma32 flags.
  507. * PCIE - can handle 40-bits.
  508. * IGP - can handle 40-bits (in theory)
  509. * AGP - generally dma32 is safest
  510. * PCI - only dma32
  511. */
  512. rdev->need_dma32 = false;
  513. if (rdev->flags & RADEON_IS_AGP)
  514. rdev->need_dma32 = true;
  515. if (rdev->flags & RADEON_IS_PCI)
  516. rdev->need_dma32 = true;
  517. dma_bits = rdev->need_dma32 ? 32 : 40;
  518. r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
  519. if (r) {
  520. printk(KERN_WARNING "radeon: No suitable DMA available.\n");
  521. }
  522. /* Registers mapping */
  523. /* TODO: block userspace mapping of io register */
  524. rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
  525. rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
  526. rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
  527. if (rdev->rmmio == NULL) {
  528. return -ENOMEM;
  529. }
  530. DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
  531. DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
  532. rdev->new_init_path = false;
  533. r = radeon_init(rdev);
  534. if (r) {
  535. return r;
  536. }
  537. /* if we have > 1 VGA cards, then disable the radeon VGA resources */
  538. r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
  539. if (r) {
  540. return -EINVAL;
  541. }
  542. if (!rdev->new_init_path) {
  543. /* Setup errata flags */
  544. radeon_errata(rdev);
  545. /* Initialize scratch registers */
  546. radeon_scratch_init(rdev);
  547. /* Initialize surface registers */
  548. radeon_surface_init(rdev);
  549. /* BIOS*/
  550. if (!radeon_get_bios(rdev)) {
  551. if (ASIC_IS_AVIVO(rdev))
  552. return -EINVAL;
  553. }
  554. if (rdev->is_atom_bios) {
  555. r = radeon_atombios_init(rdev);
  556. if (r) {
  557. return r;
  558. }
  559. } else {
  560. r = radeon_combios_init(rdev);
  561. if (r) {
  562. return r;
  563. }
  564. }
  565. /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  566. if (radeon_gpu_reset(rdev)) {
  567. /* FIXME: what do we want to do here ? */
  568. }
  569. /* check if cards are posted or not */
  570. if (!radeon_card_posted(rdev) && rdev->bios) {
  571. DRM_INFO("GPU not posted. posting now...\n");
  572. if (rdev->is_atom_bios) {
  573. atom_asic_init(rdev->mode_info.atom_context);
  574. } else {
  575. radeon_combios_asic_init(rdev->ddev);
  576. }
  577. }
  578. /* Get clock & vram information */
  579. radeon_get_clock_info(rdev->ddev);
  580. radeon_vram_info(rdev);
  581. /* Initialize clocks */
  582. r = radeon_clocks_init(rdev);
  583. if (r) {
  584. return r;
  585. }
  586. /* Initialize memory controller (also test AGP) */
  587. r = radeon_mc_init(rdev);
  588. if (r) {
  589. return r;
  590. }
  591. /* Fence driver */
  592. r = radeon_fence_driver_init(rdev);
  593. if (r) {
  594. return r;
  595. }
  596. r = radeon_irq_kms_init(rdev);
  597. if (r) {
  598. return r;
  599. }
  600. /* Memory manager */
  601. r = radeon_object_init(rdev);
  602. if (r) {
  603. return r;
  604. }
  605. r = radeon_gpu_gart_init(rdev);
  606. if (r)
  607. return r;
  608. /* Initialize GART (initialize after TTM so we can allocate
  609. * memory through TTM but finalize after TTM) */
  610. r = radeon_gart_enable(rdev);
  611. if (r)
  612. return 0;
  613. r = radeon_gem_init(rdev);
  614. if (r)
  615. return 0;
  616. /* 1M ring buffer */
  617. r = radeon_cp_init(rdev, 1024 * 1024);
  618. if (r)
  619. return 0;
  620. r = radeon_wb_init(rdev);
  621. if (r)
  622. DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
  623. r = radeon_ib_pool_init(rdev);
  624. if (r)
  625. return 0;
  626. r = radeon_ib_test(rdev);
  627. if (r)
  628. return 0;
  629. rdev->accel_working = true;
  630. }
  631. DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
  632. if (radeon_testing) {
  633. radeon_test_moves(rdev);
  634. }
  635. if (radeon_benchmarking) {
  636. radeon_benchmark(rdev);
  637. }
  638. return 0;
  639. }
  640. void radeon_device_fini(struct radeon_device *rdev)
  641. {
  642. DRM_INFO("radeon: finishing device.\n");
  643. rdev->shutdown = true;
  644. /* Order matter so becarefull if you rearrange anythings */
  645. if (!rdev->new_init_path) {
  646. radeon_ib_pool_fini(rdev);
  647. radeon_cp_fini(rdev);
  648. radeon_wb_fini(rdev);
  649. radeon_gpu_gart_fini(rdev);
  650. radeon_gem_fini(rdev);
  651. radeon_mc_fini(rdev);
  652. #if __OS_HAS_AGP
  653. radeon_agp_fini(rdev);
  654. #endif
  655. radeon_irq_kms_fini(rdev);
  656. vga_client_register(rdev->pdev, NULL, NULL, NULL);
  657. radeon_fence_driver_fini(rdev);
  658. radeon_clocks_fini(rdev);
  659. radeon_object_fini(rdev);
  660. if (rdev->is_atom_bios) {
  661. radeon_atombios_fini(rdev);
  662. } else {
  663. radeon_combios_fini(rdev);
  664. }
  665. kfree(rdev->bios);
  666. rdev->bios = NULL;
  667. } else {
  668. radeon_fini(rdev);
  669. }
  670. iounmap(rdev->rmmio);
  671. rdev->rmmio = NULL;
  672. }
  673. /*
  674. * Suspend & resume.
  675. */
  676. int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
  677. {
  678. struct radeon_device *rdev = dev->dev_private;
  679. struct drm_crtc *crtc;
  680. if (dev == NULL || rdev == NULL) {
  681. return -ENODEV;
  682. }
  683. if (state.event == PM_EVENT_PRETHAW) {
  684. return 0;
  685. }
  686. /* unpin the front buffers */
  687. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  688. struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
  689. struct radeon_object *robj;
  690. if (rfb == NULL || rfb->obj == NULL) {
  691. continue;
  692. }
  693. robj = rfb->obj->driver_private;
  694. if (robj != rdev->fbdev_robj) {
  695. radeon_object_unpin(robj);
  696. }
  697. }
  698. /* evict vram memory */
  699. radeon_object_evict_vram(rdev);
  700. /* wait for gpu to finish processing current batch */
  701. radeon_fence_wait_last(rdev);
  702. radeon_save_bios_scratch_regs(rdev);
  703. if (!rdev->new_init_path) {
  704. radeon_cp_disable(rdev);
  705. radeon_gart_disable(rdev);
  706. rdev->irq.sw_int = false;
  707. radeon_irq_set(rdev);
  708. } else {
  709. radeon_suspend(rdev);
  710. }
  711. /* evict remaining vram memory */
  712. radeon_object_evict_vram(rdev);
  713. pci_save_state(dev->pdev);
  714. if (state.event == PM_EVENT_SUSPEND) {
  715. /* Shut down the device */
  716. pci_disable_device(dev->pdev);
  717. pci_set_power_state(dev->pdev, PCI_D3hot);
  718. }
  719. acquire_console_sem();
  720. fb_set_suspend(rdev->fbdev_info, 1);
  721. release_console_sem();
  722. return 0;
  723. }
  724. int radeon_resume_kms(struct drm_device *dev)
  725. {
  726. struct radeon_device *rdev = dev->dev_private;
  727. int r;
  728. acquire_console_sem();
  729. pci_set_power_state(dev->pdev, PCI_D0);
  730. pci_restore_state(dev->pdev);
  731. if (pci_enable_device(dev->pdev)) {
  732. release_console_sem();
  733. return -1;
  734. }
  735. pci_set_master(dev->pdev);
  736. /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  737. if (!rdev->new_init_path) {
  738. if (radeon_gpu_reset(rdev)) {
  739. /* FIXME: what do we want to do here ? */
  740. }
  741. /* post card */
  742. if (rdev->is_atom_bios) {
  743. atom_asic_init(rdev->mode_info.atom_context);
  744. } else {
  745. radeon_combios_asic_init(rdev->ddev);
  746. }
  747. /* Initialize clocks */
  748. r = radeon_clocks_init(rdev);
  749. if (r) {
  750. release_console_sem();
  751. return r;
  752. }
  753. /* Enable IRQ */
  754. rdev->irq.sw_int = true;
  755. radeon_irq_set(rdev);
  756. /* Initialize GPU Memory Controller */
  757. r = radeon_mc_init(rdev);
  758. if (r) {
  759. goto out;
  760. }
  761. r = radeon_gart_enable(rdev);
  762. if (r) {
  763. goto out;
  764. }
  765. r = radeon_cp_init(rdev, rdev->cp.ring_size);
  766. if (r) {
  767. goto out;
  768. }
  769. } else {
  770. radeon_resume(rdev);
  771. }
  772. out:
  773. radeon_restore_bios_scratch_regs(rdev);
  774. fb_set_suspend(rdev->fbdev_info, 0);
  775. release_console_sem();
  776. /* blat the mode back in */
  777. drm_helper_resume_force_mode(dev);
  778. return 0;
  779. }
  780. /*
  781. * Debugfs
  782. */
  783. struct radeon_debugfs {
  784. struct drm_info_list *files;
  785. unsigned num_files;
  786. };
  787. static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
  788. static unsigned _radeon_debugfs_count = 0;
  789. int radeon_debugfs_add_files(struct radeon_device *rdev,
  790. struct drm_info_list *files,
  791. unsigned nfiles)
  792. {
  793. unsigned i;
  794. for (i = 0; i < _radeon_debugfs_count; i++) {
  795. if (_radeon_debugfs[i].files == files) {
  796. /* Already registered */
  797. return 0;
  798. }
  799. }
  800. if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
  801. DRM_ERROR("Reached maximum number of debugfs files.\n");
  802. DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
  803. return -EINVAL;
  804. }
  805. _radeon_debugfs[_radeon_debugfs_count].files = files;
  806. _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
  807. _radeon_debugfs_count++;
  808. #if defined(CONFIG_DEBUG_FS)
  809. drm_debugfs_create_files(files, nfiles,
  810. rdev->ddev->control->debugfs_root,
  811. rdev->ddev->control);
  812. drm_debugfs_create_files(files, nfiles,
  813. rdev->ddev->primary->debugfs_root,
  814. rdev->ddev->primary);
  815. #endif
  816. return 0;
  817. }
  818. #if defined(CONFIG_DEBUG_FS)
  819. int radeon_debugfs_init(struct drm_minor *minor)
  820. {
  821. return 0;
  822. }
  823. void radeon_debugfs_cleanup(struct drm_minor *minor)
  824. {
  825. unsigned i;
  826. for (i = 0; i < _radeon_debugfs_count; i++) {
  827. drm_debugfs_remove_files(_radeon_debugfs[i].files,
  828. _radeon_debugfs[i].num_files, minor);
  829. }
  830. }
  831. #endif