radeon.h 34 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #ifndef __RADEON_H__
  29. #define __RADEON_H__
  30. #include "radeon_object.h"
  31. /* TODO: Here are things that needs to be done :
  32. * - surface allocator & initializer : (bit like scratch reg) should
  33. * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34. * related to surface
  35. * - WB : write back stuff (do it bit like scratch reg things)
  36. * - Vblank : look at Jesse's rework and what we should do
  37. * - r600/r700: gart & cp
  38. * - cs : clean cs ioctl use bitmap & things like that.
  39. * - power management stuff
  40. * - Barrier in gart code
  41. * - Unmappabled vram ?
  42. * - TESTING, TESTING, TESTING
  43. */
  44. #include <asm/atomic.h>
  45. #include <linux/wait.h>
  46. #include <linux/list.h>
  47. #include <linux/kref.h>
  48. #include "radeon_mode.h"
  49. #include "radeon_reg.h"
  50. /*
  51. * Modules parameters.
  52. */
  53. extern int radeon_no_wb;
  54. extern int radeon_modeset;
  55. extern int radeon_dynclks;
  56. extern int radeon_r4xx_atom;
  57. extern int radeon_agpmode;
  58. extern int radeon_vram_limit;
  59. extern int radeon_gart_size;
  60. extern int radeon_benchmarking;
  61. extern int radeon_testing;
  62. extern int radeon_connector_table;
  63. extern int radeon_tv;
  64. /*
  65. * Copy from radeon_drv.h so we don't have to include both and have conflicting
  66. * symbol;
  67. */
  68. #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
  69. #define RADEON_IB_POOL_SIZE 16
  70. #define RADEON_DEBUGFS_MAX_NUM_FILES 32
  71. #define RADEONFB_CONN_LIMIT 4
  72. #define RADEON_BIOS_NUM_SCRATCH 8
  73. enum radeon_family {
  74. CHIP_R100,
  75. CHIP_RV100,
  76. CHIP_RS100,
  77. CHIP_RV200,
  78. CHIP_RS200,
  79. CHIP_R200,
  80. CHIP_RV250,
  81. CHIP_RS300,
  82. CHIP_RV280,
  83. CHIP_R300,
  84. CHIP_R350,
  85. CHIP_RV350,
  86. CHIP_RV380,
  87. CHIP_R420,
  88. CHIP_R423,
  89. CHIP_RV410,
  90. CHIP_RS400,
  91. CHIP_RS480,
  92. CHIP_RS600,
  93. CHIP_RS690,
  94. CHIP_RS740,
  95. CHIP_RV515,
  96. CHIP_R520,
  97. CHIP_RV530,
  98. CHIP_RV560,
  99. CHIP_RV570,
  100. CHIP_R580,
  101. CHIP_R600,
  102. CHIP_RV610,
  103. CHIP_RV630,
  104. CHIP_RV670,
  105. CHIP_RV620,
  106. CHIP_RV635,
  107. CHIP_RS780,
  108. CHIP_RS880,
  109. CHIP_RV770,
  110. CHIP_RV730,
  111. CHIP_RV710,
  112. CHIP_RV740,
  113. CHIP_LAST,
  114. };
  115. enum radeon_chip_flags {
  116. RADEON_FAMILY_MASK = 0x0000ffffUL,
  117. RADEON_FLAGS_MASK = 0xffff0000UL,
  118. RADEON_IS_MOBILITY = 0x00010000UL,
  119. RADEON_IS_IGP = 0x00020000UL,
  120. RADEON_SINGLE_CRTC = 0x00040000UL,
  121. RADEON_IS_AGP = 0x00080000UL,
  122. RADEON_HAS_HIERZ = 0x00100000UL,
  123. RADEON_IS_PCIE = 0x00200000UL,
  124. RADEON_NEW_MEMMAP = 0x00400000UL,
  125. RADEON_IS_PCI = 0x00800000UL,
  126. RADEON_IS_IGPGART = 0x01000000UL,
  127. };
  128. /*
  129. * Errata workarounds.
  130. */
  131. enum radeon_pll_errata {
  132. CHIP_ERRATA_R300_CG = 0x00000001,
  133. CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
  134. CHIP_ERRATA_PLL_DELAY = 0x00000004
  135. };
  136. struct radeon_device;
  137. /*
  138. * BIOS.
  139. */
  140. bool radeon_get_bios(struct radeon_device *rdev);
  141. /*
  142. * Dummy page
  143. */
  144. struct radeon_dummy_page {
  145. struct page *page;
  146. dma_addr_t addr;
  147. };
  148. int radeon_dummy_page_init(struct radeon_device *rdev);
  149. void radeon_dummy_page_fini(struct radeon_device *rdev);
  150. /*
  151. * Clocks
  152. */
  153. struct radeon_clock {
  154. struct radeon_pll p1pll;
  155. struct radeon_pll p2pll;
  156. struct radeon_pll spll;
  157. struct radeon_pll mpll;
  158. /* 10 Khz units */
  159. uint32_t default_mclk;
  160. uint32_t default_sclk;
  161. };
  162. /*
  163. * Fences.
  164. */
  165. struct radeon_fence_driver {
  166. uint32_t scratch_reg;
  167. atomic_t seq;
  168. uint32_t last_seq;
  169. unsigned long count_timeout;
  170. wait_queue_head_t queue;
  171. rwlock_t lock;
  172. struct list_head created;
  173. struct list_head emited;
  174. struct list_head signaled;
  175. };
  176. struct radeon_fence {
  177. struct radeon_device *rdev;
  178. struct kref kref;
  179. struct list_head list;
  180. /* protected by radeon_fence.lock */
  181. uint32_t seq;
  182. unsigned long timeout;
  183. bool emited;
  184. bool signaled;
  185. };
  186. int radeon_fence_driver_init(struct radeon_device *rdev);
  187. void radeon_fence_driver_fini(struct radeon_device *rdev);
  188. int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
  189. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
  190. void radeon_fence_process(struct radeon_device *rdev);
  191. bool radeon_fence_signaled(struct radeon_fence *fence);
  192. int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
  193. int radeon_fence_wait_next(struct radeon_device *rdev);
  194. int radeon_fence_wait_last(struct radeon_device *rdev);
  195. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
  196. void radeon_fence_unref(struct radeon_fence **fence);
  197. /*
  198. * Tiling registers
  199. */
  200. struct radeon_surface_reg {
  201. struct radeon_object *robj;
  202. };
  203. #define RADEON_GEM_MAX_SURFACES 8
  204. /*
  205. * Radeon buffer.
  206. */
  207. struct radeon_object;
  208. struct radeon_object_list {
  209. struct list_head list;
  210. struct radeon_object *robj;
  211. uint64_t gpu_offset;
  212. unsigned rdomain;
  213. unsigned wdomain;
  214. uint32_t tiling_flags;
  215. };
  216. int radeon_object_init(struct radeon_device *rdev);
  217. void radeon_object_fini(struct radeon_device *rdev);
  218. int radeon_object_create(struct radeon_device *rdev,
  219. struct drm_gem_object *gobj,
  220. unsigned long size,
  221. bool kernel,
  222. uint32_t domain,
  223. bool interruptible,
  224. struct radeon_object **robj_ptr);
  225. int radeon_object_kmap(struct radeon_object *robj, void **ptr);
  226. void radeon_object_kunmap(struct radeon_object *robj);
  227. void radeon_object_unref(struct radeon_object **robj);
  228. int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
  229. uint64_t *gpu_addr);
  230. void radeon_object_unpin(struct radeon_object *robj);
  231. int radeon_object_wait(struct radeon_object *robj);
  232. int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
  233. int radeon_object_evict_vram(struct radeon_device *rdev);
  234. int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
  235. void radeon_object_force_delete(struct radeon_device *rdev);
  236. void radeon_object_list_add_object(struct radeon_object_list *lobj,
  237. struct list_head *head);
  238. int radeon_object_list_validate(struct list_head *head, void *fence);
  239. void radeon_object_list_unvalidate(struct list_head *head);
  240. void radeon_object_list_clean(struct list_head *head);
  241. int radeon_object_fbdev_mmap(struct radeon_object *robj,
  242. struct vm_area_struct *vma);
  243. unsigned long radeon_object_size(struct radeon_object *robj);
  244. void radeon_object_clear_surface_reg(struct radeon_object *robj);
  245. int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
  246. bool force_drop);
  247. void radeon_object_set_tiling_flags(struct radeon_object *robj,
  248. uint32_t tiling_flags, uint32_t pitch);
  249. void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
  250. void radeon_bo_move_notify(struct ttm_buffer_object *bo,
  251. struct ttm_mem_reg *mem);
  252. void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
  253. /*
  254. * GEM objects.
  255. */
  256. struct radeon_gem {
  257. struct list_head objects;
  258. };
  259. int radeon_gem_init(struct radeon_device *rdev);
  260. void radeon_gem_fini(struct radeon_device *rdev);
  261. int radeon_gem_object_create(struct radeon_device *rdev, int size,
  262. int alignment, int initial_domain,
  263. bool discardable, bool kernel,
  264. bool interruptible,
  265. struct drm_gem_object **obj);
  266. int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
  267. uint64_t *gpu_addr);
  268. void radeon_gem_object_unpin(struct drm_gem_object *obj);
  269. /*
  270. * GART structures, functions & helpers
  271. */
  272. struct radeon_mc;
  273. struct radeon_gart_table_ram {
  274. volatile uint32_t *ptr;
  275. };
  276. struct radeon_gart_table_vram {
  277. struct radeon_object *robj;
  278. volatile uint32_t *ptr;
  279. };
  280. union radeon_gart_table {
  281. struct radeon_gart_table_ram ram;
  282. struct radeon_gart_table_vram vram;
  283. };
  284. struct radeon_gart {
  285. dma_addr_t table_addr;
  286. unsigned num_gpu_pages;
  287. unsigned num_cpu_pages;
  288. unsigned table_size;
  289. union radeon_gart_table table;
  290. struct page **pages;
  291. dma_addr_t *pages_addr;
  292. bool ready;
  293. };
  294. int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
  295. void radeon_gart_table_ram_free(struct radeon_device *rdev);
  296. int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
  297. void radeon_gart_table_vram_free(struct radeon_device *rdev);
  298. int radeon_gart_init(struct radeon_device *rdev);
  299. void radeon_gart_fini(struct radeon_device *rdev);
  300. void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
  301. int pages);
  302. int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
  303. int pages, struct page **pagelist);
  304. /*
  305. * GPU MC structures, functions & helpers
  306. */
  307. struct radeon_mc {
  308. resource_size_t aper_size;
  309. resource_size_t aper_base;
  310. resource_size_t agp_base;
  311. /* for some chips with <= 32MB we need to lie
  312. * about vram size near mc fb location */
  313. u64 mc_vram_size;
  314. u64 gtt_location;
  315. u64 gtt_size;
  316. u64 gtt_start;
  317. u64 gtt_end;
  318. u64 vram_location;
  319. u64 vram_start;
  320. u64 vram_end;
  321. unsigned vram_width;
  322. u64 real_vram_size;
  323. int vram_mtrr;
  324. bool vram_is_ddr;
  325. };
  326. int radeon_mc_setup(struct radeon_device *rdev);
  327. /*
  328. * GPU scratch registers structures, functions & helpers
  329. */
  330. struct radeon_scratch {
  331. unsigned num_reg;
  332. bool free[32];
  333. uint32_t reg[32];
  334. };
  335. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
  336. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
  337. /*
  338. * IRQS.
  339. */
  340. struct radeon_irq {
  341. bool installed;
  342. bool sw_int;
  343. /* FIXME: use a define max crtc rather than hardcode it */
  344. bool crtc_vblank_int[2];
  345. };
  346. int radeon_irq_kms_init(struct radeon_device *rdev);
  347. void radeon_irq_kms_fini(struct radeon_device *rdev);
  348. /*
  349. * CP & ring.
  350. */
  351. struct radeon_ib {
  352. struct list_head list;
  353. unsigned long idx;
  354. uint64_t gpu_addr;
  355. struct radeon_fence *fence;
  356. volatile uint32_t *ptr;
  357. uint32_t length_dw;
  358. };
  359. /*
  360. * locking -
  361. * mutex protects scheduled_ibs, ready, alloc_bm
  362. */
  363. struct radeon_ib_pool {
  364. struct mutex mutex;
  365. struct radeon_object *robj;
  366. struct list_head scheduled_ibs;
  367. struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
  368. bool ready;
  369. DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
  370. };
  371. struct radeon_cp {
  372. struct radeon_object *ring_obj;
  373. volatile uint32_t *ring;
  374. unsigned rptr;
  375. unsigned wptr;
  376. unsigned wptr_old;
  377. unsigned ring_size;
  378. unsigned ring_free_dw;
  379. int count_dw;
  380. uint64_t gpu_addr;
  381. uint32_t align_mask;
  382. uint32_t ptr_mask;
  383. struct mutex mutex;
  384. bool ready;
  385. };
  386. struct r600_blit {
  387. struct radeon_object *shader_obj;
  388. u64 shader_gpu_addr;
  389. u32 vs_offset, ps_offset;
  390. u32 state_offset;
  391. u32 state_len;
  392. u32 vb_used, vb_total;
  393. struct radeon_ib *vb_ib;
  394. };
  395. int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
  396. void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
  397. int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
  398. int radeon_ib_pool_init(struct radeon_device *rdev);
  399. void radeon_ib_pool_fini(struct radeon_device *rdev);
  400. int radeon_ib_test(struct radeon_device *rdev);
  401. /* Ring access between begin & end cannot sleep */
  402. void radeon_ring_free_size(struct radeon_device *rdev);
  403. int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
  404. void radeon_ring_unlock_commit(struct radeon_device *rdev);
  405. void radeon_ring_unlock_undo(struct radeon_device *rdev);
  406. int radeon_ring_test(struct radeon_device *rdev);
  407. int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
  408. void radeon_ring_fini(struct radeon_device *rdev);
  409. /*
  410. * CS.
  411. */
  412. struct radeon_cs_reloc {
  413. struct drm_gem_object *gobj;
  414. struct radeon_object *robj;
  415. struct radeon_object_list lobj;
  416. uint32_t handle;
  417. uint32_t flags;
  418. };
  419. struct radeon_cs_chunk {
  420. uint32_t chunk_id;
  421. uint32_t length_dw;
  422. uint32_t *kdata;
  423. };
  424. struct radeon_cs_parser {
  425. struct radeon_device *rdev;
  426. struct drm_file *filp;
  427. /* chunks */
  428. unsigned nchunks;
  429. struct radeon_cs_chunk *chunks;
  430. uint64_t *chunks_array;
  431. /* IB */
  432. unsigned idx;
  433. /* relocations */
  434. unsigned nrelocs;
  435. struct radeon_cs_reloc *relocs;
  436. struct radeon_cs_reloc **relocs_ptr;
  437. struct list_head validated;
  438. /* indices of various chunks */
  439. int chunk_ib_idx;
  440. int chunk_relocs_idx;
  441. struct radeon_ib *ib;
  442. void *track;
  443. unsigned family;
  444. };
  445. struct radeon_cs_packet {
  446. unsigned idx;
  447. unsigned type;
  448. unsigned reg;
  449. unsigned opcode;
  450. int count;
  451. unsigned one_reg_wr;
  452. };
  453. typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
  454. struct radeon_cs_packet *pkt,
  455. unsigned idx, unsigned reg);
  456. typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
  457. struct radeon_cs_packet *pkt);
  458. /*
  459. * AGP
  460. */
  461. int radeon_agp_init(struct radeon_device *rdev);
  462. void radeon_agp_fini(struct radeon_device *rdev);
  463. /*
  464. * Writeback
  465. */
  466. struct radeon_wb {
  467. struct radeon_object *wb_obj;
  468. volatile uint32_t *wb;
  469. uint64_t gpu_addr;
  470. };
  471. /**
  472. * struct radeon_pm - power management datas
  473. * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
  474. * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
  475. * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
  476. * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
  477. * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
  478. * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
  479. * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
  480. * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
  481. * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
  482. * @sclk: GPU clock Mhz (core bandwith depends of this clock)
  483. * @needed_bandwidth: current bandwidth needs
  484. *
  485. * It keeps track of various data needed to take powermanagement decision.
  486. * Bandwith need is used to determine minimun clock of the GPU and memory.
  487. * Equation between gpu/memory clock and available bandwidth is hw dependent
  488. * (type of memory, bus size, efficiency, ...)
  489. */
  490. struct radeon_pm {
  491. fixed20_12 max_bandwidth;
  492. fixed20_12 igp_sideport_mclk;
  493. fixed20_12 igp_system_mclk;
  494. fixed20_12 igp_ht_link_clk;
  495. fixed20_12 igp_ht_link_width;
  496. fixed20_12 k8_bandwidth;
  497. fixed20_12 sideport_bandwidth;
  498. fixed20_12 ht_bandwidth;
  499. fixed20_12 core_bandwidth;
  500. fixed20_12 sclk;
  501. fixed20_12 needed_bandwidth;
  502. };
  503. /*
  504. * Benchmarking
  505. */
  506. void radeon_benchmark(struct radeon_device *rdev);
  507. /*
  508. * Testing
  509. */
  510. void radeon_test_moves(struct radeon_device *rdev);
  511. /*
  512. * Debugfs
  513. */
  514. int radeon_debugfs_add_files(struct radeon_device *rdev,
  515. struct drm_info_list *files,
  516. unsigned nfiles);
  517. int radeon_debugfs_fence_init(struct radeon_device *rdev);
  518. int r100_debugfs_rbbm_init(struct radeon_device *rdev);
  519. int r100_debugfs_cp_init(struct radeon_device *rdev);
  520. /*
  521. * ASIC specific functions.
  522. */
  523. struct radeon_asic {
  524. int (*init)(struct radeon_device *rdev);
  525. void (*fini)(struct radeon_device *rdev);
  526. int (*resume)(struct radeon_device *rdev);
  527. int (*suspend)(struct radeon_device *rdev);
  528. void (*errata)(struct radeon_device *rdev);
  529. void (*vram_info)(struct radeon_device *rdev);
  530. void (*vga_set_state)(struct radeon_device *rdev, bool state);
  531. int (*gpu_reset)(struct radeon_device *rdev);
  532. int (*mc_init)(struct radeon_device *rdev);
  533. void (*mc_fini)(struct radeon_device *rdev);
  534. int (*wb_init)(struct radeon_device *rdev);
  535. void (*wb_fini)(struct radeon_device *rdev);
  536. int (*gart_init)(struct radeon_device *rdev);
  537. void (*gart_fini)(struct radeon_device *rdev);
  538. int (*gart_enable)(struct radeon_device *rdev);
  539. void (*gart_disable)(struct radeon_device *rdev);
  540. void (*gart_tlb_flush)(struct radeon_device *rdev);
  541. int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
  542. int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
  543. void (*cp_fini)(struct radeon_device *rdev);
  544. void (*cp_disable)(struct radeon_device *rdev);
  545. void (*cp_commit)(struct radeon_device *rdev);
  546. void (*ring_start)(struct radeon_device *rdev);
  547. int (*ring_test)(struct radeon_device *rdev);
  548. void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
  549. int (*ib_test)(struct radeon_device *rdev);
  550. int (*irq_set)(struct radeon_device *rdev);
  551. int (*irq_process)(struct radeon_device *rdev);
  552. u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
  553. void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
  554. int (*cs_parse)(struct radeon_cs_parser *p);
  555. int (*copy_blit)(struct radeon_device *rdev,
  556. uint64_t src_offset,
  557. uint64_t dst_offset,
  558. unsigned num_pages,
  559. struct radeon_fence *fence);
  560. int (*copy_dma)(struct radeon_device *rdev,
  561. uint64_t src_offset,
  562. uint64_t dst_offset,
  563. unsigned num_pages,
  564. struct radeon_fence *fence);
  565. int (*copy)(struct radeon_device *rdev,
  566. uint64_t src_offset,
  567. uint64_t dst_offset,
  568. unsigned num_pages,
  569. struct radeon_fence *fence);
  570. void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
  571. void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
  572. void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
  573. void (*set_clock_gating)(struct radeon_device *rdev, int enable);
  574. int (*set_surface_reg)(struct radeon_device *rdev, int reg,
  575. uint32_t tiling_flags, uint32_t pitch,
  576. uint32_t offset, uint32_t obj_size);
  577. int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
  578. void (*bandwidth_update)(struct radeon_device *rdev);
  579. };
  580. /*
  581. * Asic structures
  582. */
  583. struct r100_asic {
  584. const unsigned *reg_safe_bm;
  585. unsigned reg_safe_bm_size;
  586. };
  587. struct r300_asic {
  588. const unsigned *reg_safe_bm;
  589. unsigned reg_safe_bm_size;
  590. };
  591. struct r600_asic {
  592. unsigned max_pipes;
  593. unsigned max_tile_pipes;
  594. unsigned max_simds;
  595. unsigned max_backends;
  596. unsigned max_gprs;
  597. unsigned max_threads;
  598. unsigned max_stack_entries;
  599. unsigned max_hw_contexts;
  600. unsigned max_gs_threads;
  601. unsigned sx_max_export_size;
  602. unsigned sx_max_export_pos_size;
  603. unsigned sx_max_export_smx_size;
  604. unsigned sq_num_cf_insts;
  605. };
  606. struct rv770_asic {
  607. unsigned max_pipes;
  608. unsigned max_tile_pipes;
  609. unsigned max_simds;
  610. unsigned max_backends;
  611. unsigned max_gprs;
  612. unsigned max_threads;
  613. unsigned max_stack_entries;
  614. unsigned max_hw_contexts;
  615. unsigned max_gs_threads;
  616. unsigned sx_max_export_size;
  617. unsigned sx_max_export_pos_size;
  618. unsigned sx_max_export_smx_size;
  619. unsigned sq_num_cf_insts;
  620. unsigned sx_num_of_sets;
  621. unsigned sc_prim_fifo_size;
  622. unsigned sc_hiz_tile_fifo_size;
  623. unsigned sc_earlyz_tile_fifo_fize;
  624. };
  625. union radeon_asic_config {
  626. struct r300_asic r300;
  627. struct r100_asic r100;
  628. struct r600_asic r600;
  629. struct rv770_asic rv770;
  630. };
  631. /*
  632. * IOCTL.
  633. */
  634. int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
  635. struct drm_file *filp);
  636. int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
  637. struct drm_file *filp);
  638. int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
  639. struct drm_file *file_priv);
  640. int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
  641. struct drm_file *file_priv);
  642. int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
  643. struct drm_file *file_priv);
  644. int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
  645. struct drm_file *file_priv);
  646. int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
  647. struct drm_file *filp);
  648. int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
  649. struct drm_file *filp);
  650. int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
  651. struct drm_file *filp);
  652. int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
  653. struct drm_file *filp);
  654. int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
  655. int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
  656. struct drm_file *filp);
  657. int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
  658. struct drm_file *filp);
  659. /*
  660. * Core structure, functions and helpers.
  661. */
  662. typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
  663. typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
  664. struct radeon_device {
  665. struct device *dev;
  666. struct drm_device *ddev;
  667. struct pci_dev *pdev;
  668. /* ASIC */
  669. union radeon_asic_config config;
  670. enum radeon_family family;
  671. unsigned long flags;
  672. int usec_timeout;
  673. enum radeon_pll_errata pll_errata;
  674. int num_gb_pipes;
  675. int num_z_pipes;
  676. int disp_priority;
  677. /* BIOS */
  678. uint8_t *bios;
  679. bool is_atom_bios;
  680. uint16_t bios_header_start;
  681. struct radeon_object *stollen_vga_memory;
  682. struct fb_info *fbdev_info;
  683. struct radeon_object *fbdev_robj;
  684. struct radeon_framebuffer *fbdev_rfb;
  685. /* Register mmio */
  686. resource_size_t rmmio_base;
  687. resource_size_t rmmio_size;
  688. void *rmmio;
  689. radeon_rreg_t mc_rreg;
  690. radeon_wreg_t mc_wreg;
  691. radeon_rreg_t pll_rreg;
  692. radeon_wreg_t pll_wreg;
  693. uint32_t pcie_reg_mask;
  694. radeon_rreg_t pciep_rreg;
  695. radeon_wreg_t pciep_wreg;
  696. struct radeon_clock clock;
  697. struct radeon_mc mc;
  698. struct radeon_gart gart;
  699. struct radeon_mode_info mode_info;
  700. struct radeon_scratch scratch;
  701. struct radeon_mman mman;
  702. struct radeon_fence_driver fence_drv;
  703. struct radeon_cp cp;
  704. struct radeon_ib_pool ib_pool;
  705. struct radeon_irq irq;
  706. struct radeon_asic *asic;
  707. struct radeon_gem gem;
  708. struct radeon_pm pm;
  709. uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
  710. struct mutex cs_mutex;
  711. struct radeon_wb wb;
  712. struct radeon_dummy_page dummy_page;
  713. bool gpu_lockup;
  714. bool shutdown;
  715. bool suspend;
  716. bool need_dma32;
  717. bool new_init_path;
  718. bool accel_working;
  719. struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
  720. const struct firmware *me_fw; /* all family ME firmware */
  721. const struct firmware *pfp_fw; /* r6/700 PFP firmware */
  722. struct r600_blit r600_blit;
  723. };
  724. int radeon_device_init(struct radeon_device *rdev,
  725. struct drm_device *ddev,
  726. struct pci_dev *pdev,
  727. uint32_t flags);
  728. void radeon_device_fini(struct radeon_device *rdev);
  729. int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
  730. /* r600 blit */
  731. int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
  732. void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
  733. void r600_kms_blit_copy(struct radeon_device *rdev,
  734. u64 src_gpu_addr, u64 dst_gpu_addr,
  735. int size_bytes);
  736. static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
  737. {
  738. if (reg < 0x10000)
  739. return readl(((void __iomem *)rdev->rmmio) + reg);
  740. else {
  741. writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  742. return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  743. }
  744. }
  745. static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  746. {
  747. if (reg < 0x10000)
  748. writel(v, ((void __iomem *)rdev->rmmio) + reg);
  749. else {
  750. writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  751. writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  752. }
  753. }
  754. /*
  755. * Registers read & write functions.
  756. */
  757. #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
  758. #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
  759. #define RREG32(reg) r100_mm_rreg(rdev, (reg))
  760. #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
  761. #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
  762. #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  763. #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  764. #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
  765. #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
  766. #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
  767. #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
  768. #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
  769. #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
  770. #define WREG32_P(reg, val, mask) \
  771. do { \
  772. uint32_t tmp_ = RREG32(reg); \
  773. tmp_ &= (mask); \
  774. tmp_ |= ((val) & ~(mask)); \
  775. WREG32(reg, tmp_); \
  776. } while (0)
  777. #define WREG32_PLL_P(reg, val, mask) \
  778. do { \
  779. uint32_t tmp_ = RREG32_PLL(reg); \
  780. tmp_ &= (mask); \
  781. tmp_ |= ((val) & ~(mask)); \
  782. WREG32_PLL(reg, tmp_); \
  783. } while (0)
  784. #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
  785. /*
  786. * Indirect registers accessor
  787. */
  788. static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
  789. {
  790. uint32_t r;
  791. WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  792. r = RREG32(RADEON_PCIE_DATA);
  793. return r;
  794. }
  795. static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  796. {
  797. WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  798. WREG32(RADEON_PCIE_DATA, (v));
  799. }
  800. void r100_pll_errata_after_index(struct radeon_device *rdev);
  801. /*
  802. * ASICs helpers.
  803. */
  804. #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
  805. (rdev->pdev->device == 0x5969))
  806. #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
  807. (rdev->family == CHIP_RV200) || \
  808. (rdev->family == CHIP_RS100) || \
  809. (rdev->family == CHIP_RS200) || \
  810. (rdev->family == CHIP_RV250) || \
  811. (rdev->family == CHIP_RV280) || \
  812. (rdev->family == CHIP_RS300))
  813. #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
  814. (rdev->family == CHIP_RV350) || \
  815. (rdev->family == CHIP_R350) || \
  816. (rdev->family == CHIP_RV380) || \
  817. (rdev->family == CHIP_R420) || \
  818. (rdev->family == CHIP_R423) || \
  819. (rdev->family == CHIP_RV410) || \
  820. (rdev->family == CHIP_RS400) || \
  821. (rdev->family == CHIP_RS480))
  822. #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
  823. #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
  824. #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
  825. /*
  826. * BIOS helpers.
  827. */
  828. #define RBIOS8(i) (rdev->bios[i])
  829. #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
  830. #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
  831. int radeon_combios_init(struct radeon_device *rdev);
  832. void radeon_combios_fini(struct radeon_device *rdev);
  833. int radeon_atombios_init(struct radeon_device *rdev);
  834. void radeon_atombios_fini(struct radeon_device *rdev);
  835. /*
  836. * RING helpers.
  837. */
  838. static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
  839. {
  840. #if DRM_DEBUG_CODE
  841. if (rdev->cp.count_dw <= 0) {
  842. DRM_ERROR("radeon: writting more dword to ring than expected !\n");
  843. }
  844. #endif
  845. rdev->cp.ring[rdev->cp.wptr++] = v;
  846. rdev->cp.wptr &= rdev->cp.ptr_mask;
  847. rdev->cp.count_dw--;
  848. rdev->cp.ring_free_dw--;
  849. }
  850. /*
  851. * ASICs macro.
  852. */
  853. #define radeon_init(rdev) (rdev)->asic->init((rdev))
  854. #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
  855. #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
  856. #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
  857. #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
  858. #define radeon_errata(rdev) (rdev)->asic->errata((rdev))
  859. #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
  860. #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
  861. #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
  862. #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
  863. #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
  864. #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
  865. #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
  866. #define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev))
  867. #define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev))
  868. #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
  869. #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
  870. #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
  871. #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
  872. #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
  873. #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
  874. #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
  875. #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
  876. #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
  877. #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
  878. #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
  879. #define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev))
  880. #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
  881. #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
  882. #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
  883. #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
  884. #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
  885. #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
  886. #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
  887. #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
  888. #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
  889. #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
  890. #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
  891. #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
  892. #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
  893. #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
  894. /* Common functions */
  895. extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
  896. extern int radeon_modeset_init(struct radeon_device *rdev);
  897. extern void radeon_modeset_fini(struct radeon_device *rdev);
  898. extern bool radeon_card_posted(struct radeon_device *rdev);
  899. extern int radeon_clocks_init(struct radeon_device *rdev);
  900. extern void radeon_clocks_fini(struct radeon_device *rdev);
  901. extern void radeon_scratch_init(struct radeon_device *rdev);
  902. extern void radeon_surface_init(struct radeon_device *rdev);
  903. extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
  904. /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
  905. struct r100_mc_save {
  906. u32 GENMO_WT;
  907. u32 CRTC_EXT_CNTL;
  908. u32 CRTC_GEN_CNTL;
  909. u32 CRTC2_GEN_CNTL;
  910. u32 CUR_OFFSET;
  911. u32 CUR2_OFFSET;
  912. };
  913. extern void r100_cp_disable(struct radeon_device *rdev);
  914. extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  915. extern void r100_cp_fini(struct radeon_device *rdev);
  916. extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  917. extern int r100_pci_gart_init(struct radeon_device *rdev);
  918. extern void r100_pci_gart_fini(struct radeon_device *rdev);
  919. extern int r100_pci_gart_enable(struct radeon_device *rdev);
  920. extern void r100_pci_gart_disable(struct radeon_device *rdev);
  921. extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
  922. extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
  923. extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
  924. extern void r100_ib_fini(struct radeon_device *rdev);
  925. extern int r100_ib_init(struct radeon_device *rdev);
  926. extern void r100_irq_disable(struct radeon_device *rdev);
  927. extern int r100_irq_set(struct radeon_device *rdev);
  928. extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
  929. extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
  930. extern void r100_vram_init_sizes(struct radeon_device *rdev);
  931. extern void r100_wb_disable(struct radeon_device *rdev);
  932. extern void r100_wb_fini(struct radeon_device *rdev);
  933. extern int r100_wb_init(struct radeon_device *rdev);
  934. /* r300,r350,rv350,rv370,rv380 */
  935. extern void r300_set_reg_safe(struct radeon_device *rdev);
  936. extern void r300_mc_program(struct radeon_device *rdev);
  937. extern void r300_vram_info(struct radeon_device *rdev);
  938. extern int rv370_pcie_gart_init(struct radeon_device *rdev);
  939. extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
  940. extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
  941. extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
  942. /* r420,r423,rv410 */
  943. extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
  944. extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
  945. extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
  946. /* rv515 */
  947. extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
  948. /* rs690, rs740 */
  949. extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
  950. struct drm_display_mode *mode1,
  951. struct drm_display_mode *mode2);
  952. /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
  953. extern bool r600_card_posted(struct radeon_device *rdev);
  954. extern void r600_cp_stop(struct radeon_device *rdev);
  955. extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
  956. extern int r600_cp_resume(struct radeon_device *rdev);
  957. extern int r600_count_pipe_bits(uint32_t val);
  958. extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
  959. extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
  960. extern int r600_pcie_gart_init(struct radeon_device *rdev);
  961. extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
  962. extern int r600_ib_test(struct radeon_device *rdev);
  963. extern int r600_ring_test(struct radeon_device *rdev);
  964. extern int r600_wb_init(struct radeon_device *rdev);
  965. extern void r600_wb_fini(struct radeon_device *rdev);
  966. extern void r600_scratch_init(struct radeon_device *rdev);
  967. extern int r600_blit_init(struct radeon_device *rdev);
  968. extern void r600_blit_fini(struct radeon_device *rdev);
  969. extern int r600_cp_init_microcode(struct radeon_device *rdev);
  970. extern int r600_gpu_reset(struct radeon_device *rdev);
  971. #endif