Kconfig 3.5 KB

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  1. #
  2. # DMA engine configuration
  3. #
  4. menuconfig DMADEVICES
  5. bool "DMA Engine support"
  6. depends on HAS_DMA
  7. help
  8. DMA engines can do asynchronous data transfers without
  9. involving the host CPU. Currently, this framework can be
  10. used to offload memory copies in the network stack and
  11. RAID operations in the MD driver. This menu only presents
  12. DMA Device drivers supported by the configured arch, it may
  13. be empty in some cases.
  14. if DMADEVICES
  15. comment "DMA Devices"
  16. config INTEL_IOATDMA
  17. tristate "Intel I/OAT DMA support"
  18. depends on PCI && X86
  19. select DMA_ENGINE
  20. select DCA
  21. help
  22. Enable support for the Intel(R) I/OAT DMA engine present
  23. in recent Intel Xeon chipsets.
  24. Say Y here if you have such a chipset.
  25. If unsure, say N.
  26. config INTEL_IOP_ADMA
  27. tristate "Intel IOP ADMA support"
  28. depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
  29. select DMA_ENGINE
  30. help
  31. Enable support for the Intel(R) IOP Series RAID engines.
  32. config DW_DMAC
  33. tristate "Synopsys DesignWare AHB DMA support"
  34. depends on AVR32
  35. select DMA_ENGINE
  36. default y if CPU_AT32AP7000
  37. help
  38. Support the Synopsys DesignWare AHB DMA controller. This
  39. can be integrated in chips such as the Atmel AT32ap7000.
  40. config AT_HDMAC
  41. tristate "Atmel AHB DMA support"
  42. depends on ARCH_AT91SAM9RL
  43. select DMA_ENGINE
  44. help
  45. Support the Atmel AHB DMA controller. This can be integrated in
  46. chips such as the Atmel AT91SAM9RL.
  47. config FSL_DMA
  48. tristate "Freescale Elo and Elo Plus DMA support"
  49. depends on FSL_SOC
  50. select DMA_ENGINE
  51. ---help---
  52. Enable support for the Freescale Elo and Elo Plus DMA controllers.
  53. The Elo is the DMA controller on some 82xx and 83xx parts, and the
  54. Elo Plus is the DMA controller on 85xx and 86xx parts.
  55. config MV_XOR
  56. bool "Marvell XOR engine support"
  57. depends on PLAT_ORION
  58. select DMA_ENGINE
  59. ---help---
  60. Enable support for the Marvell XOR engine.
  61. config MX3_IPU
  62. bool "MX3x Image Processing Unit support"
  63. depends on ARCH_MX3
  64. select DMA_ENGINE
  65. default y
  66. help
  67. If you plan to use the Image Processing unit in the i.MX3x, say
  68. Y here. If unsure, select Y.
  69. config MX3_IPU_IRQS
  70. int "Number of dynamically mapped interrupts for IPU"
  71. depends on MX3_IPU
  72. range 2 137
  73. default 4
  74. help
  75. Out of 137 interrupt sources on i.MX31 IPU only very few are used.
  76. To avoid bloating the irq_desc[] array we allocate a sufficient
  77. number of IRQ slots and map them dynamically to specific sources.
  78. config TXX9_DMAC
  79. tristate "Toshiba TXx9 SoC DMA support"
  80. depends on MACH_TX49XX || MACH_TX39XX
  81. select DMA_ENGINE
  82. help
  83. Support the TXx9 SoC internal DMA controller. This can be
  84. integrated in chips such as the Toshiba TX4927/38/39.
  85. config DMA_ENGINE
  86. bool
  87. comment "DMA Clients"
  88. depends on DMA_ENGINE
  89. config NET_DMA
  90. bool "Network: TCP receive copy offload"
  91. depends on DMA_ENGINE && NET
  92. default (INTEL_IOATDMA || FSL_DMA)
  93. help
  94. This enables the use of DMA engines in the network stack to
  95. offload receive copy-to-user operations, freeing CPU cycles.
  96. Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
  97. say N.
  98. config ASYNC_TX_DMA
  99. bool "Async_tx: Offload support for the async_tx api"
  100. depends on DMA_ENGINE && !HIGHMEM64G
  101. help
  102. This allows the async_tx api to take advantage of offload engines for
  103. memcpy, memset, xor, and raid6 p+q operations. If your platform has
  104. a dma engine that can perform raid operations and you have enabled
  105. MD_RAID456 say Y.
  106. If unsure, say N.
  107. config DMATEST
  108. tristate "DMA Test client"
  109. depends on DMA_ENGINE
  110. help
  111. Simple DMA test client. Say N unless you're debugging a
  112. DMA Device driver.
  113. endif