ezbrd.c 19 KB

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  1. /*
  2. * File: arch/blackfin/mach-bf527/boards/ezbrd.c
  3. * Based on: arch/blackfin/mach-bf537/boards/stamp.c
  4. * Author: Aidan Williams <aidan@nicta.com.au>
  5. *
  6. * Created:
  7. * Description:
  8. *
  9. * Modified:
  10. * Copyright 2005 National ICT Australia (NICTA)
  11. * Copyright 2004-2008 Analog Devices Inc.
  12. *
  13. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, see the file COPYING, or write
  27. * to the Free Software Foundation, Inc.,
  28. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  29. */
  30. #include <linux/device.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/mtd/mtd.h>
  33. #include <linux/mtd/partitions.h>
  34. #include <linux/mtd/physmap.h>
  35. #include <linux/spi/spi.h>
  36. #include <linux/spi/flash.h>
  37. #include <linux/i2c.h>
  38. #include <linux/irq.h>
  39. #include <linux/interrupt.h>
  40. #include <linux/usb/musb.h>
  41. #include <asm/dma.h>
  42. #include <asm/bfin5xx_spi.h>
  43. #include <asm/reboot.h>
  44. #include <asm/nand.h>
  45. #include <asm/portmux.h>
  46. #include <asm/dpmc.h>
  47. #include <linux/spi/ad7877.h>
  48. /*
  49. * Name the Board for the /proc/cpuinfo
  50. */
  51. const char bfin_board_name[] = "ADI BF526-EZBRD";
  52. /*
  53. * Driver needs to know address, irq and flag pin.
  54. */
  55. #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
  56. static struct resource musb_resources[] = {
  57. [0] = {
  58. .start = 0xffc03800,
  59. .end = 0xffc03cff,
  60. .flags = IORESOURCE_MEM,
  61. },
  62. [1] = { /* general IRQ */
  63. .start = IRQ_USB_INT0,
  64. .end = IRQ_USB_INT0,
  65. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  66. },
  67. [2] = { /* DMA IRQ */
  68. .start = IRQ_USB_DMA,
  69. .end = IRQ_USB_DMA,
  70. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  71. },
  72. };
  73. static struct musb_hdrc_config musb_config = {
  74. .multipoint = 0,
  75. .dyn_fifo = 0,
  76. .soft_con = 1,
  77. .dma = 1,
  78. .num_eps = 8,
  79. .dma_channels = 8,
  80. .gpio_vrsel = GPIO_PG13,
  81. };
  82. static struct musb_hdrc_platform_data musb_plat = {
  83. #if defined(CONFIG_USB_MUSB_OTG)
  84. .mode = MUSB_OTG,
  85. #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
  86. .mode = MUSB_HOST,
  87. #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
  88. .mode = MUSB_PERIPHERAL,
  89. #endif
  90. .config = &musb_config,
  91. };
  92. static u64 musb_dmamask = ~(u32)0;
  93. static struct platform_device musb_device = {
  94. .name = "musb_hdrc",
  95. .id = 0,
  96. .dev = {
  97. .dma_mask = &musb_dmamask,
  98. .coherent_dma_mask = 0xffffffff,
  99. .platform_data = &musb_plat,
  100. },
  101. .num_resources = ARRAY_SIZE(musb_resources),
  102. .resource = musb_resources,
  103. };
  104. #endif
  105. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  106. static struct mtd_partition ezbrd_partitions[] = {
  107. {
  108. .name = "bootloader(nor)",
  109. .size = 0x40000,
  110. .offset = 0,
  111. }, {
  112. .name = "linux kernel(nor)",
  113. .size = 0x1C0000,
  114. .offset = MTDPART_OFS_APPEND,
  115. }, {
  116. .name = "file system(nor)",
  117. .size = MTDPART_SIZ_FULL,
  118. .offset = MTDPART_OFS_APPEND,
  119. }
  120. };
  121. static struct physmap_flash_data ezbrd_flash_data = {
  122. .width = 2,
  123. .parts = ezbrd_partitions,
  124. .nr_parts = ARRAY_SIZE(ezbrd_partitions),
  125. };
  126. static struct resource ezbrd_flash_resource = {
  127. .start = 0x20000000,
  128. .end = 0x203fffff,
  129. .flags = IORESOURCE_MEM,
  130. };
  131. static struct platform_device ezbrd_flash_device = {
  132. .name = "physmap-flash",
  133. .id = 0,
  134. .dev = {
  135. .platform_data = &ezbrd_flash_data,
  136. },
  137. .num_resources = 1,
  138. .resource = &ezbrd_flash_resource,
  139. };
  140. #endif
  141. #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
  142. static struct mtd_partition partition_info[] = {
  143. {
  144. .name = "linux kernel(nand)",
  145. .offset = 0,
  146. .size = 4 * 1024 * 1024,
  147. },
  148. {
  149. .name = "file system(nand)",
  150. .offset = MTDPART_OFS_APPEND,
  151. .size = MTDPART_SIZ_FULL,
  152. },
  153. };
  154. static struct bf5xx_nand_platform bf5xx_nand_platform = {
  155. .page_size = NFC_PG_SIZE_256,
  156. .data_width = NFC_NWIDTH_8,
  157. .partitions = partition_info,
  158. .nr_partitions = ARRAY_SIZE(partition_info),
  159. .rd_dly = 3,
  160. .wr_dly = 3,
  161. };
  162. static struct resource bf5xx_nand_resources[] = {
  163. {
  164. .start = NFC_CTL,
  165. .end = NFC_DATA_RD + 2,
  166. .flags = IORESOURCE_MEM,
  167. },
  168. {
  169. .start = CH_NFC,
  170. .end = CH_NFC,
  171. .flags = IORESOURCE_IRQ,
  172. },
  173. };
  174. static struct platform_device bf5xx_nand_device = {
  175. .name = "bf5xx-nand",
  176. .id = 0,
  177. .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
  178. .resource = bf5xx_nand_resources,
  179. .dev = {
  180. .platform_data = &bf5xx_nand_platform,
  181. },
  182. };
  183. #endif
  184. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  185. static struct platform_device rtc_device = {
  186. .name = "rtc-bfin",
  187. .id = -1,
  188. };
  189. #endif
  190. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  191. static struct platform_device bfin_mii_bus = {
  192. .name = "bfin_mii_bus",
  193. };
  194. static struct platform_device bfin_mac_device = {
  195. .name = "bfin_mac",
  196. .dev.platform_data = &bfin_mii_bus,
  197. };
  198. #endif
  199. #if defined(CONFIG_MTD_M25P80) \
  200. || defined(CONFIG_MTD_M25P80_MODULE)
  201. static struct mtd_partition bfin_spi_flash_partitions[] = {
  202. {
  203. .name = "bootloader(spi)",
  204. .size = 0x00040000,
  205. .offset = 0,
  206. .mask_flags = MTD_CAP_ROM
  207. }, {
  208. .name = "linux kernel(spi)",
  209. .size = MTDPART_SIZ_FULL,
  210. .offset = MTDPART_OFS_APPEND,
  211. }
  212. };
  213. static struct flash_platform_data bfin_spi_flash_data = {
  214. .name = "m25p80",
  215. .parts = bfin_spi_flash_partitions,
  216. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  217. .type = "sst25wf040",
  218. };
  219. /* SPI flash chip (sst25wf040) */
  220. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  221. .enable_dma = 0, /* use dma transfer with this chip*/
  222. .bits_per_word = 8,
  223. };
  224. #endif
  225. #if defined(CONFIG_BFIN_SPI_ADC) \
  226. || defined(CONFIG_BFIN_SPI_ADC_MODULE)
  227. /* SPI ADC chip */
  228. static struct bfin5xx_spi_chip spi_adc_chip_info = {
  229. .enable_dma = 1, /* use dma transfer with this chip*/
  230. .bits_per_word = 16,
  231. };
  232. #endif
  233. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  234. static struct bfin5xx_spi_chip mmc_spi_chip_info = {
  235. .enable_dma = 0,
  236. .bits_per_word = 8,
  237. };
  238. #endif
  239. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  240. static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
  241. .enable_dma = 0,
  242. .bits_per_word = 16,
  243. };
  244. static const struct ad7877_platform_data bfin_ad7877_ts_info = {
  245. .model = 7877,
  246. .vref_delay_usecs = 50, /* internal, no capacitor */
  247. .x_plate_ohms = 419,
  248. .y_plate_ohms = 486,
  249. .pressure_max = 1000,
  250. .pressure_min = 0,
  251. .stopacq_polarity = 1,
  252. .first_conversion_delay = 3,
  253. .acquisition_time = 1,
  254. .averaging = 1,
  255. .pen_down_acc_interval = 1,
  256. };
  257. #endif
  258. #if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
  259. #include <linux/spi/ad7879.h>
  260. static const struct ad7879_platform_data bfin_ad7879_ts_info = {
  261. .model = 7879, /* Model = AD7879 */
  262. .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
  263. .pressure_max = 10000,
  264. .pressure_min = 0,
  265. .first_conversion_delay = 3, /* wait 512us before do a first conversion */
  266. .acquisition_time = 1, /* 4us acquisition time per sample */
  267. .median = 2, /* do 8 measurements */
  268. .averaging = 1, /* take the average of 4 middle samples */
  269. .pen_down_acc_interval = 255, /* 9.4 ms */
  270. .gpio_output = 1, /* configure AUX/VBAT/GPIO as GPIO output */
  271. .gpio_default = 1, /* During initialization set GPIO = HIGH */
  272. };
  273. #endif
  274. #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
  275. static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
  276. .enable_dma = 0,
  277. .bits_per_word = 16,
  278. };
  279. #endif
  280. #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
  281. && defined(CONFIG_SND_SOC_WM8731_SPI)
  282. static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
  283. .enable_dma = 0,
  284. .bits_per_word = 16,
  285. };
  286. #endif
  287. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  288. static struct bfin5xx_spi_chip spidev_chip_info = {
  289. .enable_dma = 0,
  290. .bits_per_word = 8,
  291. };
  292. #endif
  293. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  294. static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
  295. .enable_dma = 0,
  296. .bits_per_word = 8,
  297. };
  298. #endif
  299. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  300. #if defined(CONFIG_MTD_M25P80) \
  301. || defined(CONFIG_MTD_M25P80_MODULE)
  302. {
  303. /* the modalias must be the same as spi device driver name */
  304. .modalias = "m25p80", /* Name of spi_driver for this device */
  305. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  306. .bus_num = 0, /* Framework bus number */
  307. .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
  308. .platform_data = &bfin_spi_flash_data,
  309. .controller_data = &spi_flash_chip_info,
  310. .mode = SPI_MODE_3,
  311. },
  312. #endif
  313. #if defined(CONFIG_BFIN_SPI_ADC) \
  314. || defined(CONFIG_BFIN_SPI_ADC_MODULE)
  315. {
  316. .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
  317. .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
  318. .bus_num = 0, /* Framework bus number */
  319. .chip_select = 1, /* Framework chip select. */
  320. .platform_data = NULL, /* No spi_driver specific config */
  321. .controller_data = &spi_adc_chip_info,
  322. },
  323. #endif
  324. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  325. {
  326. .modalias = "mmc_spi",
  327. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  328. .bus_num = 0,
  329. .chip_select = 5,
  330. .controller_data = &mmc_spi_chip_info,
  331. .mode = SPI_MODE_3,
  332. },
  333. #endif
  334. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  335. {
  336. .modalias = "ad7877",
  337. .platform_data = &bfin_ad7877_ts_info,
  338. .irq = IRQ_PF8,
  339. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  340. .bus_num = 0,
  341. .chip_select = 2,
  342. .controller_data = &spi_ad7877_chip_info,
  343. },
  344. #endif
  345. #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
  346. {
  347. .modalias = "ad7879",
  348. .platform_data = &bfin_ad7879_ts_info,
  349. .irq = IRQ_PG0,
  350. .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
  351. .bus_num = 0,
  352. .chip_select = 5,
  353. .controller_data = &spi_ad7879_chip_info,
  354. .mode = SPI_CPHA | SPI_CPOL,
  355. },
  356. #endif
  357. #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
  358. && defined(CONFIG_SND_SOC_WM8731_SPI)
  359. {
  360. .modalias = "wm8731",
  361. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  362. .bus_num = 0,
  363. .chip_select = 5,
  364. .controller_data = &spi_wm8731_chip_info,
  365. .mode = SPI_MODE_0,
  366. },
  367. #endif
  368. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  369. {
  370. .modalias = "spidev",
  371. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  372. .bus_num = 0,
  373. .chip_select = 1,
  374. .controller_data = &spidev_chip_info,
  375. },
  376. #endif
  377. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  378. {
  379. .modalias = "bfin-lq035q1-spi",
  380. .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
  381. .bus_num = 0,
  382. .chip_select = 1,
  383. .controller_data = &lq035q1_spi_chip_info,
  384. .mode = SPI_CPHA | SPI_CPOL,
  385. },
  386. #endif
  387. };
  388. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  389. /* SPI controller data */
  390. static struct bfin5xx_spi_master bfin_spi0_info = {
  391. .num_chipselect = 8,
  392. .enable_dma = 1, /* master has the ability to do dma transfer */
  393. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  394. };
  395. /* SPI (0) */
  396. static struct resource bfin_spi0_resource[] = {
  397. [0] = {
  398. .start = SPI0_REGBASE,
  399. .end = SPI0_REGBASE + 0xFF,
  400. .flags = IORESOURCE_MEM,
  401. },
  402. [1] = {
  403. .start = CH_SPI,
  404. .end = CH_SPI,
  405. .flags = IORESOURCE_DMA,
  406. },
  407. [2] = {
  408. .start = IRQ_SPI,
  409. .end = IRQ_SPI,
  410. .flags = IORESOURCE_IRQ,
  411. },
  412. };
  413. static struct platform_device bfin_spi0_device = {
  414. .name = "bfin-spi",
  415. .id = 0, /* Bus number */
  416. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  417. .resource = bfin_spi0_resource,
  418. .dev = {
  419. .platform_data = &bfin_spi0_info, /* Passed to driver */
  420. },
  421. };
  422. #endif /* spi master and devices */
  423. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  424. static struct resource bfin_uart_resources[] = {
  425. #ifdef CONFIG_SERIAL_BFIN_UART0
  426. {
  427. .start = 0xFFC00400,
  428. .end = 0xFFC004FF,
  429. .flags = IORESOURCE_MEM,
  430. },
  431. #endif
  432. #ifdef CONFIG_SERIAL_BFIN_UART1
  433. {
  434. .start = 0xFFC02000,
  435. .end = 0xFFC020FF,
  436. .flags = IORESOURCE_MEM,
  437. },
  438. #endif
  439. };
  440. static struct platform_device bfin_uart_device = {
  441. .name = "bfin-uart",
  442. .id = 1,
  443. .num_resources = ARRAY_SIZE(bfin_uart_resources),
  444. .resource = bfin_uart_resources,
  445. };
  446. #endif
  447. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  448. #ifdef CONFIG_BFIN_SIR0
  449. static struct resource bfin_sir0_resources[] = {
  450. {
  451. .start = 0xFFC00400,
  452. .end = 0xFFC004FF,
  453. .flags = IORESOURCE_MEM,
  454. },
  455. {
  456. .start = IRQ_UART0_RX,
  457. .end = IRQ_UART0_RX+1,
  458. .flags = IORESOURCE_IRQ,
  459. },
  460. {
  461. .start = CH_UART0_RX,
  462. .end = CH_UART0_RX+1,
  463. .flags = IORESOURCE_DMA,
  464. },
  465. };
  466. static struct platform_device bfin_sir0_device = {
  467. .name = "bfin_sir",
  468. .id = 0,
  469. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  470. .resource = bfin_sir0_resources,
  471. };
  472. #endif
  473. #ifdef CONFIG_BFIN_SIR1
  474. static struct resource bfin_sir1_resources[] = {
  475. {
  476. .start = 0xFFC02000,
  477. .end = 0xFFC020FF,
  478. .flags = IORESOURCE_MEM,
  479. },
  480. {
  481. .start = IRQ_UART1_RX,
  482. .end = IRQ_UART1_RX+1,
  483. .flags = IORESOURCE_IRQ,
  484. },
  485. {
  486. .start = CH_UART1_RX,
  487. .end = CH_UART1_RX+1,
  488. .flags = IORESOURCE_DMA,
  489. },
  490. };
  491. static struct platform_device bfin_sir1_device = {
  492. .name = "bfin_sir",
  493. .id = 1,
  494. .num_resources = ARRAY_SIZE(bfin_sir1_resources),
  495. .resource = bfin_sir1_resources,
  496. };
  497. #endif
  498. #endif
  499. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  500. static struct resource bfin_twi0_resource[] = {
  501. [0] = {
  502. .start = TWI0_REGBASE,
  503. .end = TWI0_REGBASE,
  504. .flags = IORESOURCE_MEM,
  505. },
  506. [1] = {
  507. .start = IRQ_TWI,
  508. .end = IRQ_TWI,
  509. .flags = IORESOURCE_IRQ,
  510. },
  511. };
  512. static struct platform_device i2c_bfin_twi_device = {
  513. .name = "i2c-bfin-twi",
  514. .id = 0,
  515. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  516. .resource = bfin_twi0_resource,
  517. };
  518. #endif
  519. static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
  520. #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
  521. {
  522. I2C_BOARD_INFO("pcf8574_lcd", 0x22),
  523. },
  524. #endif
  525. #if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
  526. {
  527. I2C_BOARD_INFO("pcf8574_keypad", 0x27),
  528. .irq = IRQ_PF8,
  529. },
  530. #endif
  531. };
  532. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  533. static struct platform_device bfin_sport0_uart_device = {
  534. .name = "bfin-sport-uart",
  535. .id = 0,
  536. };
  537. static struct platform_device bfin_sport1_uart_device = {
  538. .name = "bfin-sport-uart",
  539. .id = 1,
  540. };
  541. #endif
  542. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  543. #include <linux/input.h>
  544. #include <linux/gpio_keys.h>
  545. static struct gpio_keys_button bfin_gpio_keys_table[] = {
  546. {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
  547. {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
  548. };
  549. static struct gpio_keys_platform_data bfin_gpio_keys_data = {
  550. .buttons = bfin_gpio_keys_table,
  551. .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
  552. };
  553. static struct platform_device bfin_device_gpiokeys = {
  554. .name = "gpio-keys",
  555. .dev = {
  556. .platform_data = &bfin_gpio_keys_data,
  557. },
  558. };
  559. #endif
  560. static struct resource bfin_gpios_resources = {
  561. .start = 0,
  562. .end = MAX_BLACKFIN_GPIOS - 1,
  563. .flags = IORESOURCE_IRQ,
  564. };
  565. static struct platform_device bfin_gpios_device = {
  566. .name = "simple-gpio",
  567. .id = -1,
  568. .num_resources = 1,
  569. .resource = &bfin_gpios_resources,
  570. };
  571. static const unsigned int cclk_vlev_datasheet[] =
  572. {
  573. VRPAIR(VLEV_100, 400000000),
  574. VRPAIR(VLEV_105, 426000000),
  575. VRPAIR(VLEV_110, 500000000),
  576. VRPAIR(VLEV_115, 533000000),
  577. VRPAIR(VLEV_120, 600000000),
  578. };
  579. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  580. .tuple_tab = cclk_vlev_datasheet,
  581. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  582. .vr_settling_time = 25 /* us */,
  583. };
  584. static struct platform_device bfin_dpmc = {
  585. .name = "bfin dpmc",
  586. .dev = {
  587. .platform_data = &bfin_dmpc_vreg_data,
  588. },
  589. };
  590. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  591. #include <asm/bfin-lq035q1.h>
  592. static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
  593. .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
  594. .use_bl = 1,
  595. .gpio_bl = GPIO_PG12,
  596. };
  597. static struct resource bfin_lq035q1_resources[] = {
  598. {
  599. .start = IRQ_PPI_ERROR,
  600. .end = IRQ_PPI_ERROR,
  601. .flags = IORESOURCE_IRQ,
  602. },
  603. };
  604. static struct platform_device bfin_lq035q1_device = {
  605. .name = "bfin-lq035q1",
  606. .id = -1,
  607. .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
  608. .resource = bfin_lq035q1_resources,
  609. .dev = {
  610. .platform_data = &bfin_lq035q1_data,
  611. },
  612. };
  613. #endif
  614. static struct platform_device *stamp_devices[] __initdata = {
  615. &bfin_dpmc,
  616. #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
  617. &bf5xx_nand_device,
  618. #endif
  619. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  620. &rtc_device,
  621. #endif
  622. #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
  623. &musb_device,
  624. #endif
  625. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  626. &bfin_mii_bus,
  627. &bfin_mac_device,
  628. #endif
  629. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  630. &bfin_spi0_device,
  631. #endif
  632. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  633. &bfin_uart_device,
  634. #endif
  635. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  636. &bfin_lq035q1_device,
  637. #endif
  638. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  639. #ifdef CONFIG_BFIN_SIR0
  640. &bfin_sir0_device,
  641. #endif
  642. #ifdef CONFIG_BFIN_SIR1
  643. &bfin_sir1_device,
  644. #endif
  645. #endif
  646. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  647. &i2c_bfin_twi_device,
  648. #endif
  649. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  650. &bfin_sport0_uart_device,
  651. &bfin_sport1_uart_device,
  652. #endif
  653. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  654. &bfin_device_gpiokeys,
  655. #endif
  656. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  657. &ezbrd_flash_device,
  658. #endif
  659. &bfin_gpios_device,
  660. };
  661. static int __init ezbrd_init(void)
  662. {
  663. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  664. i2c_register_board_info(0, bfin_i2c_board_info,
  665. ARRAY_SIZE(bfin_i2c_board_info));
  666. platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
  667. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  668. return 0;
  669. }
  670. arch_initcall(ezbrd_init);
  671. void native_machine_restart(char *cmd)
  672. {
  673. /* workaround reboot hang when booting from SPI */
  674. if ((bfin_read_SYSCR() & 0x7) == 0x3)
  675. bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
  676. }
  677. void bfin_get_ether_addr(char *addr)
  678. {
  679. /* the MAC is stored in OTP memory page 0xDF */
  680. u32 ret;
  681. u64 otp_mac;
  682. u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
  683. ret = otp_read(0xDF, 0x00, &otp_mac);
  684. if (!(ret & 0x1)) {
  685. char *otp_mac_p = (char *)&otp_mac;
  686. for (ret = 0; ret < 6; ++ret)
  687. addr[ret] = otp_mac_p[5 - ret];
  688. }
  689. }
  690. EXPORT_SYMBOL(bfin_get_ether_addr);