gpio.c 19 KB

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  1. /*
  2. *
  3. * arch/arm/mach-u300/gpio.c
  4. *
  5. *
  6. * Copyright (C) 2007-2009 ST-Ericsson AB
  7. * License terms: GNU General Public License (GPL) version 2
  8. * U300 GPIO module.
  9. * This can driver either of the two basic GPIO cores
  10. * available in the U300 platforms:
  11. * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
  12. * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
  13. * Notice that you also have inline macros in <asm-arch/gpio.h>
  14. * Author: Linus Walleij <linus.walleij@stericsson.com>
  15. * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
  16. *
  17. */
  18. #include <linux/module.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/delay.h>
  21. #include <linux/errno.h>
  22. #include <linux/io.h>
  23. #include <linux/clk.h>
  24. #include <linux/err.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/gpio.h>
  27. /* Need access to SYSCON registers for PADmuxing */
  28. #include <mach/syscon.h>
  29. #include "padmux.h"
  30. /* Reference to GPIO block clock */
  31. static struct clk *clk;
  32. /* Memory resource */
  33. static struct resource *memres;
  34. static void __iomem *virtbase;
  35. static struct device *gpiodev;
  36. struct u300_gpio_port {
  37. const char *name;
  38. int irq;
  39. int number;
  40. };
  41. static struct u300_gpio_port gpio_ports[] = {
  42. {
  43. .name = "gpio0",
  44. .number = 0,
  45. },
  46. {
  47. .name = "gpio1",
  48. .number = 1,
  49. },
  50. {
  51. .name = "gpio2",
  52. .number = 2,
  53. },
  54. #ifdef U300_COH901571_3
  55. {
  56. .name = "gpio3",
  57. .number = 3,
  58. },
  59. {
  60. .name = "gpio4",
  61. .number = 4,
  62. },
  63. #ifdef CONFIG_MACH_U300_BS335
  64. {
  65. .name = "gpio5",
  66. .number = 5,
  67. },
  68. {
  69. .name = "gpio6",
  70. .number = 6,
  71. },
  72. #endif
  73. #endif
  74. };
  75. #ifdef U300_COH901571_3
  76. /* Default input value */
  77. #define DEFAULT_OUTPUT_LOW 0
  78. #define DEFAULT_OUTPUT_HIGH 1
  79. /* GPIO Pull-Up status */
  80. #define DISABLE_PULL_UP 0
  81. #define ENABLE_PULL_UP 1
  82. #define GPIO_NOT_USED 0
  83. #define GPIO_IN 1
  84. #define GPIO_OUT 2
  85. struct u300_gpio_configuration_data {
  86. unsigned char pin_usage;
  87. unsigned char default_output_value;
  88. unsigned char pull_up;
  89. };
  90. /* Initial configuration */
  91. const struct u300_gpio_configuration_data
  92. u300_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
  93. #ifdef CONFIG_MACH_U300_BS335
  94. /* Port 0, pins 0-7 */
  95. {
  96. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  97. {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP},
  98. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  99. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  100. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  101. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  102. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  103. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
  104. },
  105. /* Port 1, pins 0-7 */
  106. {
  107. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  108. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  109. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  110. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  111. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  112. {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP},
  113. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  114. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
  115. },
  116. /* Port 2, pins 0-7 */
  117. {
  118. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  119. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  120. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  121. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  122. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  123. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  124. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  125. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
  126. },
  127. /* Port 3, pins 0-7 */
  128. {
  129. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  130. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  131. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  132. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  133. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  134. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  135. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  136. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
  137. },
  138. /* Port 4, pins 0-7 */
  139. {
  140. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  141. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  142. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  143. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  144. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  145. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  146. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  147. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
  148. },
  149. /* Port 5, pins 0-7 */
  150. {
  151. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  152. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  153. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  154. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  155. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  156. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  157. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  158. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
  159. },
  160. /* Port 6, pind 0-7 */
  161. {
  162. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  163. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  164. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  165. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  166. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  167. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  168. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  169. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
  170. }
  171. #endif
  172. #ifdef CONFIG_MACH_U300_BS365
  173. /* Port 0, pins 0-7 */
  174. {
  175. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  176. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  177. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  178. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  179. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  180. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  181. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  182. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
  183. },
  184. /* Port 1, pins 0-7 */
  185. {
  186. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  187. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  188. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  189. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  190. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  191. {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP},
  192. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  193. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
  194. },
  195. /* Port 2, pins 0-7 */
  196. {
  197. {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  198. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  199. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  200. {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
  201. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  202. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  203. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  204. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
  205. },
  206. /* Port 3, pins 0-7 */
  207. {
  208. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  209. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  210. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  211. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  212. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  213. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  214. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  215. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
  216. },
  217. /* Port 4, pins 0-7 */
  218. {
  219. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  220. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  221. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  222. {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  223. /* These 4 pins doesn't exist on DB3210 */
  224. {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  225. {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  226. {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
  227. {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
  228. }
  229. #endif
  230. };
  231. #endif
  232. /* No users == we can power down GPIO */
  233. static int gpio_users;
  234. struct gpio_struct {
  235. int (*callback)(void *);
  236. void *data;
  237. int users;
  238. };
  239. static struct gpio_struct gpio_pin[U300_GPIO_MAX];
  240. /*
  241. * Let drivers register callback in order to get notified when there is
  242. * an interrupt on the gpio pin
  243. */
  244. int gpio_register_callback(unsigned gpio, int (*func)(void *arg), void *data)
  245. {
  246. if (gpio_pin[gpio].callback)
  247. dev_warn(gpiodev, "%s: WARNING: callback already "
  248. "registered for gpio pin#%d\n", __func__, gpio);
  249. gpio_pin[gpio].callback = func;
  250. gpio_pin[gpio].data = data;
  251. return 0;
  252. }
  253. EXPORT_SYMBOL(gpio_register_callback);
  254. int gpio_unregister_callback(unsigned gpio)
  255. {
  256. if (!gpio_pin[gpio].callback)
  257. dev_warn(gpiodev, "%s: WARNING: callback already "
  258. "unregistered for gpio pin#%d\n", __func__, gpio);
  259. gpio_pin[gpio].callback = NULL;
  260. gpio_pin[gpio].data = NULL;
  261. return 0;
  262. }
  263. EXPORT_SYMBOL(gpio_unregister_callback);
  264. int gpio_request(unsigned gpio, const char *label)
  265. {
  266. if (gpio_pin[gpio].users)
  267. return -EINVAL;
  268. else
  269. gpio_pin[gpio].users++;
  270. gpio_users++;
  271. return 0;
  272. }
  273. EXPORT_SYMBOL(gpio_request);
  274. void gpio_free(unsigned gpio)
  275. {
  276. gpio_users--;
  277. gpio_pin[gpio].users--;
  278. if (unlikely(gpio_pin[gpio].users < 0)) {
  279. dev_warn(gpiodev, "warning: gpio#%d release mismatch\n",
  280. gpio);
  281. gpio_pin[gpio].users = 0;
  282. }
  283. return;
  284. }
  285. EXPORT_SYMBOL(gpio_free);
  286. /* This returns zero or nonzero */
  287. int gpio_get_value(unsigned gpio)
  288. {
  289. return readl(virtbase + U300_GPIO_PXPDIR +
  290. PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING) & (1 << (gpio & 0x07));
  291. }
  292. EXPORT_SYMBOL(gpio_get_value);
  293. /*
  294. * We hope that the compiler will optimize away the unused branch
  295. * in case "value" is a constant
  296. */
  297. void gpio_set_value(unsigned gpio, int value)
  298. {
  299. u32 val;
  300. unsigned long flags;
  301. local_irq_save(flags);
  302. if (value) {
  303. /* set */
  304. val = readl(virtbase + U300_GPIO_PXPDOR +
  305. PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING)
  306. & (1 << (gpio & 0x07));
  307. writel(val | (1 << (gpio & 0x07)), virtbase +
  308. U300_GPIO_PXPDOR +
  309. PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
  310. } else {
  311. /* clear */
  312. val = readl(virtbase + U300_GPIO_PXPDOR +
  313. PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING)
  314. & (1 << (gpio & 0x07));
  315. writel(val & ~(1 << (gpio & 0x07)), virtbase +
  316. U300_GPIO_PXPDOR +
  317. PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
  318. }
  319. local_irq_restore(flags);
  320. }
  321. EXPORT_SYMBOL(gpio_set_value);
  322. int gpio_direction_input(unsigned gpio)
  323. {
  324. unsigned long flags;
  325. u32 val;
  326. if (gpio > U300_GPIO_MAX)
  327. return -EINVAL;
  328. local_irq_save(flags);
  329. val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
  330. U300_GPIO_PORTX_SPACING);
  331. /* Mask out this pin*/
  332. val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1));
  333. /* This is not needed since it sets the bits to zero.*/
  334. /* val |= (U300_GPIO_PXPCR_PIN_MODE_INPUT << (gpio*2)); */
  335. writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
  336. U300_GPIO_PORTX_SPACING);
  337. local_irq_restore(flags);
  338. return 0;
  339. }
  340. EXPORT_SYMBOL(gpio_direction_input);
  341. int gpio_direction_output(unsigned gpio, int value)
  342. {
  343. unsigned long flags;
  344. u32 val;
  345. if (gpio > U300_GPIO_MAX)
  346. return -EINVAL;
  347. local_irq_save(flags);
  348. val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
  349. U300_GPIO_PORTX_SPACING);
  350. /* Mask out this pin */
  351. val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1));
  352. /*
  353. * FIXME: configure for push/pull, open drain or open source per pin
  354. * in setup. The current driver will only support push/pull.
  355. */
  356. val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
  357. << ((gpio & 0x07) << 1));
  358. writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
  359. U300_GPIO_PORTX_SPACING);
  360. gpio_set_value(gpio, value);
  361. local_irq_restore(flags);
  362. return 0;
  363. }
  364. EXPORT_SYMBOL(gpio_direction_output);
  365. /*
  366. * Enable an IRQ, edge is rising edge (!= 0) or falling edge (==0).
  367. */
  368. void enable_irq_on_gpio_pin(unsigned gpio, int edge)
  369. {
  370. u32 val;
  371. unsigned long flags;
  372. local_irq_save(flags);
  373. val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
  374. U300_GPIO_PORTX_SPACING);
  375. val |= (1 << (gpio & 0x07));
  376. writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
  377. U300_GPIO_PORTX_SPACING);
  378. val = readl(virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) *
  379. U300_GPIO_PORTX_SPACING);
  380. if (edge)
  381. val |= (1 << (gpio & 0x07));
  382. else
  383. val &= ~(1 << (gpio & 0x07));
  384. writel(val, virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) *
  385. U300_GPIO_PORTX_SPACING);
  386. local_irq_restore(flags);
  387. }
  388. EXPORT_SYMBOL(enable_irq_on_gpio_pin);
  389. void disable_irq_on_gpio_pin(unsigned gpio)
  390. {
  391. u32 val;
  392. unsigned long flags;
  393. local_irq_save(flags);
  394. val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
  395. U300_GPIO_PORTX_SPACING);
  396. val &= ~(1 << (gpio & 0x07));
  397. writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
  398. U300_GPIO_PORTX_SPACING);
  399. local_irq_restore(flags);
  400. }
  401. EXPORT_SYMBOL(disable_irq_on_gpio_pin);
  402. /* Enable (value == 0) or disable (value == 1) internal pullup */
  403. void gpio_pullup(unsigned gpio, int value)
  404. {
  405. u32 val;
  406. unsigned long flags;
  407. local_irq_save(flags);
  408. if (value) {
  409. val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) *
  410. U300_GPIO_PORTX_SPACING);
  411. writel(val | (1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
  412. PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
  413. } else {
  414. val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) *
  415. U300_GPIO_PORTX_SPACING);
  416. writel(val & ~(1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
  417. PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
  418. }
  419. local_irq_restore(flags);
  420. }
  421. EXPORT_SYMBOL(gpio_pullup);
  422. static irqreturn_t gpio_irq_handler(int irq, void *dev_id)
  423. {
  424. struct u300_gpio_port *port = dev_id;
  425. u32 val;
  426. int pin;
  427. /* Read event register */
  428. val = readl(virtbase + U300_GPIO_PXIEV + port->number *
  429. U300_GPIO_PORTX_SPACING);
  430. /* Mask with enable register */
  431. val &= readl(virtbase + U300_GPIO_PXIEV + port->number *
  432. U300_GPIO_PORTX_SPACING);
  433. /* Mask relevant bits */
  434. val &= U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK;
  435. /* ACK IRQ (clear event) */
  436. writel(val, virtbase + U300_GPIO_PXIEV + port->number *
  437. U300_GPIO_PORTX_SPACING);
  438. /* Print message */
  439. while (val != 0) {
  440. unsigned gpio;
  441. pin = __ffs(val);
  442. /* mask off this pin */
  443. val &= ~(1 << pin);
  444. gpio = (port->number << 3) + pin;
  445. if (gpio_pin[gpio].callback)
  446. (void)gpio_pin[gpio].callback(gpio_pin[gpio].data);
  447. else
  448. dev_dbg(gpiodev, "stray GPIO IRQ on line %d\n",
  449. gpio);
  450. }
  451. return IRQ_HANDLED;
  452. }
  453. static void gpio_set_initial_values(void)
  454. {
  455. #ifdef U300_COH901571_3
  456. int i, j;
  457. unsigned long flags;
  458. u32 val;
  459. /* Write default values to all pins */
  460. for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
  461. val = 0;
  462. for (j = 0; j < 8; j++)
  463. val |= (u32) (u300_gpio_config[i][j].default_output_value != DEFAULT_OUTPUT_LOW) << j;
  464. local_irq_save(flags);
  465. writel(val, virtbase + U300_GPIO_PXPDOR + i * U300_GPIO_PORTX_SPACING);
  466. local_irq_restore(flags);
  467. }
  468. /*
  469. * Put all pins that are set to either 'GPIO_OUT' or 'GPIO_NOT_USED'
  470. * to output and 'GPIO_IN' to input for each port. And initalize
  471. * default value on outputs.
  472. */
  473. for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
  474. for (j = 0; j < U300_GPIO_PINS_PER_PORT; j++) {
  475. local_irq_save(flags);
  476. val = readl(virtbase + U300_GPIO_PXPCR +
  477. i * U300_GPIO_PORTX_SPACING);
  478. /* Mask out this pin */
  479. val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << (j << 1));
  480. if (u300_gpio_config[i][j].pin_usage != GPIO_IN)
  481. val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL << (j << 1));
  482. writel(val, virtbase + U300_GPIO_PXPCR +
  483. i * U300_GPIO_PORTX_SPACING);
  484. local_irq_restore(flags);
  485. }
  486. }
  487. /* Enable or disable the internal pull-ups in the GPIO ASIC block */
  488. for (i = 0; i < U300_GPIO_MAX; i++) {
  489. val = 0;
  490. for (j = 0; j < 8; j++)
  491. val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP)) << j;
  492. local_irq_save(flags);
  493. writel(val, virtbase + U300_GPIO_PXPER + i * U300_GPIO_PORTX_SPACING);
  494. local_irq_restore(flags);
  495. }
  496. #endif
  497. }
  498. static int __init gpio_probe(struct platform_device *pdev)
  499. {
  500. u32 val;
  501. int err = 0;
  502. int i;
  503. int num_irqs;
  504. gpiodev = &pdev->dev;
  505. memset(gpio_pin, 0, sizeof(gpio_pin));
  506. /* Get GPIO clock */
  507. clk = clk_get(&pdev->dev, NULL);
  508. if (IS_ERR(clk)) {
  509. err = PTR_ERR(clk);
  510. dev_err(gpiodev, "could not get GPIO clock\n");
  511. goto err_no_clk;
  512. }
  513. err = clk_enable(clk);
  514. if (err) {
  515. dev_err(gpiodev, "could not enable GPIO clock\n");
  516. goto err_no_clk_enable;
  517. }
  518. memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  519. if (!memres)
  520. goto err_no_resource;
  521. if (request_mem_region(memres->start, memres->end - memres->start, "GPIO Controller")
  522. == NULL) {
  523. err = -ENODEV;
  524. goto err_no_ioregion;
  525. }
  526. virtbase = ioremap(memres->start, resource_size(memres));
  527. if (!virtbase) {
  528. err = -ENOMEM;
  529. goto err_no_ioremap;
  530. }
  531. dev_info(gpiodev, "remapped 0x%08x to %p\n",
  532. memres->start, virtbase);
  533. #ifdef U300_COH901335
  534. dev_info(gpiodev, "initializing GPIO Controller COH 901 335\n");
  535. /* Turn on the GPIO block */
  536. writel(U300_GPIO_CR_BLOCK_CLOCK_ENABLE, virtbase + U300_GPIO_CR);
  537. #endif
  538. #ifdef U300_COH901571_3
  539. dev_info(gpiodev, "initializing GPIO Controller COH 901 571/3\n");
  540. val = readl(virtbase + U300_GPIO_CR);
  541. dev_info(gpiodev, "COH901571/3 block version: %d, " \
  542. "number of cores: %d\n",
  543. ((val & 0x0000FE00) >> 9),
  544. ((val & 0x000001FC) >> 2));
  545. writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, virtbase + U300_GPIO_CR);
  546. #endif
  547. /* Set up some padmuxing here */
  548. #ifdef CONFIG_MMC
  549. pmx_set_mission_mode_mmc();
  550. #endif
  551. #ifdef CONFIG_SPI_PL022
  552. pmx_set_mission_mode_spi();
  553. #endif
  554. gpio_set_initial_values();
  555. for (num_irqs = 0 ; num_irqs < U300_GPIO_NUM_PORTS; num_irqs++) {
  556. gpio_ports[num_irqs].irq =
  557. platform_get_irq_byname(pdev,
  558. gpio_ports[num_irqs].name);
  559. err = request_irq(gpio_ports[num_irqs].irq,
  560. gpio_irq_handler, IRQF_DISABLED,
  561. gpio_ports[num_irqs].name,
  562. &gpio_ports[num_irqs]);
  563. if (err) {
  564. dev_err(gpiodev, "cannot allocate IRQ for %s!\n",
  565. gpio_ports[num_irqs].name);
  566. goto err_no_irq;
  567. }
  568. /* Turns off PortX_irq_force */
  569. writel(0x0, virtbase + U300_GPIO_PXIFR +
  570. num_irqs * U300_GPIO_PORTX_SPACING);
  571. }
  572. return 0;
  573. err_no_irq:
  574. for (i = 0; i < num_irqs; i++)
  575. free_irq(gpio_ports[i].irq, &gpio_ports[i]);
  576. iounmap(virtbase);
  577. err_no_ioremap:
  578. release_mem_region(memres->start, memres->end - memres->start);
  579. err_no_ioregion:
  580. err_no_resource:
  581. clk_disable(clk);
  582. err_no_clk_enable:
  583. clk_put(clk);
  584. err_no_clk:
  585. dev_info(gpiodev, "module ERROR:%d\n", err);
  586. return err;
  587. }
  588. static int __exit gpio_remove(struct platform_device *pdev)
  589. {
  590. int i;
  591. /* Turn off the GPIO block */
  592. writel(0x00000000U, virtbase + U300_GPIO_CR);
  593. for (i = 0 ; i < U300_GPIO_NUM_PORTS; i++)
  594. free_irq(gpio_ports[i].irq, &gpio_ports[i]);
  595. iounmap(virtbase);
  596. release_mem_region(memres->start, memres->end - memres->start);
  597. clk_disable(clk);
  598. clk_put(clk);
  599. return 0;
  600. }
  601. static struct platform_driver gpio_driver = {
  602. .driver = {
  603. .name = "u300-gpio",
  604. },
  605. .remove = __exit_p(gpio_remove),
  606. };
  607. static int __init u300_gpio_init(void)
  608. {
  609. return platform_driver_probe(&gpio_driver, gpio_probe);
  610. }
  611. static void __exit u300_gpio_exit(void)
  612. {
  613. platform_driver_unregister(&gpio_driver);
  614. }
  615. arch_initcall(u300_gpio_init);
  616. module_exit(u300_gpio_exit);
  617. MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
  618. #ifdef U300_COH901571_3
  619. MODULE_DESCRIPTION("ST-Ericsson AB COH 901 571/3 GPIO driver");
  620. #endif
  621. #ifdef U300_COH901335
  622. MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335 GPIO driver");
  623. #endif
  624. MODULE_LICENSE("GPL");