at91sam9n12.dtsi 15 KB

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  1. /*
  2. * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
  3. *
  4. * Copyright (C) 2012 Atmel,
  5. * 2012 Hong Xu <hong.xu@atmel.com>
  6. *
  7. * Licensed under GPLv2 or later.
  8. */
  9. #include "skeleton.dtsi"
  10. #include <dt-bindings/pinctrl/at91.h>
  11. #include <dt-bindings/interrupt-controller/irq.h>
  12. #include <dt-bindings/gpio/gpio.h>
  13. / {
  14. model = "Atmel AT91SAM9N12 SoC";
  15. compatible = "atmel,at91sam9n12";
  16. interrupt-parent = <&aic>;
  17. aliases {
  18. serial0 = &dbgu;
  19. serial1 = &usart0;
  20. serial2 = &usart1;
  21. serial3 = &usart2;
  22. serial4 = &usart3;
  23. gpio0 = &pioA;
  24. gpio1 = &pioB;
  25. gpio2 = &pioC;
  26. gpio3 = &pioD;
  27. tcb0 = &tcb0;
  28. tcb1 = &tcb1;
  29. i2c0 = &i2c0;
  30. i2c1 = &i2c1;
  31. ssc0 = &ssc0;
  32. };
  33. cpus {
  34. cpu@0 {
  35. compatible = "arm,arm926ejs";
  36. };
  37. };
  38. memory {
  39. reg = <0x20000000 0x10000000>;
  40. };
  41. ahb {
  42. compatible = "simple-bus";
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. ranges;
  46. apb {
  47. compatible = "simple-bus";
  48. #address-cells = <1>;
  49. #size-cells = <1>;
  50. ranges;
  51. aic: interrupt-controller@fffff000 {
  52. #interrupt-cells = <3>;
  53. compatible = "atmel,at91rm9200-aic";
  54. interrupt-controller;
  55. reg = <0xfffff000 0x200>;
  56. };
  57. ramc0: ramc@ffffe800 {
  58. compatible = "atmel,at91sam9g45-ddramc";
  59. reg = <0xffffe800 0x200>;
  60. };
  61. pmc: pmc@fffffc00 {
  62. compatible = "atmel,at91rm9200-pmc";
  63. reg = <0xfffffc00 0x100>;
  64. };
  65. rstc@fffffe00 {
  66. compatible = "atmel,at91sam9g45-rstc";
  67. reg = <0xfffffe00 0x10>;
  68. };
  69. pit: timer@fffffe30 {
  70. compatible = "atmel,at91sam9260-pit";
  71. reg = <0xfffffe30 0xf>;
  72. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  73. };
  74. shdwc@fffffe10 {
  75. compatible = "atmel,at91sam9x5-shdwc";
  76. reg = <0xfffffe10 0x10>;
  77. };
  78. mmc0: mmc@f0008000 {
  79. compatible = "atmel,hsmci";
  80. reg = <0xf0008000 0x600>;
  81. interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
  82. dmas = <&dma 1 0>;
  83. dma-names = "rxtx";
  84. #address-cells = <1>;
  85. #size-cells = <0>;
  86. status = "disabled";
  87. };
  88. tcb0: timer@f8008000 {
  89. compatible = "atmel,at91sam9x5-tcb";
  90. reg = <0xf8008000 0x100>;
  91. interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
  92. };
  93. tcb1: timer@f800c000 {
  94. compatible = "atmel,at91sam9x5-tcb";
  95. reg = <0xf800c000 0x100>;
  96. interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
  97. };
  98. dma: dma-controller@ffffec00 {
  99. compatible = "atmel,at91sam9g45-dma";
  100. reg = <0xffffec00 0x200>;
  101. interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
  102. #dma-cells = <2>;
  103. };
  104. pinctrl@fffff400 {
  105. #address-cells = <1>;
  106. #size-cells = <1>;
  107. compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
  108. ranges = <0xfffff400 0xfffff400 0x800>;
  109. atmel,mux-mask = <
  110. /* A B C */
  111. 0xffffffff 0xffe07983 0x00000000 /* pioA */
  112. 0x00040000 0x00047e0f 0x00000000 /* pioB */
  113. 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
  114. 0x003fffff 0x003f8000 0x00000000 /* pioD */
  115. >;
  116. /* shared pinctrl settings */
  117. dbgu {
  118. pinctrl_dbgu: dbgu-0 {
  119. atmel,pins =
  120. <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
  121. AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */
  122. };
  123. };
  124. usart0 {
  125. pinctrl_usart0: usart0-0 {
  126. atmel,pins =
  127. <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
  128. AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */
  129. };
  130. pinctrl_usart0_rts: usart0_rts-0 {
  131. atmel,pins =
  132. <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */
  133. };
  134. pinctrl_usart0_cts: usart0_cts-0 {
  135. atmel,pins =
  136. <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */
  137. };
  138. };
  139. usart1 {
  140. pinctrl_usart1: usart1-0 {
  141. atmel,pins =
  142. <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
  143. AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */
  144. };
  145. };
  146. usart2 {
  147. pinctrl_usart2: usart2-0 {
  148. atmel,pins =
  149. <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
  150. AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */
  151. };
  152. pinctrl_usart2_rts: usart2_rts-0 {
  153. atmel,pins =
  154. <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
  155. };
  156. pinctrl_usart2_cts: usart2_cts-0 {
  157. atmel,pins =
  158. <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
  159. };
  160. };
  161. usart3 {
  162. pinctrl_usart3: usart3-0 {
  163. atmel,pins =
  164. <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */
  165. AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */
  166. };
  167. pinctrl_usart3_rts: usart3_rts-0 {
  168. atmel,pins =
  169. <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
  170. };
  171. pinctrl_usart3_cts: usart3_cts-0 {
  172. atmel,pins =
  173. <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
  174. };
  175. };
  176. uart0 {
  177. pinctrl_uart0: uart0-0 {
  178. atmel,pins =
  179. <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */
  180. AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */
  181. };
  182. };
  183. uart1 {
  184. pinctrl_uart1: uart1-0 {
  185. atmel,pins =
  186. <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */
  187. AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */
  188. };
  189. };
  190. nand {
  191. pinctrl_nand: nand-0 {
  192. atmel,pins =
  193. <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/
  194. AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */
  195. };
  196. };
  197. mmc0 {
  198. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  199. atmel,pins =
  200. <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
  201. AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
  202. AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */
  203. };
  204. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  205. atmel,pins =
  206. <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
  207. AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
  208. AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
  209. };
  210. pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
  211. atmel,pins =
  212. <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
  213. AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */
  214. AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */
  215. AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */
  216. };
  217. };
  218. ssc0 {
  219. pinctrl_ssc0_tx: ssc0_tx-0 {
  220. atmel,pins =
  221. <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
  222. AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
  223. AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
  224. };
  225. pinctrl_ssc0_rx: ssc0_rx-0 {
  226. atmel,pins =
  227. <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
  228. AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
  229. AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
  230. };
  231. };
  232. spi0 {
  233. pinctrl_spi0: spi0-0 {
  234. atmel,pins =
  235. <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */
  236. AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */
  237. AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
  238. };
  239. };
  240. spi1 {
  241. pinctrl_spi1: spi1-0 {
  242. atmel,pins =
  243. <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */
  244. AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */
  245. AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
  246. };
  247. };
  248. tcb0 {
  249. pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
  250. atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  251. };
  252. pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
  253. atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  254. };
  255. pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
  256. atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  257. };
  258. pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
  259. atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  260. };
  261. pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
  262. atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  263. };
  264. pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
  265. atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  266. };
  267. pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
  268. atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  269. };
  270. pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
  271. atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  272. };
  273. pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
  274. atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  275. };
  276. };
  277. tcb1 {
  278. pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
  279. atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  280. };
  281. pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
  282. atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  283. };
  284. pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
  285. atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  286. };
  287. pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
  288. atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  289. };
  290. pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
  291. atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  292. };
  293. pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
  294. atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  295. };
  296. pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
  297. atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  298. };
  299. pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
  300. atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  301. };
  302. pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
  303. atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  304. };
  305. };
  306. pioA: gpio@fffff400 {
  307. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  308. reg = <0xfffff400 0x200>;
  309. interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
  310. #gpio-cells = <2>;
  311. gpio-controller;
  312. interrupt-controller;
  313. #interrupt-cells = <2>;
  314. };
  315. pioB: gpio@fffff600 {
  316. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  317. reg = <0xfffff600 0x200>;
  318. interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
  319. #gpio-cells = <2>;
  320. gpio-controller;
  321. interrupt-controller;
  322. #interrupt-cells = <2>;
  323. };
  324. pioC: gpio@fffff800 {
  325. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  326. reg = <0xfffff800 0x200>;
  327. interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
  328. #gpio-cells = <2>;
  329. gpio-controller;
  330. interrupt-controller;
  331. #interrupt-cells = <2>;
  332. };
  333. pioD: gpio@fffffa00 {
  334. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  335. reg = <0xfffffa00 0x200>;
  336. interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
  337. #gpio-cells = <2>;
  338. gpio-controller;
  339. interrupt-controller;
  340. #interrupt-cells = <2>;
  341. };
  342. };
  343. dbgu: serial@fffff200 {
  344. compatible = "atmel,at91sam9260-usart";
  345. reg = <0xfffff200 0x200>;
  346. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  347. pinctrl-names = "default";
  348. pinctrl-0 = <&pinctrl_dbgu>;
  349. status = "disabled";
  350. };
  351. ssc0: ssc@f0010000 {
  352. compatible = "atmel,at91sam9g45-ssc";
  353. reg = <0xf0010000 0x4000>;
  354. interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
  355. pinctrl-names = "default";
  356. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  357. status = "disabled";
  358. };
  359. usart0: serial@f801c000 {
  360. compatible = "atmel,at91sam9260-usart";
  361. reg = <0xf801c000 0x4000>;
  362. interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
  363. pinctrl-names = "default";
  364. pinctrl-0 = <&pinctrl_usart0>;
  365. status = "disabled";
  366. };
  367. usart1: serial@f8020000 {
  368. compatible = "atmel,at91sam9260-usart";
  369. reg = <0xf8020000 0x4000>;
  370. interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
  371. pinctrl-names = "default";
  372. pinctrl-0 = <&pinctrl_usart1>;
  373. status = "disabled";
  374. };
  375. usart2: serial@f8024000 {
  376. compatible = "atmel,at91sam9260-usart";
  377. reg = <0xf8024000 0x4000>;
  378. interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
  379. pinctrl-names = "default";
  380. pinctrl-0 = <&pinctrl_usart2>;
  381. status = "disabled";
  382. };
  383. usart3: serial@f8028000 {
  384. compatible = "atmel,at91sam9260-usart";
  385. reg = <0xf8028000 0x4000>;
  386. interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
  387. pinctrl-names = "default";
  388. pinctrl-0 = <&pinctrl_usart3>;
  389. status = "disabled";
  390. };
  391. i2c0: i2c@f8010000 {
  392. compatible = "atmel,at91sam9x5-i2c";
  393. reg = <0xf8010000 0x100>;
  394. interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
  395. dmas = <&dma 1 13>,
  396. <&dma 1 14>;
  397. dma-names = "tx", "rx";
  398. #address-cells = <1>;
  399. #size-cells = <0>;
  400. status = "disabled";
  401. };
  402. i2c1: i2c@f8014000 {
  403. compatible = "atmel,at91sam9x5-i2c";
  404. reg = <0xf8014000 0x100>;
  405. interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
  406. dmas = <&dma 1 15>,
  407. <&dma 1 16>;
  408. dma-names = "tx", "rx";
  409. #address-cells = <1>;
  410. #size-cells = <0>;
  411. status = "disabled";
  412. };
  413. spi0: spi@f0000000 {
  414. #address-cells = <1>;
  415. #size-cells = <0>;
  416. compatible = "atmel,at91rm9200-spi";
  417. reg = <0xf0000000 0x100>;
  418. interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
  419. pinctrl-names = "default";
  420. pinctrl-0 = <&pinctrl_spi0>;
  421. status = "disabled";
  422. };
  423. spi1: spi@f0004000 {
  424. #address-cells = <1>;
  425. #size-cells = <0>;
  426. compatible = "atmel,at91rm9200-spi";
  427. reg = <0xf0004000 0x100>;
  428. interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
  429. pinctrl-names = "default";
  430. pinctrl-0 = <&pinctrl_spi1>;
  431. status = "disabled";
  432. };
  433. watchdog@fffffe40 {
  434. compatible = "atmel,at91sam9260-wdt";
  435. reg = <0xfffffe40 0x10>;
  436. status = "disabled";
  437. };
  438. };
  439. nand0: nand@40000000 {
  440. compatible = "atmel,at91rm9200-nand";
  441. #address-cells = <1>;
  442. #size-cells = <1>;
  443. reg = < 0x40000000 0x10000000
  444. 0xffffe000 0x00000600
  445. 0xffffe600 0x00000200
  446. 0x00108000 0x00018000
  447. >;
  448. atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
  449. atmel,nand-addr-offset = <21>;
  450. atmel,nand-cmd-offset = <22>;
  451. pinctrl-names = "default";
  452. pinctrl-0 = <&pinctrl_nand>;
  453. gpios = <&pioD 5 GPIO_ACTIVE_HIGH
  454. &pioD 4 GPIO_ACTIVE_HIGH
  455. 0
  456. >;
  457. status = "disabled";
  458. };
  459. usb0: ohci@00500000 {
  460. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  461. reg = <0x00500000 0x00100000>;
  462. interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
  463. status = "disabled";
  464. };
  465. };
  466. i2c@0 {
  467. compatible = "i2c-gpio";
  468. gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
  469. &pioA 31 GPIO_ACTIVE_HIGH /* scl */
  470. >;
  471. i2c-gpio,sda-open-drain;
  472. i2c-gpio,scl-open-drain;
  473. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  474. #address-cells = <1>;
  475. #size-cells = <0>;
  476. status = "disabled";
  477. };
  478. };