devs.c 39 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643
  1. /* linux/arch/arm/plat-samsung/devs.c
  2. *
  3. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * Base SAMSUNG platform device definitions
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/types.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/list.h>
  16. #include <linux/timer.h>
  17. #include <linux/init.h>
  18. #include <linux/serial_core.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/io.h>
  21. #include <linux/slab.h>
  22. #include <linux/string.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/fb.h>
  25. #include <linux/gfp.h>
  26. #include <linux/mtd/mtd.h>
  27. #include <linux/mtd/onenand.h>
  28. #include <linux/mtd/partitions.h>
  29. #include <linux/mmc/host.h>
  30. #include <linux/ioport.h>
  31. #include <linux/platform_data/s3c-hsudc.h>
  32. #include <linux/platform_data/s3c-hsotg.h>
  33. #include <media/s5p_hdmi.h>
  34. #include <asm/irq.h>
  35. #include <asm/mach/arch.h>
  36. #include <asm/mach/map.h>
  37. #include <asm/mach/irq.h>
  38. #include <mach/hardware.h>
  39. #include <mach/dma.h>
  40. #include <mach/irqs.h>
  41. #include <mach/map.h>
  42. #include <plat/cpu.h>
  43. #include <plat/devs.h>
  44. #include <plat/adc.h>
  45. #include <plat/ata.h>
  46. #include <plat/ehci.h>
  47. #include <plat/fb.h>
  48. #include <plat/fb-s3c2410.h>
  49. #include <plat/hwmon.h>
  50. #include <plat/iic.h>
  51. #include <plat/keypad.h>
  52. #include <plat/mci.h>
  53. #include <plat/nand.h>
  54. #include <plat/sdhci.h>
  55. #include <plat/ts.h>
  56. #include <plat/udc.h>
  57. #include <plat/usb-control.h>
  58. #include <plat/usb-phy.h>
  59. #include <plat/regs-iic.h>
  60. #include <plat/regs-serial.h>
  61. #include <plat/regs-spi.h>
  62. #include <plat/s3c64xx-spi.h>
  63. static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
  64. /* AC97 */
  65. #ifdef CONFIG_CPU_S3C2440
  66. static struct resource s3c_ac97_resource[] = {
  67. [0] = DEFINE_RES_MEM(S3C2440_PA_AC97, S3C2440_SZ_AC97),
  68. [1] = DEFINE_RES_IRQ(IRQ_S3C244X_AC97),
  69. [2] = DEFINE_RES_DMA_NAMED(DMACH_PCM_OUT, "PCM out"),
  70. [3] = DEFINE_RES_DMA_NAMED(DMACH_PCM_IN, "PCM in"),
  71. [4] = DEFINE_RES_DMA_NAMED(DMACH_MIC_IN, "Mic in"),
  72. };
  73. struct platform_device s3c_device_ac97 = {
  74. .name = "samsung-ac97",
  75. .id = -1,
  76. .num_resources = ARRAY_SIZE(s3c_ac97_resource),
  77. .resource = s3c_ac97_resource,
  78. .dev = {
  79. .dma_mask = &samsung_device_dma_mask,
  80. .coherent_dma_mask = DMA_BIT_MASK(32),
  81. }
  82. };
  83. #endif /* CONFIG_CPU_S3C2440 */
  84. /* ADC */
  85. #ifdef CONFIG_PLAT_S3C24XX
  86. static struct resource s3c_adc_resource[] = {
  87. [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
  88. [1] = DEFINE_RES_IRQ(IRQ_TC),
  89. [2] = DEFINE_RES_IRQ(IRQ_ADC),
  90. };
  91. struct platform_device s3c_device_adc = {
  92. .name = "s3c24xx-adc",
  93. .id = -1,
  94. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  95. .resource = s3c_adc_resource,
  96. };
  97. #endif /* CONFIG_PLAT_S3C24XX */
  98. #if defined(CONFIG_SAMSUNG_DEV_ADC)
  99. static struct resource s3c_adc_resource[] = {
  100. [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
  101. [1] = DEFINE_RES_IRQ(IRQ_TC),
  102. [2] = DEFINE_RES_IRQ(IRQ_ADC),
  103. };
  104. struct platform_device s3c_device_adc = {
  105. .name = "samsung-adc",
  106. .id = -1,
  107. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  108. .resource = s3c_adc_resource,
  109. };
  110. #endif /* CONFIG_SAMSUNG_DEV_ADC */
  111. /* Camif Controller */
  112. #ifdef CONFIG_CPU_S3C2440
  113. static struct resource s3c_camif_resource[] = {
  114. [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF),
  115. [1] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_C),
  116. [2] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_P),
  117. };
  118. struct platform_device s3c_device_camif = {
  119. .name = "s3c2440-camif",
  120. .id = -1,
  121. .num_resources = ARRAY_SIZE(s3c_camif_resource),
  122. .resource = s3c_camif_resource,
  123. .dev = {
  124. .dma_mask = &samsung_device_dma_mask,
  125. .coherent_dma_mask = DMA_BIT_MASK(32),
  126. }
  127. };
  128. #endif /* CONFIG_CPU_S3C2440 */
  129. /* ASOC DMA */
  130. struct platform_device samsung_asoc_dma = {
  131. .name = "samsung-audio",
  132. .id = -1,
  133. .dev = {
  134. .dma_mask = &samsung_device_dma_mask,
  135. .coherent_dma_mask = DMA_BIT_MASK(32),
  136. }
  137. };
  138. struct platform_device samsung_asoc_idma = {
  139. .name = "samsung-idma",
  140. .id = -1,
  141. .dev = {
  142. .dma_mask = &samsung_device_dma_mask,
  143. .coherent_dma_mask = DMA_BIT_MASK(32),
  144. }
  145. };
  146. /* FB */
  147. #ifdef CONFIG_S3C_DEV_FB
  148. static struct resource s3c_fb_resource[] = {
  149. [0] = DEFINE_RES_MEM(S3C_PA_FB, SZ_16K),
  150. [1] = DEFINE_RES_IRQ(IRQ_LCD_VSYNC),
  151. [2] = DEFINE_RES_IRQ(IRQ_LCD_FIFO),
  152. [3] = DEFINE_RES_IRQ(IRQ_LCD_SYSTEM),
  153. };
  154. struct platform_device s3c_device_fb = {
  155. .name = "s3c-fb",
  156. .id = -1,
  157. .num_resources = ARRAY_SIZE(s3c_fb_resource),
  158. .resource = s3c_fb_resource,
  159. .dev = {
  160. .dma_mask = &samsung_device_dma_mask,
  161. .coherent_dma_mask = DMA_BIT_MASK(32),
  162. },
  163. };
  164. void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
  165. {
  166. s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
  167. &s3c_device_fb);
  168. }
  169. #endif /* CONFIG_S3C_DEV_FB */
  170. /* FIMC */
  171. #ifdef CONFIG_S5P_DEV_FIMC0
  172. static struct resource s5p_fimc0_resource[] = {
  173. [0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K),
  174. [1] = DEFINE_RES_IRQ(IRQ_FIMC0),
  175. };
  176. struct platform_device s5p_device_fimc0 = {
  177. .name = "s5p-fimc",
  178. .id = 0,
  179. .num_resources = ARRAY_SIZE(s5p_fimc0_resource),
  180. .resource = s5p_fimc0_resource,
  181. .dev = {
  182. .dma_mask = &samsung_device_dma_mask,
  183. .coherent_dma_mask = DMA_BIT_MASK(32),
  184. },
  185. };
  186. struct platform_device s5p_device_fimc_md = {
  187. .name = "s5p-fimc-md",
  188. .id = -1,
  189. };
  190. #endif /* CONFIG_S5P_DEV_FIMC0 */
  191. #ifdef CONFIG_S5P_DEV_FIMC1
  192. static struct resource s5p_fimc1_resource[] = {
  193. [0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K),
  194. [1] = DEFINE_RES_IRQ(IRQ_FIMC1),
  195. };
  196. struct platform_device s5p_device_fimc1 = {
  197. .name = "s5p-fimc",
  198. .id = 1,
  199. .num_resources = ARRAY_SIZE(s5p_fimc1_resource),
  200. .resource = s5p_fimc1_resource,
  201. .dev = {
  202. .dma_mask = &samsung_device_dma_mask,
  203. .coherent_dma_mask = DMA_BIT_MASK(32),
  204. },
  205. };
  206. #endif /* CONFIG_S5P_DEV_FIMC1 */
  207. #ifdef CONFIG_S5P_DEV_FIMC2
  208. static struct resource s5p_fimc2_resource[] = {
  209. [0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K),
  210. [1] = DEFINE_RES_IRQ(IRQ_FIMC2),
  211. };
  212. struct platform_device s5p_device_fimc2 = {
  213. .name = "s5p-fimc",
  214. .id = 2,
  215. .num_resources = ARRAY_SIZE(s5p_fimc2_resource),
  216. .resource = s5p_fimc2_resource,
  217. .dev = {
  218. .dma_mask = &samsung_device_dma_mask,
  219. .coherent_dma_mask = DMA_BIT_MASK(32),
  220. },
  221. };
  222. #endif /* CONFIG_S5P_DEV_FIMC2 */
  223. #ifdef CONFIG_S5P_DEV_FIMC3
  224. static struct resource s5p_fimc3_resource[] = {
  225. [0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K),
  226. [1] = DEFINE_RES_IRQ(IRQ_FIMC3),
  227. };
  228. struct platform_device s5p_device_fimc3 = {
  229. .name = "s5p-fimc",
  230. .id = 3,
  231. .num_resources = ARRAY_SIZE(s5p_fimc3_resource),
  232. .resource = s5p_fimc3_resource,
  233. .dev = {
  234. .dma_mask = &samsung_device_dma_mask,
  235. .coherent_dma_mask = DMA_BIT_MASK(32),
  236. },
  237. };
  238. #endif /* CONFIG_S5P_DEV_FIMC3 */
  239. /* G2D */
  240. #ifdef CONFIG_S5P_DEV_G2D
  241. static struct resource s5p_g2d_resource[] = {
  242. [0] = DEFINE_RES_MEM(S5P_PA_G2D, SZ_4K),
  243. [1] = DEFINE_RES_IRQ(IRQ_2D),
  244. };
  245. struct platform_device s5p_device_g2d = {
  246. .name = "s5p-g2d",
  247. .id = 0,
  248. .num_resources = ARRAY_SIZE(s5p_g2d_resource),
  249. .resource = s5p_g2d_resource,
  250. .dev = {
  251. .dma_mask = &samsung_device_dma_mask,
  252. .coherent_dma_mask = DMA_BIT_MASK(32),
  253. },
  254. };
  255. #endif /* CONFIG_S5P_DEV_G2D */
  256. #ifdef CONFIG_S5P_DEV_JPEG
  257. static struct resource s5p_jpeg_resource[] = {
  258. [0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K),
  259. [1] = DEFINE_RES_IRQ(IRQ_JPEG),
  260. };
  261. struct platform_device s5p_device_jpeg = {
  262. .name = "s5p-jpeg",
  263. .id = 0,
  264. .num_resources = ARRAY_SIZE(s5p_jpeg_resource),
  265. .resource = s5p_jpeg_resource,
  266. .dev = {
  267. .dma_mask = &samsung_device_dma_mask,
  268. .coherent_dma_mask = DMA_BIT_MASK(32),
  269. },
  270. };
  271. #endif /* CONFIG_S5P_DEV_JPEG */
  272. /* FIMD0 */
  273. #ifdef CONFIG_S5P_DEV_FIMD0
  274. static struct resource s5p_fimd0_resource[] = {
  275. [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
  276. [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC),
  277. [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO),
  278. [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM),
  279. };
  280. struct platform_device s5p_device_fimd0 = {
  281. .name = "s5p-fb",
  282. .id = 0,
  283. .num_resources = ARRAY_SIZE(s5p_fimd0_resource),
  284. .resource = s5p_fimd0_resource,
  285. .dev = {
  286. .dma_mask = &samsung_device_dma_mask,
  287. .coherent_dma_mask = DMA_BIT_MASK(32),
  288. },
  289. };
  290. void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
  291. {
  292. s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
  293. &s5p_device_fimd0);
  294. }
  295. #endif /* CONFIG_S5P_DEV_FIMD0 */
  296. /* HWMON */
  297. #ifdef CONFIG_S3C_DEV_HWMON
  298. struct platform_device s3c_device_hwmon = {
  299. .name = "s3c-hwmon",
  300. .id = -1,
  301. .dev.parent = &s3c_device_adc.dev,
  302. };
  303. void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd)
  304. {
  305. s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata),
  306. &s3c_device_hwmon);
  307. }
  308. #endif /* CONFIG_S3C_DEV_HWMON */
  309. /* HSMMC */
  310. #ifdef CONFIG_S3C_DEV_HSMMC
  311. static struct resource s3c_hsmmc_resource[] = {
  312. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC0, SZ_4K),
  313. [1] = DEFINE_RES_IRQ(IRQ_HSMMC0),
  314. };
  315. struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
  316. .max_width = 4,
  317. .host_caps = (MMC_CAP_4_BIT_DATA |
  318. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  319. };
  320. struct platform_device s3c_device_hsmmc0 = {
  321. .name = "s3c-sdhci",
  322. .id = 0,
  323. .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
  324. .resource = s3c_hsmmc_resource,
  325. .dev = {
  326. .dma_mask = &samsung_device_dma_mask,
  327. .coherent_dma_mask = DMA_BIT_MASK(32),
  328. .platform_data = &s3c_hsmmc0_def_platdata,
  329. },
  330. };
  331. void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
  332. {
  333. s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata);
  334. }
  335. #endif /* CONFIG_S3C_DEV_HSMMC */
  336. #ifdef CONFIG_S3C_DEV_HSMMC1
  337. static struct resource s3c_hsmmc1_resource[] = {
  338. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC1, SZ_4K),
  339. [1] = DEFINE_RES_IRQ(IRQ_HSMMC1),
  340. };
  341. struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
  342. .max_width = 4,
  343. .host_caps = (MMC_CAP_4_BIT_DATA |
  344. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  345. };
  346. struct platform_device s3c_device_hsmmc1 = {
  347. .name = "s3c-sdhci",
  348. .id = 1,
  349. .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
  350. .resource = s3c_hsmmc1_resource,
  351. .dev = {
  352. .dma_mask = &samsung_device_dma_mask,
  353. .coherent_dma_mask = DMA_BIT_MASK(32),
  354. .platform_data = &s3c_hsmmc1_def_platdata,
  355. },
  356. };
  357. void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
  358. {
  359. s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata);
  360. }
  361. #endif /* CONFIG_S3C_DEV_HSMMC1 */
  362. /* HSMMC2 */
  363. #ifdef CONFIG_S3C_DEV_HSMMC2
  364. static struct resource s3c_hsmmc2_resource[] = {
  365. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC2, SZ_4K),
  366. [1] = DEFINE_RES_IRQ(IRQ_HSMMC2),
  367. };
  368. struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
  369. .max_width = 4,
  370. .host_caps = (MMC_CAP_4_BIT_DATA |
  371. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  372. };
  373. struct platform_device s3c_device_hsmmc2 = {
  374. .name = "s3c-sdhci",
  375. .id = 2,
  376. .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource),
  377. .resource = s3c_hsmmc2_resource,
  378. .dev = {
  379. .dma_mask = &samsung_device_dma_mask,
  380. .coherent_dma_mask = DMA_BIT_MASK(32),
  381. .platform_data = &s3c_hsmmc2_def_platdata,
  382. },
  383. };
  384. void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
  385. {
  386. s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata);
  387. }
  388. #endif /* CONFIG_S3C_DEV_HSMMC2 */
  389. #ifdef CONFIG_S3C_DEV_HSMMC3
  390. static struct resource s3c_hsmmc3_resource[] = {
  391. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC3, SZ_4K),
  392. [1] = DEFINE_RES_IRQ(IRQ_HSMMC3),
  393. };
  394. struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
  395. .max_width = 4,
  396. .host_caps = (MMC_CAP_4_BIT_DATA |
  397. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  398. };
  399. struct platform_device s3c_device_hsmmc3 = {
  400. .name = "s3c-sdhci",
  401. .id = 3,
  402. .num_resources = ARRAY_SIZE(s3c_hsmmc3_resource),
  403. .resource = s3c_hsmmc3_resource,
  404. .dev = {
  405. .dma_mask = &samsung_device_dma_mask,
  406. .coherent_dma_mask = DMA_BIT_MASK(32),
  407. .platform_data = &s3c_hsmmc3_def_platdata,
  408. },
  409. };
  410. void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
  411. {
  412. s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata);
  413. }
  414. #endif /* CONFIG_S3C_DEV_HSMMC3 */
  415. /* I2C */
  416. static struct resource s3c_i2c0_resource[] = {
  417. [0] = DEFINE_RES_MEM(S3C_PA_IIC, SZ_4K),
  418. [1] = DEFINE_RES_IRQ(IRQ_IIC),
  419. };
  420. struct platform_device s3c_device_i2c0 = {
  421. .name = "s3c2410-i2c",
  422. #ifdef CONFIG_S3C_DEV_I2C1
  423. .id = 0,
  424. #else
  425. .id = -1,
  426. #endif
  427. .num_resources = ARRAY_SIZE(s3c_i2c0_resource),
  428. .resource = s3c_i2c0_resource,
  429. };
  430. struct s3c2410_platform_i2c default_i2c_data __initdata = {
  431. .flags = 0,
  432. .slave_addr = 0x10,
  433. .frequency = 100*1000,
  434. .sda_delay = 100,
  435. };
  436. void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
  437. {
  438. struct s3c2410_platform_i2c *npd;
  439. if (!pd) {
  440. pd = &default_i2c_data;
  441. pd->bus_num = 0;
  442. }
  443. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  444. &s3c_device_i2c0);
  445. if (!npd->cfg_gpio)
  446. npd->cfg_gpio = s3c_i2c0_cfg_gpio;
  447. }
  448. #ifdef CONFIG_S3C_DEV_I2C1
  449. static struct resource s3c_i2c1_resource[] = {
  450. [0] = DEFINE_RES_MEM(S3C_PA_IIC1, SZ_4K),
  451. [1] = DEFINE_RES_IRQ(IRQ_IIC1),
  452. };
  453. struct platform_device s3c_device_i2c1 = {
  454. .name = "s3c2410-i2c",
  455. .id = 1,
  456. .num_resources = ARRAY_SIZE(s3c_i2c1_resource),
  457. .resource = s3c_i2c1_resource,
  458. };
  459. void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
  460. {
  461. struct s3c2410_platform_i2c *npd;
  462. if (!pd) {
  463. pd = &default_i2c_data;
  464. pd->bus_num = 1;
  465. }
  466. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  467. &s3c_device_i2c1);
  468. if (!npd->cfg_gpio)
  469. npd->cfg_gpio = s3c_i2c1_cfg_gpio;
  470. }
  471. #endif /* CONFIG_S3C_DEV_I2C1 */
  472. #ifdef CONFIG_S3C_DEV_I2C2
  473. static struct resource s3c_i2c2_resource[] = {
  474. [0] = DEFINE_RES_MEM(S3C_PA_IIC2, SZ_4K),
  475. [1] = DEFINE_RES_IRQ(IRQ_IIC2),
  476. };
  477. struct platform_device s3c_device_i2c2 = {
  478. .name = "s3c2410-i2c",
  479. .id = 2,
  480. .num_resources = ARRAY_SIZE(s3c_i2c2_resource),
  481. .resource = s3c_i2c2_resource,
  482. };
  483. void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
  484. {
  485. struct s3c2410_platform_i2c *npd;
  486. if (!pd) {
  487. pd = &default_i2c_data;
  488. pd->bus_num = 2;
  489. }
  490. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  491. &s3c_device_i2c2);
  492. if (!npd->cfg_gpio)
  493. npd->cfg_gpio = s3c_i2c2_cfg_gpio;
  494. }
  495. #endif /* CONFIG_S3C_DEV_I2C2 */
  496. #ifdef CONFIG_S3C_DEV_I2C3
  497. static struct resource s3c_i2c3_resource[] = {
  498. [0] = DEFINE_RES_MEM(S3C_PA_IIC3, SZ_4K),
  499. [1] = DEFINE_RES_IRQ(IRQ_IIC3),
  500. };
  501. struct platform_device s3c_device_i2c3 = {
  502. .name = "s3c2440-i2c",
  503. .id = 3,
  504. .num_resources = ARRAY_SIZE(s3c_i2c3_resource),
  505. .resource = s3c_i2c3_resource,
  506. };
  507. void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd)
  508. {
  509. struct s3c2410_platform_i2c *npd;
  510. if (!pd) {
  511. pd = &default_i2c_data;
  512. pd->bus_num = 3;
  513. }
  514. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  515. &s3c_device_i2c3);
  516. if (!npd->cfg_gpio)
  517. npd->cfg_gpio = s3c_i2c3_cfg_gpio;
  518. }
  519. #endif /*CONFIG_S3C_DEV_I2C3 */
  520. #ifdef CONFIG_S3C_DEV_I2C4
  521. static struct resource s3c_i2c4_resource[] = {
  522. [0] = DEFINE_RES_MEM(S3C_PA_IIC4, SZ_4K),
  523. [1] = DEFINE_RES_IRQ(IRQ_IIC4),
  524. };
  525. struct platform_device s3c_device_i2c4 = {
  526. .name = "s3c2440-i2c",
  527. .id = 4,
  528. .num_resources = ARRAY_SIZE(s3c_i2c4_resource),
  529. .resource = s3c_i2c4_resource,
  530. };
  531. void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd)
  532. {
  533. struct s3c2410_platform_i2c *npd;
  534. if (!pd) {
  535. pd = &default_i2c_data;
  536. pd->bus_num = 4;
  537. }
  538. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  539. &s3c_device_i2c4);
  540. if (!npd->cfg_gpio)
  541. npd->cfg_gpio = s3c_i2c4_cfg_gpio;
  542. }
  543. #endif /*CONFIG_S3C_DEV_I2C4 */
  544. #ifdef CONFIG_S3C_DEV_I2C5
  545. static struct resource s3c_i2c5_resource[] = {
  546. [0] = DEFINE_RES_MEM(S3C_PA_IIC5, SZ_4K),
  547. [1] = DEFINE_RES_IRQ(IRQ_IIC5),
  548. };
  549. struct platform_device s3c_device_i2c5 = {
  550. .name = "s3c2440-i2c",
  551. .id = 5,
  552. .num_resources = ARRAY_SIZE(s3c_i2c5_resource),
  553. .resource = s3c_i2c5_resource,
  554. };
  555. void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd)
  556. {
  557. struct s3c2410_platform_i2c *npd;
  558. if (!pd) {
  559. pd = &default_i2c_data;
  560. pd->bus_num = 5;
  561. }
  562. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  563. &s3c_device_i2c5);
  564. if (!npd->cfg_gpio)
  565. npd->cfg_gpio = s3c_i2c5_cfg_gpio;
  566. }
  567. #endif /*CONFIG_S3C_DEV_I2C5 */
  568. #ifdef CONFIG_S3C_DEV_I2C6
  569. static struct resource s3c_i2c6_resource[] = {
  570. [0] = DEFINE_RES_MEM(S3C_PA_IIC6, SZ_4K),
  571. [1] = DEFINE_RES_IRQ(IRQ_IIC6),
  572. };
  573. struct platform_device s3c_device_i2c6 = {
  574. .name = "s3c2440-i2c",
  575. .id = 6,
  576. .num_resources = ARRAY_SIZE(s3c_i2c6_resource),
  577. .resource = s3c_i2c6_resource,
  578. };
  579. void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd)
  580. {
  581. struct s3c2410_platform_i2c *npd;
  582. if (!pd) {
  583. pd = &default_i2c_data;
  584. pd->bus_num = 6;
  585. }
  586. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  587. &s3c_device_i2c6);
  588. if (!npd->cfg_gpio)
  589. npd->cfg_gpio = s3c_i2c6_cfg_gpio;
  590. }
  591. #endif /* CONFIG_S3C_DEV_I2C6 */
  592. #ifdef CONFIG_S3C_DEV_I2C7
  593. static struct resource s3c_i2c7_resource[] = {
  594. [0] = DEFINE_RES_MEM(S3C_PA_IIC7, SZ_4K),
  595. [1] = DEFINE_RES_IRQ(IRQ_IIC7),
  596. };
  597. struct platform_device s3c_device_i2c7 = {
  598. .name = "s3c2440-i2c",
  599. .id = 7,
  600. .num_resources = ARRAY_SIZE(s3c_i2c7_resource),
  601. .resource = s3c_i2c7_resource,
  602. };
  603. void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
  604. {
  605. struct s3c2410_platform_i2c *npd;
  606. if (!pd) {
  607. pd = &default_i2c_data;
  608. pd->bus_num = 7;
  609. }
  610. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  611. &s3c_device_i2c7);
  612. if (!npd->cfg_gpio)
  613. npd->cfg_gpio = s3c_i2c7_cfg_gpio;
  614. }
  615. #endif /* CONFIG_S3C_DEV_I2C7 */
  616. /* I2C HDMIPHY */
  617. #ifdef CONFIG_S5P_DEV_I2C_HDMIPHY
  618. static struct resource s5p_i2c_resource[] = {
  619. [0] = DEFINE_RES_MEM(S5P_PA_IIC_HDMIPHY, SZ_4K),
  620. [1] = DEFINE_RES_IRQ(IRQ_IIC_HDMIPHY),
  621. };
  622. struct platform_device s5p_device_i2c_hdmiphy = {
  623. .name = "s3c2440-hdmiphy-i2c",
  624. .id = -1,
  625. .num_resources = ARRAY_SIZE(s5p_i2c_resource),
  626. .resource = s5p_i2c_resource,
  627. };
  628. void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
  629. {
  630. struct s3c2410_platform_i2c *npd;
  631. if (!pd) {
  632. pd = &default_i2c_data;
  633. if (soc_is_exynos4210() ||
  634. soc_is_exynos4212() || soc_is_exynos4412())
  635. pd->bus_num = 8;
  636. else if (soc_is_s5pv210())
  637. pd->bus_num = 3;
  638. else
  639. pd->bus_num = 0;
  640. }
  641. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  642. &s5p_device_i2c_hdmiphy);
  643. }
  644. struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
  645. void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
  646. struct i2c_board_info *mhl_info, int mhl_bus)
  647. {
  648. struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata;
  649. if (soc_is_exynos4210() ||
  650. soc_is_exynos4212() || soc_is_exynos4412())
  651. pd->hdmiphy_bus = 8;
  652. else if (soc_is_s5pv210())
  653. pd->hdmiphy_bus = 3;
  654. else
  655. pd->hdmiphy_bus = 0;
  656. pd->hdmiphy_info = hdmiphy_info;
  657. pd->mhl_info = mhl_info;
  658. pd->mhl_bus = mhl_bus;
  659. s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data),
  660. &s5p_device_hdmi);
  661. }
  662. #endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
  663. /* I2S */
  664. #ifdef CONFIG_PLAT_S3C24XX
  665. static struct resource s3c_iis_resource[] = {
  666. [0] = DEFINE_RES_MEM(S3C24XX_PA_IIS, S3C24XX_SZ_IIS),
  667. };
  668. struct platform_device s3c_device_iis = {
  669. .name = "s3c24xx-iis",
  670. .id = -1,
  671. .num_resources = ARRAY_SIZE(s3c_iis_resource),
  672. .resource = s3c_iis_resource,
  673. .dev = {
  674. .dma_mask = &samsung_device_dma_mask,
  675. .coherent_dma_mask = DMA_BIT_MASK(32),
  676. }
  677. };
  678. #endif /* CONFIG_PLAT_S3C24XX */
  679. /* IDE CFCON */
  680. #ifdef CONFIG_SAMSUNG_DEV_IDE
  681. static struct resource s3c_cfcon_resource[] = {
  682. [0] = DEFINE_RES_MEM(SAMSUNG_PA_CFCON, SZ_16K),
  683. [1] = DEFINE_RES_IRQ(IRQ_CFCON),
  684. };
  685. struct platform_device s3c_device_cfcon = {
  686. .id = 0,
  687. .num_resources = ARRAY_SIZE(s3c_cfcon_resource),
  688. .resource = s3c_cfcon_resource,
  689. };
  690. void __init s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
  691. {
  692. s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata),
  693. &s3c_device_cfcon);
  694. }
  695. #endif /* CONFIG_SAMSUNG_DEV_IDE */
  696. /* KEYPAD */
  697. #ifdef CONFIG_SAMSUNG_DEV_KEYPAD
  698. static struct resource samsung_keypad_resources[] = {
  699. [0] = DEFINE_RES_MEM(SAMSUNG_PA_KEYPAD, SZ_32),
  700. [1] = DEFINE_RES_IRQ(IRQ_KEYPAD),
  701. };
  702. struct platform_device samsung_device_keypad = {
  703. .name = "samsung-keypad",
  704. .id = -1,
  705. .num_resources = ARRAY_SIZE(samsung_keypad_resources),
  706. .resource = samsung_keypad_resources,
  707. };
  708. void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
  709. {
  710. struct samsung_keypad_platdata *npd;
  711. npd = s3c_set_platdata(pd, sizeof(struct samsung_keypad_platdata),
  712. &samsung_device_keypad);
  713. if (!npd->cfg_gpio)
  714. npd->cfg_gpio = samsung_keypad_cfg_gpio;
  715. }
  716. #endif /* CONFIG_SAMSUNG_DEV_KEYPAD */
  717. /* LCD Controller */
  718. #ifdef CONFIG_PLAT_S3C24XX
  719. static struct resource s3c_lcd_resource[] = {
  720. [0] = DEFINE_RES_MEM(S3C24XX_PA_LCD, S3C24XX_SZ_LCD),
  721. [1] = DEFINE_RES_IRQ(IRQ_LCD),
  722. };
  723. struct platform_device s3c_device_lcd = {
  724. .name = "s3c2410-lcd",
  725. .id = -1,
  726. .num_resources = ARRAY_SIZE(s3c_lcd_resource),
  727. .resource = s3c_lcd_resource,
  728. .dev = {
  729. .dma_mask = &samsung_device_dma_mask,
  730. .coherent_dma_mask = DMA_BIT_MASK(32),
  731. }
  732. };
  733. void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
  734. {
  735. struct s3c2410fb_mach_info *npd;
  736. npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_lcd);
  737. if (npd) {
  738. npd->displays = kmemdup(pd->displays,
  739. sizeof(struct s3c2410fb_display) * npd->num_displays,
  740. GFP_KERNEL);
  741. if (!npd->displays)
  742. printk(KERN_ERR "no memory for LCD display data\n");
  743. } else {
  744. printk(KERN_ERR "no memory for LCD platform data\n");
  745. }
  746. }
  747. #endif /* CONFIG_PLAT_S3C24XX */
  748. /* MFC */
  749. #ifdef CONFIG_S5P_DEV_MFC
  750. static struct resource s5p_mfc_resource[] = {
  751. [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
  752. [1] = DEFINE_RES_IRQ(IRQ_MFC),
  753. };
  754. struct platform_device s5p_device_mfc = {
  755. .name = "s5p-mfc",
  756. .id = -1,
  757. .num_resources = ARRAY_SIZE(s5p_mfc_resource),
  758. .resource = s5p_mfc_resource,
  759. };
  760. /*
  761. * MFC hardware has 2 memory interfaces which are modelled as two separate
  762. * platform devices to let dma-mapping distinguish between them.
  763. *
  764. * MFC parent device (s5p_device_mfc) must be registered before memory
  765. * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
  766. */
  767. struct platform_device s5p_device_mfc_l = {
  768. .name = "s5p-mfc-l",
  769. .id = -1,
  770. .dev = {
  771. .parent = &s5p_device_mfc.dev,
  772. .dma_mask = &samsung_device_dma_mask,
  773. .coherent_dma_mask = DMA_BIT_MASK(32),
  774. },
  775. };
  776. struct platform_device s5p_device_mfc_r = {
  777. .name = "s5p-mfc-r",
  778. .id = -1,
  779. .dev = {
  780. .parent = &s5p_device_mfc.dev,
  781. .dma_mask = &samsung_device_dma_mask,
  782. .coherent_dma_mask = DMA_BIT_MASK(32),
  783. },
  784. };
  785. #endif /* CONFIG_S5P_DEV_MFC */
  786. /* MIPI CSIS */
  787. #ifdef CONFIG_S5P_DEV_CSIS0
  788. static struct resource s5p_mipi_csis0_resource[] = {
  789. [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_16K),
  790. [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0),
  791. };
  792. struct platform_device s5p_device_mipi_csis0 = {
  793. .name = "s5p-mipi-csis",
  794. .id = 0,
  795. .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource),
  796. .resource = s5p_mipi_csis0_resource,
  797. };
  798. #endif /* CONFIG_S5P_DEV_CSIS0 */
  799. #ifdef CONFIG_S5P_DEV_CSIS1
  800. static struct resource s5p_mipi_csis1_resource[] = {
  801. [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_16K),
  802. [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1),
  803. };
  804. struct platform_device s5p_device_mipi_csis1 = {
  805. .name = "s5p-mipi-csis",
  806. .id = 1,
  807. .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource),
  808. .resource = s5p_mipi_csis1_resource,
  809. };
  810. #endif
  811. /* NAND */
  812. #ifdef CONFIG_S3C_DEV_NAND
  813. static struct resource s3c_nand_resource[] = {
  814. [0] = DEFINE_RES_MEM(S3C_PA_NAND, SZ_1M),
  815. };
  816. struct platform_device s3c_device_nand = {
  817. .name = "s3c2410-nand",
  818. .id = -1,
  819. .num_resources = ARRAY_SIZE(s3c_nand_resource),
  820. .resource = s3c_nand_resource,
  821. };
  822. /*
  823. * s3c_nand_copy_set() - copy nand set data
  824. * @set: The new structure, directly copied from the old.
  825. *
  826. * Copy all the fields from the NAND set field from what is probably __initdata
  827. * to new kernel memory. The code returns 0 if the copy happened correctly or
  828. * an error code for the calling function to display.
  829. *
  830. * Note, we currently do not try and look to see if we've already copied the
  831. * data in a previous set.
  832. */
  833. static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set)
  834. {
  835. void *ptr;
  836. int size;
  837. size = sizeof(struct mtd_partition) * set->nr_partitions;
  838. if (size) {
  839. ptr = kmemdup(set->partitions, size, GFP_KERNEL);
  840. set->partitions = ptr;
  841. if (!ptr)
  842. return -ENOMEM;
  843. }
  844. if (set->nr_map && set->nr_chips) {
  845. size = sizeof(int) * set->nr_chips;
  846. ptr = kmemdup(set->nr_map, size, GFP_KERNEL);
  847. set->nr_map = ptr;
  848. if (!ptr)
  849. return -ENOMEM;
  850. }
  851. if (set->ecc_layout) {
  852. ptr = kmemdup(set->ecc_layout,
  853. sizeof(struct nand_ecclayout), GFP_KERNEL);
  854. set->ecc_layout = ptr;
  855. if (!ptr)
  856. return -ENOMEM;
  857. }
  858. return 0;
  859. }
  860. void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
  861. {
  862. struct s3c2410_platform_nand *npd;
  863. int size;
  864. int ret;
  865. /* note, if we get a failure in allocation, we simply drop out of the
  866. * function. If there is so little memory available at initialisation
  867. * time then there is little chance the system is going to run.
  868. */
  869. npd = s3c_set_platdata(nand, sizeof(struct s3c2410_platform_nand),
  870. &s3c_device_nand);
  871. if (!npd)
  872. return;
  873. /* now see if we need to copy any of the nand set data */
  874. size = sizeof(struct s3c2410_nand_set) * npd->nr_sets;
  875. if (size) {
  876. struct s3c2410_nand_set *from = npd->sets;
  877. struct s3c2410_nand_set *to;
  878. int i;
  879. to = kmemdup(from, size, GFP_KERNEL);
  880. npd->sets = to; /* set, even if we failed */
  881. if (!to) {
  882. printk(KERN_ERR "%s: no memory for sets\n", __func__);
  883. return;
  884. }
  885. for (i = 0; i < npd->nr_sets; i++) {
  886. ret = s3c_nand_copy_set(to);
  887. if (ret) {
  888. printk(KERN_ERR "%s: failed to copy set %d\n",
  889. __func__, i);
  890. return;
  891. }
  892. to++;
  893. }
  894. }
  895. }
  896. #endif /* CONFIG_S3C_DEV_NAND */
  897. /* ONENAND */
  898. #ifdef CONFIG_S3C_DEV_ONENAND
  899. static struct resource s3c_onenand_resources[] = {
  900. [0] = DEFINE_RES_MEM(S3C_PA_ONENAND, SZ_1K),
  901. [1] = DEFINE_RES_MEM(S3C_PA_ONENAND_BUF, S3C_SZ_ONENAND_BUF),
  902. [2] = DEFINE_RES_IRQ(IRQ_ONENAND),
  903. };
  904. struct platform_device s3c_device_onenand = {
  905. .name = "samsung-onenand",
  906. .id = 0,
  907. .num_resources = ARRAY_SIZE(s3c_onenand_resources),
  908. .resource = s3c_onenand_resources,
  909. };
  910. #endif /* CONFIG_S3C_DEV_ONENAND */
  911. #ifdef CONFIG_S3C64XX_DEV_ONENAND1
  912. static struct resource s3c64xx_onenand1_resources[] = {
  913. [0] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1, SZ_1K),
  914. [1] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1_BUF, S3C64XX_SZ_ONENAND1_BUF),
  915. [2] = DEFINE_RES_IRQ(IRQ_ONENAND1),
  916. };
  917. struct platform_device s3c64xx_device_onenand1 = {
  918. .name = "samsung-onenand",
  919. .id = 1,
  920. .num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources),
  921. .resource = s3c64xx_onenand1_resources,
  922. };
  923. void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
  924. {
  925. s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
  926. &s3c64xx_device_onenand1);
  927. }
  928. #endif /* CONFIG_S3C64XX_DEV_ONENAND1 */
  929. #ifdef CONFIG_S5P_DEV_ONENAND
  930. static struct resource s5p_onenand_resources[] = {
  931. [0] = DEFINE_RES_MEM(S5P_PA_ONENAND, SZ_128K),
  932. [1] = DEFINE_RES_MEM(S5P_PA_ONENAND_DMA, SZ_8K),
  933. [2] = DEFINE_RES_IRQ(IRQ_ONENAND_AUDI),
  934. };
  935. struct platform_device s5p_device_onenand = {
  936. .name = "s5pc110-onenand",
  937. .id = -1,
  938. .num_resources = ARRAY_SIZE(s5p_onenand_resources),
  939. .resource = s5p_onenand_resources,
  940. };
  941. #endif /* CONFIG_S5P_DEV_ONENAND */
  942. /* PMU */
  943. #ifdef CONFIG_PLAT_S5P
  944. static struct resource s5p_pmu_resource[] = {
  945. DEFINE_RES_IRQ(IRQ_PMU)
  946. };
  947. static struct platform_device s5p_device_pmu = {
  948. .name = "arm-pmu",
  949. .id = -1,
  950. .num_resources = ARRAY_SIZE(s5p_pmu_resource),
  951. .resource = s5p_pmu_resource,
  952. };
  953. static int __init s5p_pmu_init(void)
  954. {
  955. platform_device_register(&s5p_device_pmu);
  956. return 0;
  957. }
  958. arch_initcall(s5p_pmu_init);
  959. #endif /* CONFIG_PLAT_S5P */
  960. /* PWM Timer */
  961. #ifdef CONFIG_SAMSUNG_DEV_PWM
  962. #define TIMER_RESOURCE_SIZE (1)
  963. #define TIMER_RESOURCE(_tmr, _irq) \
  964. (struct resource [TIMER_RESOURCE_SIZE]) { \
  965. [0] = { \
  966. .start = _irq, \
  967. .end = _irq, \
  968. .flags = IORESOURCE_IRQ \
  969. } \
  970. }
  971. #define DEFINE_S3C_TIMER(_tmr_no, _irq) \
  972. .name = "s3c24xx-pwm", \
  973. .id = _tmr_no, \
  974. .num_resources = TIMER_RESOURCE_SIZE, \
  975. .resource = TIMER_RESOURCE(_tmr_no, _irq), \
  976. /*
  977. * since we already have an static mapping for the timer,
  978. * we do not bother setting any IO resource for the base.
  979. */
  980. struct platform_device s3c_device_timer[] = {
  981. [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
  982. [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
  983. [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
  984. [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
  985. [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
  986. };
  987. #endif /* CONFIG_SAMSUNG_DEV_PWM */
  988. /* RTC */
  989. #ifdef CONFIG_PLAT_S3C24XX
  990. static struct resource s3c_rtc_resource[] = {
  991. [0] = DEFINE_RES_MEM(S3C24XX_PA_RTC, SZ_256),
  992. [1] = DEFINE_RES_IRQ(IRQ_RTC),
  993. [2] = DEFINE_RES_IRQ(IRQ_TICK),
  994. };
  995. struct platform_device s3c_device_rtc = {
  996. .name = "s3c2410-rtc",
  997. .id = -1,
  998. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  999. .resource = s3c_rtc_resource,
  1000. };
  1001. #endif /* CONFIG_PLAT_S3C24XX */
  1002. #ifdef CONFIG_S3C_DEV_RTC
  1003. static struct resource s3c_rtc_resource[] = {
  1004. [0] = DEFINE_RES_MEM(S3C_PA_RTC, SZ_256),
  1005. [1] = DEFINE_RES_IRQ(IRQ_RTC_ALARM),
  1006. [2] = DEFINE_RES_IRQ(IRQ_RTC_TIC),
  1007. };
  1008. struct platform_device s3c_device_rtc = {
  1009. .name = "s3c64xx-rtc",
  1010. .id = -1,
  1011. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  1012. .resource = s3c_rtc_resource,
  1013. };
  1014. #endif /* CONFIG_S3C_DEV_RTC */
  1015. /* SDI */
  1016. #ifdef CONFIG_PLAT_S3C24XX
  1017. static struct resource s3c_sdi_resource[] = {
  1018. [0] = DEFINE_RES_MEM(S3C24XX_PA_SDI, S3C24XX_SZ_SDI),
  1019. [1] = DEFINE_RES_IRQ(IRQ_SDI),
  1020. };
  1021. struct platform_device s3c_device_sdi = {
  1022. .name = "s3c2410-sdi",
  1023. .id = -1,
  1024. .num_resources = ARRAY_SIZE(s3c_sdi_resource),
  1025. .resource = s3c_sdi_resource,
  1026. };
  1027. void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
  1028. {
  1029. s3c_set_platdata(pdata, sizeof(struct s3c24xx_mci_pdata),
  1030. &s3c_device_sdi);
  1031. }
  1032. #endif /* CONFIG_PLAT_S3C24XX */
  1033. /* SPI */
  1034. #ifdef CONFIG_PLAT_S3C24XX
  1035. static struct resource s3c_spi0_resource[] = {
  1036. [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI, SZ_32),
  1037. [1] = DEFINE_RES_IRQ(IRQ_SPI0),
  1038. };
  1039. struct platform_device s3c_device_spi0 = {
  1040. .name = "s3c2410-spi",
  1041. .id = 0,
  1042. .num_resources = ARRAY_SIZE(s3c_spi0_resource),
  1043. .resource = s3c_spi0_resource,
  1044. .dev = {
  1045. .dma_mask = &samsung_device_dma_mask,
  1046. .coherent_dma_mask = DMA_BIT_MASK(32),
  1047. }
  1048. };
  1049. static struct resource s3c_spi1_resource[] = {
  1050. [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI1, SZ_32),
  1051. [1] = DEFINE_RES_IRQ(IRQ_SPI1),
  1052. };
  1053. struct platform_device s3c_device_spi1 = {
  1054. .name = "s3c2410-spi",
  1055. .id = 1,
  1056. .num_resources = ARRAY_SIZE(s3c_spi1_resource),
  1057. .resource = s3c_spi1_resource,
  1058. .dev = {
  1059. .dma_mask = &samsung_device_dma_mask,
  1060. .coherent_dma_mask = DMA_BIT_MASK(32),
  1061. }
  1062. };
  1063. #endif /* CONFIG_PLAT_S3C24XX */
  1064. /* Touchscreen */
  1065. #ifdef CONFIG_PLAT_S3C24XX
  1066. static struct resource s3c_ts_resource[] = {
  1067. [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
  1068. [1] = DEFINE_RES_IRQ(IRQ_TC),
  1069. };
  1070. struct platform_device s3c_device_ts = {
  1071. .name = "s3c2410-ts",
  1072. .id = -1,
  1073. .dev.parent = &s3c_device_adc.dev,
  1074. .num_resources = ARRAY_SIZE(s3c_ts_resource),
  1075. .resource = s3c_ts_resource,
  1076. };
  1077. void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_info)
  1078. {
  1079. s3c_set_platdata(hard_s3c2410ts_info,
  1080. sizeof(struct s3c2410_ts_mach_info), &s3c_device_ts);
  1081. }
  1082. #endif /* CONFIG_PLAT_S3C24XX */
  1083. #ifdef CONFIG_SAMSUNG_DEV_TS
  1084. static struct resource s3c_ts_resource[] = {
  1085. [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
  1086. [1] = DEFINE_RES_IRQ(IRQ_TC),
  1087. };
  1088. static struct s3c2410_ts_mach_info default_ts_data __initdata = {
  1089. .delay = 10000,
  1090. .presc = 49,
  1091. .oversampling_shift = 2,
  1092. };
  1093. struct platform_device s3c_device_ts = {
  1094. .name = "s3c64xx-ts",
  1095. .id = -1,
  1096. .num_resources = ARRAY_SIZE(s3c_ts_resource),
  1097. .resource = s3c_ts_resource,
  1098. };
  1099. void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
  1100. {
  1101. if (!pd)
  1102. pd = &default_ts_data;
  1103. s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info),
  1104. &s3c_device_ts);
  1105. }
  1106. #endif /* CONFIG_SAMSUNG_DEV_TS */
  1107. /* TV */
  1108. #ifdef CONFIG_S5P_DEV_TV
  1109. static struct resource s5p_hdmi_resources[] = {
  1110. [0] = DEFINE_RES_MEM(S5P_PA_HDMI, SZ_1M),
  1111. [1] = DEFINE_RES_IRQ(IRQ_HDMI),
  1112. };
  1113. struct platform_device s5p_device_hdmi = {
  1114. .name = "s5p-hdmi",
  1115. .id = -1,
  1116. .num_resources = ARRAY_SIZE(s5p_hdmi_resources),
  1117. .resource = s5p_hdmi_resources,
  1118. };
  1119. static struct resource s5p_sdo_resources[] = {
  1120. [0] = DEFINE_RES_MEM(S5P_PA_SDO, SZ_64K),
  1121. [1] = DEFINE_RES_IRQ(IRQ_SDO),
  1122. };
  1123. struct platform_device s5p_device_sdo = {
  1124. .name = "s5p-sdo",
  1125. .id = -1,
  1126. .num_resources = ARRAY_SIZE(s5p_sdo_resources),
  1127. .resource = s5p_sdo_resources,
  1128. };
  1129. static struct resource s5p_mixer_resources[] = {
  1130. [0] = DEFINE_RES_MEM_NAMED(S5P_PA_MIXER, SZ_64K, "mxr"),
  1131. [1] = DEFINE_RES_MEM_NAMED(S5P_PA_VP, SZ_64K, "vp"),
  1132. [2] = DEFINE_RES_IRQ_NAMED(IRQ_MIXER, "irq"),
  1133. };
  1134. struct platform_device s5p_device_mixer = {
  1135. .name = "s5p-mixer",
  1136. .id = -1,
  1137. .num_resources = ARRAY_SIZE(s5p_mixer_resources),
  1138. .resource = s5p_mixer_resources,
  1139. .dev = {
  1140. .dma_mask = &samsung_device_dma_mask,
  1141. .coherent_dma_mask = DMA_BIT_MASK(32),
  1142. }
  1143. };
  1144. #endif /* CONFIG_S5P_DEV_TV */
  1145. /* USB */
  1146. #ifdef CONFIG_S3C_DEV_USB_HOST
  1147. static struct resource s3c_usb_resource[] = {
  1148. [0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
  1149. [1] = DEFINE_RES_IRQ(IRQ_USBH),
  1150. };
  1151. struct platform_device s3c_device_ohci = {
  1152. .name = "s3c2410-ohci",
  1153. .id = -1,
  1154. .num_resources = ARRAY_SIZE(s3c_usb_resource),
  1155. .resource = s3c_usb_resource,
  1156. .dev = {
  1157. .dma_mask = &samsung_device_dma_mask,
  1158. .coherent_dma_mask = DMA_BIT_MASK(32),
  1159. }
  1160. };
  1161. /*
  1162. * s3c_ohci_set_platdata - initialise OHCI device platform data
  1163. * @info: The platform data.
  1164. *
  1165. * This call copies the @info passed in and sets the device .platform_data
  1166. * field to that copy. The @info is copied so that the original can be marked
  1167. * __initdata.
  1168. */
  1169. void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info)
  1170. {
  1171. s3c_set_platdata(info, sizeof(struct s3c2410_hcd_info),
  1172. &s3c_device_ohci);
  1173. }
  1174. #endif /* CONFIG_S3C_DEV_USB_HOST */
  1175. /* USB Device (Gadget) */
  1176. #ifdef CONFIG_PLAT_S3C24XX
  1177. static struct resource s3c_usbgadget_resource[] = {
  1178. [0] = DEFINE_RES_MEM(S3C24XX_PA_USBDEV, S3C24XX_SZ_USBDEV),
  1179. [1] = DEFINE_RES_IRQ(IRQ_USBD),
  1180. };
  1181. struct platform_device s3c_device_usbgadget = {
  1182. .name = "s3c2410-usbgadget",
  1183. .id = -1,
  1184. .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
  1185. .resource = s3c_usbgadget_resource,
  1186. };
  1187. void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
  1188. {
  1189. s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usbgadget);
  1190. }
  1191. #endif /* CONFIG_PLAT_S3C24XX */
  1192. /* USB EHCI Host Controller */
  1193. #ifdef CONFIG_S5P_DEV_USB_EHCI
  1194. static struct resource s5p_ehci_resource[] = {
  1195. [0] = DEFINE_RES_MEM(S5P_PA_EHCI, SZ_256),
  1196. [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
  1197. };
  1198. struct platform_device s5p_device_ehci = {
  1199. .name = "s5p-ehci",
  1200. .id = -1,
  1201. .num_resources = ARRAY_SIZE(s5p_ehci_resource),
  1202. .resource = s5p_ehci_resource,
  1203. .dev = {
  1204. .dma_mask = &samsung_device_dma_mask,
  1205. .coherent_dma_mask = DMA_BIT_MASK(32),
  1206. }
  1207. };
  1208. void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd)
  1209. {
  1210. struct s5p_ehci_platdata *npd;
  1211. npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata),
  1212. &s5p_device_ehci);
  1213. if (!npd->phy_init)
  1214. npd->phy_init = s5p_usb_phy_init;
  1215. if (!npd->phy_exit)
  1216. npd->phy_exit = s5p_usb_phy_exit;
  1217. }
  1218. #endif /* CONFIG_S5P_DEV_USB_EHCI */
  1219. /* USB HSOTG */
  1220. #ifdef CONFIG_S3C_DEV_USB_HSOTG
  1221. static struct resource s3c_usb_hsotg_resources[] = {
  1222. [0] = DEFINE_RES_MEM(S3C_PA_USB_HSOTG, SZ_128K),
  1223. [1] = DEFINE_RES_IRQ(IRQ_OTG),
  1224. };
  1225. struct platform_device s3c_device_usb_hsotg = {
  1226. .name = "s3c-hsotg",
  1227. .id = -1,
  1228. .num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources),
  1229. .resource = s3c_usb_hsotg_resources,
  1230. .dev = {
  1231. .dma_mask = &samsung_device_dma_mask,
  1232. .coherent_dma_mask = DMA_BIT_MASK(32),
  1233. },
  1234. };
  1235. void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
  1236. {
  1237. struct s3c_hsotg_plat *npd;
  1238. npd = s3c_set_platdata(pd, sizeof(struct s3c_hsotg_plat),
  1239. &s3c_device_usb_hsotg);
  1240. if (!npd->phy_init)
  1241. npd->phy_init = s5p_usb_phy_init;
  1242. if (!npd->phy_exit)
  1243. npd->phy_exit = s5p_usb_phy_exit;
  1244. }
  1245. #endif /* CONFIG_S3C_DEV_USB_HSOTG */
  1246. /* USB High Spped 2.0 Device (Gadget) */
  1247. #ifdef CONFIG_PLAT_S3C24XX
  1248. static struct resource s3c_hsudc_resource[] = {
  1249. [0] = DEFINE_RES_MEM(S3C2416_PA_HSUDC, S3C2416_SZ_HSUDC),
  1250. [1] = DEFINE_RES_IRQ(IRQ_USBD),
  1251. };
  1252. struct platform_device s3c_device_usb_hsudc = {
  1253. .name = "s3c-hsudc",
  1254. .id = -1,
  1255. .num_resources = ARRAY_SIZE(s3c_hsudc_resource),
  1256. .resource = s3c_hsudc_resource,
  1257. .dev = {
  1258. .dma_mask = &samsung_device_dma_mask,
  1259. .coherent_dma_mask = DMA_BIT_MASK(32),
  1260. },
  1261. };
  1262. void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd)
  1263. {
  1264. s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc);
  1265. }
  1266. #endif /* CONFIG_PLAT_S3C24XX */
  1267. /* WDT */
  1268. #ifdef CONFIG_S3C_DEV_WDT
  1269. static struct resource s3c_wdt_resource[] = {
  1270. [0] = DEFINE_RES_MEM(S3C_PA_WDT, SZ_1K),
  1271. [1] = DEFINE_RES_IRQ(IRQ_WDT),
  1272. };
  1273. struct platform_device s3c_device_wdt = {
  1274. .name = "s3c2410-wdt",
  1275. .id = -1,
  1276. .num_resources = ARRAY_SIZE(s3c_wdt_resource),
  1277. .resource = s3c_wdt_resource,
  1278. };
  1279. #endif /* CONFIG_S3C_DEV_WDT */
  1280. #ifdef CONFIG_S3C64XX_DEV_SPI0
  1281. static struct resource s3c64xx_spi0_resource[] = {
  1282. [0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
  1283. [1] = DEFINE_RES_DMA(DMACH_SPI0_TX),
  1284. [2] = DEFINE_RES_DMA(DMACH_SPI0_RX),
  1285. [3] = DEFINE_RES_IRQ(IRQ_SPI0),
  1286. };
  1287. struct platform_device s3c64xx_device_spi0 = {
  1288. .name = "s3c6410-spi",
  1289. .id = 0,
  1290. .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
  1291. .resource = s3c64xx_spi0_resource,
  1292. .dev = {
  1293. .dma_mask = &samsung_device_dma_mask,
  1294. .coherent_dma_mask = DMA_BIT_MASK(32),
  1295. },
  1296. };
  1297. void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1298. int num_cs)
  1299. {
  1300. struct s3c64xx_spi_info pd;
  1301. /* Reject invalid configuration */
  1302. if (!num_cs || src_clk_nr < 0) {
  1303. pr_err("%s: Invalid SPI configuration\n", __func__);
  1304. return;
  1305. }
  1306. pd.num_cs = num_cs;
  1307. pd.src_clk_nr = src_clk_nr;
  1308. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
  1309. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0);
  1310. }
  1311. #endif /* CONFIG_S3C64XX_DEV_SPI0 */
  1312. #ifdef CONFIG_S3C64XX_DEV_SPI1
  1313. static struct resource s3c64xx_spi1_resource[] = {
  1314. [0] = DEFINE_RES_MEM(S3C_PA_SPI1, SZ_256),
  1315. [1] = DEFINE_RES_DMA(DMACH_SPI1_TX),
  1316. [2] = DEFINE_RES_DMA(DMACH_SPI1_RX),
  1317. [3] = DEFINE_RES_IRQ(IRQ_SPI1),
  1318. };
  1319. struct platform_device s3c64xx_device_spi1 = {
  1320. .name = "s3c6410-spi",
  1321. .id = 1,
  1322. .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
  1323. .resource = s3c64xx_spi1_resource,
  1324. .dev = {
  1325. .dma_mask = &samsung_device_dma_mask,
  1326. .coherent_dma_mask = DMA_BIT_MASK(32),
  1327. },
  1328. };
  1329. void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1330. int num_cs)
  1331. {
  1332. /* Reject invalid configuration */
  1333. if (!num_cs || src_clk_nr < 0) {
  1334. pr_err("%s: Invalid SPI configuration\n", __func__);
  1335. return;
  1336. }
  1337. pd.num_cs = num_cs;
  1338. pd.src_clk_nr = src_clk_nr;
  1339. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio;
  1340. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1);
  1341. }
  1342. #endif /* CONFIG_S3C64XX_DEV_SPI1 */
  1343. #ifdef CONFIG_S3C64XX_DEV_SPI2
  1344. static struct resource s3c64xx_spi2_resource[] = {
  1345. [0] = DEFINE_RES_MEM(S3C_PA_SPI2, SZ_256),
  1346. [1] = DEFINE_RES_DMA(DMACH_SPI2_TX),
  1347. [2] = DEFINE_RES_DMA(DMACH_SPI2_RX),
  1348. [3] = DEFINE_RES_IRQ(IRQ_SPI2),
  1349. };
  1350. struct platform_device s3c64xx_device_spi2 = {
  1351. .name = "s3c6410-spi",
  1352. .id = 2,
  1353. .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource),
  1354. .resource = s3c64xx_spi2_resource,
  1355. .dev = {
  1356. .dma_mask = &samsung_device_dma_mask,
  1357. .coherent_dma_mask = DMA_BIT_MASK(32),
  1358. },
  1359. };
  1360. void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1361. int num_cs)
  1362. {
  1363. struct s3c64xx_spi_info pd;
  1364. /* Reject invalid configuration */
  1365. if (!num_cs || src_clk_nr < 0) {
  1366. pr_err("%s: Invalid SPI configuration\n", __func__);
  1367. return;
  1368. }
  1369. pd.num_cs = num_cs;
  1370. pd.src_clk_nr = src_clk_nr;
  1371. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio;
  1372. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2);
  1373. }
  1374. #endif /* CONFIG_S3C64XX_DEV_SPI2 */