cpu-features.h 4.8 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2003, 2004 Ralf Baechle
  7. * Copyright (C) 2004 Maciej W. Rozycki
  8. */
  9. #ifndef __ASM_CPU_FEATURES_H
  10. #define __ASM_CPU_FEATURES_H
  11. #include <linux/config.h>
  12. #include <asm/cpu.h>
  13. #include <asm/cpu-info.h>
  14. #include <cpu-feature-overrides.h>
  15. /*
  16. * SMP assumption: Options of CPU 0 are a superset of all processors.
  17. * This is true for all known MIPS systems.
  18. */
  19. #ifndef cpu_has_tlb
  20. #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
  21. #endif
  22. #ifndef cpu_has_4kex
  23. #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
  24. #endif
  25. #ifndef cpu_has_4ktlb
  26. #define cpu_has_4ktlb (cpu_data[0].options & MIPS_CPU_4KTLB)
  27. #endif
  28. #ifndef cpu_has_fpu
  29. #define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU)
  30. #endif
  31. #ifndef cpu_has_32fpr
  32. #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
  33. #endif
  34. #ifndef cpu_has_counter
  35. #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
  36. #endif
  37. #ifndef cpu_has_watch
  38. #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
  39. #endif
  40. #ifndef cpu_has_divec
  41. #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
  42. #endif
  43. #ifndef cpu_has_vce
  44. #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
  45. #endif
  46. #ifndef cpu_has_cache_cdex_p
  47. #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
  48. #endif
  49. #ifndef cpu_has_cache_cdex_s
  50. #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
  51. #endif
  52. #ifndef cpu_has_prefetch
  53. #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
  54. #endif
  55. #ifndef cpu_has_mcheck
  56. #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
  57. #endif
  58. #ifndef cpu_has_ejtag
  59. #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
  60. #endif
  61. #ifndef cpu_has_llsc
  62. #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
  63. #endif
  64. #ifndef cpu_has_mips16
  65. #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
  66. #endif
  67. #ifndef cpu_has_mdmx
  68. #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
  69. #endif
  70. #ifndef cpu_has_mips3d
  71. #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
  72. #endif
  73. #ifndef cpu_has_smartmips
  74. #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
  75. #endif
  76. #ifndef cpu_has_vtag_icache
  77. #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
  78. #endif
  79. #ifndef cpu_has_dc_aliases
  80. #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
  81. #endif
  82. #ifndef cpu_has_ic_fills_f_dc
  83. #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
  84. #endif
  85. /*
  86. * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
  87. * such as the R10000 have I-Caches that snoop local stores; the embedded ones
  88. * don't. For maintaining I-cache coherency this means we need to flush the
  89. * D-cache all the way back to whever the I-cache does refills from, so the
  90. * I-cache has a chance to see the new data at all. Then we have to flush the
  91. * I-cache also.
  92. * Note we may have been rescheduled and may no longer be running on the CPU
  93. * that did the store so we can't optimize this into only doing the flush on
  94. * the local CPU.
  95. */
  96. #ifndef cpu_icache_snoops_remote_store
  97. #ifdef CONFIG_SMP
  98. #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
  99. #else
  100. #define cpu_icache_snoops_remote_store 1
  101. #endif
  102. #endif
  103. #ifndef cpu_has_dsp
  104. #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
  105. #endif
  106. #ifdef CONFIG_32BIT
  107. # ifndef cpu_has_nofpuex
  108. # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
  109. # endif
  110. # ifndef cpu_has_64bits
  111. # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
  112. # endif
  113. # ifndef cpu_has_64bit_zero_reg
  114. # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
  115. # endif
  116. # ifndef cpu_has_64bit_gp_regs
  117. # define cpu_has_64bit_gp_regs 0
  118. # endif
  119. # ifndef cpu_has_64bit_addresses
  120. # define cpu_has_64bit_addresses 0
  121. # endif
  122. #endif
  123. #ifdef CONFIG_64BIT
  124. # ifndef cpu_has_nofpuex
  125. # define cpu_has_nofpuex 0
  126. # endif
  127. # ifndef cpu_has_64bits
  128. # define cpu_has_64bits 1
  129. # endif
  130. # ifndef cpu_has_64bit_zero_reg
  131. # define cpu_has_64bit_zero_reg 1
  132. # endif
  133. # ifndef cpu_has_64bit_gp_regs
  134. # define cpu_has_64bit_gp_regs 1
  135. # endif
  136. # ifndef cpu_has_64bit_addresses
  137. # define cpu_has_64bit_addresses 1
  138. # endif
  139. #endif
  140. #ifndef cpu_has_subset_pcaches
  141. #define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES)
  142. #endif
  143. #ifndef cpu_dcache_line_size
  144. #define cpu_dcache_line_size() current_cpu_data.dcache.linesz
  145. #endif
  146. #ifndef cpu_icache_line_size
  147. #define cpu_icache_line_size() current_cpu_data.icache.linesz
  148. #endif
  149. #ifndef cpu_scache_line_size
  150. #define cpu_scache_line_size() current_cpu_data.scache.linesz
  151. #endif
  152. #endif /* __ASM_CPU_FEATURES_H */