pci.c 28 KB

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  1. /* pci.c: UltraSparc PCI controller support.
  2. *
  3. * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
  4. * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
  5. * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
  6. *
  7. * OF tree based PCI bus probing taken from the PowerPC port
  8. * with minor modifications, see there for credits.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/string.h>
  13. #include <linux/sched.h>
  14. #include <linux/capability.h>
  15. #include <linux/errno.h>
  16. #include <linux/smp_lock.h>
  17. #include <linux/msi.h>
  18. #include <linux/irq.h>
  19. #include <linux/init.h>
  20. #include <asm/uaccess.h>
  21. #include <asm/pbm.h>
  22. #include <asm/pgtable.h>
  23. #include <asm/irq.h>
  24. #include <asm/ebus.h>
  25. #include <asm/isa.h>
  26. #include <asm/prom.h>
  27. #include <asm/apb.h>
  28. #include "pci_impl.h"
  29. unsigned long pci_memspace_mask = 0xffffffffUL;
  30. #ifndef CONFIG_PCI
  31. /* A "nop" PCI implementation. */
  32. asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
  33. unsigned long off, unsigned long len,
  34. unsigned char *buf)
  35. {
  36. return 0;
  37. }
  38. asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
  39. unsigned long off, unsigned long len,
  40. unsigned char *buf)
  41. {
  42. return 0;
  43. }
  44. #else
  45. /* List of all PCI controllers found in the system. */
  46. struct pci_controller_info *pci_controller_root = NULL;
  47. /* Each PCI controller found gets a unique index. */
  48. int pci_num_controllers = 0;
  49. volatile int pci_poke_in_progress;
  50. volatile int pci_poke_cpu = -1;
  51. volatile int pci_poke_faulted;
  52. static DEFINE_SPINLOCK(pci_poke_lock);
  53. void pci_config_read8(u8 *addr, u8 *ret)
  54. {
  55. unsigned long flags;
  56. u8 byte;
  57. spin_lock_irqsave(&pci_poke_lock, flags);
  58. pci_poke_cpu = smp_processor_id();
  59. pci_poke_in_progress = 1;
  60. pci_poke_faulted = 0;
  61. __asm__ __volatile__("membar #Sync\n\t"
  62. "lduba [%1] %2, %0\n\t"
  63. "membar #Sync"
  64. : "=r" (byte)
  65. : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  66. : "memory");
  67. pci_poke_in_progress = 0;
  68. pci_poke_cpu = -1;
  69. if (!pci_poke_faulted)
  70. *ret = byte;
  71. spin_unlock_irqrestore(&pci_poke_lock, flags);
  72. }
  73. void pci_config_read16(u16 *addr, u16 *ret)
  74. {
  75. unsigned long flags;
  76. u16 word;
  77. spin_lock_irqsave(&pci_poke_lock, flags);
  78. pci_poke_cpu = smp_processor_id();
  79. pci_poke_in_progress = 1;
  80. pci_poke_faulted = 0;
  81. __asm__ __volatile__("membar #Sync\n\t"
  82. "lduha [%1] %2, %0\n\t"
  83. "membar #Sync"
  84. : "=r" (word)
  85. : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  86. : "memory");
  87. pci_poke_in_progress = 0;
  88. pci_poke_cpu = -1;
  89. if (!pci_poke_faulted)
  90. *ret = word;
  91. spin_unlock_irqrestore(&pci_poke_lock, flags);
  92. }
  93. void pci_config_read32(u32 *addr, u32 *ret)
  94. {
  95. unsigned long flags;
  96. u32 dword;
  97. spin_lock_irqsave(&pci_poke_lock, flags);
  98. pci_poke_cpu = smp_processor_id();
  99. pci_poke_in_progress = 1;
  100. pci_poke_faulted = 0;
  101. __asm__ __volatile__("membar #Sync\n\t"
  102. "lduwa [%1] %2, %0\n\t"
  103. "membar #Sync"
  104. : "=r" (dword)
  105. : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  106. : "memory");
  107. pci_poke_in_progress = 0;
  108. pci_poke_cpu = -1;
  109. if (!pci_poke_faulted)
  110. *ret = dword;
  111. spin_unlock_irqrestore(&pci_poke_lock, flags);
  112. }
  113. void pci_config_write8(u8 *addr, u8 val)
  114. {
  115. unsigned long flags;
  116. spin_lock_irqsave(&pci_poke_lock, flags);
  117. pci_poke_cpu = smp_processor_id();
  118. pci_poke_in_progress = 1;
  119. pci_poke_faulted = 0;
  120. __asm__ __volatile__("membar #Sync\n\t"
  121. "stba %0, [%1] %2\n\t"
  122. "membar #Sync"
  123. : /* no outputs */
  124. : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  125. : "memory");
  126. pci_poke_in_progress = 0;
  127. pci_poke_cpu = -1;
  128. spin_unlock_irqrestore(&pci_poke_lock, flags);
  129. }
  130. void pci_config_write16(u16 *addr, u16 val)
  131. {
  132. unsigned long flags;
  133. spin_lock_irqsave(&pci_poke_lock, flags);
  134. pci_poke_cpu = smp_processor_id();
  135. pci_poke_in_progress = 1;
  136. pci_poke_faulted = 0;
  137. __asm__ __volatile__("membar #Sync\n\t"
  138. "stha %0, [%1] %2\n\t"
  139. "membar #Sync"
  140. : /* no outputs */
  141. : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  142. : "memory");
  143. pci_poke_in_progress = 0;
  144. pci_poke_cpu = -1;
  145. spin_unlock_irqrestore(&pci_poke_lock, flags);
  146. }
  147. void pci_config_write32(u32 *addr, u32 val)
  148. {
  149. unsigned long flags;
  150. spin_lock_irqsave(&pci_poke_lock, flags);
  151. pci_poke_cpu = smp_processor_id();
  152. pci_poke_in_progress = 1;
  153. pci_poke_faulted = 0;
  154. __asm__ __volatile__("membar #Sync\n\t"
  155. "stwa %0, [%1] %2\n\t"
  156. "membar #Sync"
  157. : /* no outputs */
  158. : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  159. : "memory");
  160. pci_poke_in_progress = 0;
  161. pci_poke_cpu = -1;
  162. spin_unlock_irqrestore(&pci_poke_lock, flags);
  163. }
  164. /* Probe for all PCI controllers in the system. */
  165. extern void sabre_init(struct device_node *, const char *);
  166. extern void psycho_init(struct device_node *, const char *);
  167. extern void schizo_init(struct device_node *, const char *);
  168. extern void schizo_plus_init(struct device_node *, const char *);
  169. extern void tomatillo_init(struct device_node *, const char *);
  170. extern void sun4v_pci_init(struct device_node *, const char *);
  171. static struct {
  172. char *model_name;
  173. void (*init)(struct device_node *, const char *);
  174. } pci_controller_table[] __initdata = {
  175. { "SUNW,sabre", sabre_init },
  176. { "pci108e,a000", sabre_init },
  177. { "pci108e,a001", sabre_init },
  178. { "SUNW,psycho", psycho_init },
  179. { "pci108e,8000", psycho_init },
  180. { "SUNW,schizo", schizo_init },
  181. { "pci108e,8001", schizo_init },
  182. { "SUNW,schizo+", schizo_plus_init },
  183. { "pci108e,8002", schizo_plus_init },
  184. { "SUNW,tomatillo", tomatillo_init },
  185. { "pci108e,a801", tomatillo_init },
  186. { "SUNW,sun4v-pci", sun4v_pci_init },
  187. };
  188. #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
  189. sizeof(pci_controller_table[0]))
  190. static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
  191. {
  192. int i;
  193. for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
  194. if (!strncmp(model_name,
  195. pci_controller_table[i].model_name,
  196. namelen)) {
  197. pci_controller_table[i].init(dp, model_name);
  198. return 1;
  199. }
  200. }
  201. return 0;
  202. }
  203. static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp)
  204. {
  205. int i;
  206. for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
  207. if (!strncmp(model_name,
  208. pci_controller_table[i].model_name,
  209. namelen)) {
  210. return 1;
  211. }
  212. }
  213. return 0;
  214. }
  215. static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
  216. {
  217. struct device_node *dp;
  218. int count = 0;
  219. for_each_node_by_name(dp, "pci") {
  220. struct property *prop;
  221. int len;
  222. prop = of_find_property(dp, "model", &len);
  223. if (!prop)
  224. prop = of_find_property(dp, "compatible", &len);
  225. if (prop) {
  226. const char *model = prop->value;
  227. int item_len = 0;
  228. /* Our value may be a multi-valued string in the
  229. * case of some compatible properties. For sanity,
  230. * only try the first one.
  231. */
  232. while (model[item_len] && len) {
  233. len--;
  234. item_len++;
  235. }
  236. if (handler(model, item_len, dp))
  237. count++;
  238. }
  239. }
  240. return count;
  241. }
  242. /* Is there some PCI controller in the system? */
  243. int __init pcic_present(void)
  244. {
  245. return pci_controller_scan(pci_is_controller);
  246. }
  247. struct pci_iommu_ops *pci_iommu_ops;
  248. EXPORT_SYMBOL(pci_iommu_ops);
  249. extern struct pci_iommu_ops pci_sun4u_iommu_ops,
  250. pci_sun4v_iommu_ops;
  251. /* Find each controller in the system, attach and initialize
  252. * software state structure for each and link into the
  253. * pci_controller_root. Setup the controller enough such
  254. * that bus scanning can be done.
  255. */
  256. static void __init pci_controller_probe(void)
  257. {
  258. if (tlb_type == hypervisor)
  259. pci_iommu_ops = &pci_sun4v_iommu_ops;
  260. else
  261. pci_iommu_ops = &pci_sun4u_iommu_ops;
  262. printk("PCI: Probing for controllers.\n");
  263. pci_controller_scan(pci_controller_init);
  264. }
  265. static unsigned long pci_parse_of_flags(u32 addr0)
  266. {
  267. unsigned long flags = 0;
  268. if (addr0 & 0x02000000) {
  269. flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
  270. flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
  271. flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
  272. if (addr0 & 0x40000000)
  273. flags |= IORESOURCE_PREFETCH
  274. | PCI_BASE_ADDRESS_MEM_PREFETCH;
  275. } else if (addr0 & 0x01000000)
  276. flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
  277. return flags;
  278. }
  279. /* The of_device layer has translated all of the assigned-address properties
  280. * into physical address resources, we only have to figure out the register
  281. * mapping.
  282. */
  283. static void pci_parse_of_addrs(struct of_device *op,
  284. struct device_node *node,
  285. struct pci_dev *dev)
  286. {
  287. struct resource *op_res;
  288. const u32 *addrs;
  289. int proplen;
  290. addrs = of_get_property(node, "assigned-addresses", &proplen);
  291. if (!addrs)
  292. return;
  293. printk(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
  294. op_res = &op->resource[0];
  295. for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
  296. struct resource *res;
  297. unsigned long flags;
  298. int i;
  299. flags = pci_parse_of_flags(addrs[0]);
  300. if (!flags)
  301. continue;
  302. i = addrs[0] & 0xff;
  303. printk(" start: %lx, end: %lx, i: %x\n",
  304. op_res->start, op_res->end, i);
  305. if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
  306. res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
  307. } else if (i == dev->rom_base_reg) {
  308. res = &dev->resource[PCI_ROM_RESOURCE];
  309. flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
  310. } else {
  311. printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
  312. continue;
  313. }
  314. res->start = op_res->start;
  315. res->end = op_res->end;
  316. res->flags = flags;
  317. res->name = pci_name(dev);
  318. }
  319. }
  320. struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
  321. struct device_node *node,
  322. struct pci_bus *bus, int devfn)
  323. {
  324. struct dev_archdata *sd;
  325. struct pci_dev *dev;
  326. const char *type;
  327. u32 class;
  328. dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
  329. if (!dev)
  330. return NULL;
  331. sd = &dev->dev.archdata;
  332. sd->iommu = pbm->iommu;
  333. sd->stc = &pbm->stc;
  334. sd->host_controller = pbm;
  335. sd->prom_node = node;
  336. sd->op = of_find_device_by_node(node);
  337. sd->msi_num = 0xffffffff;
  338. type = of_get_property(node, "device_type", NULL);
  339. if (type == NULL)
  340. type = "";
  341. printk(" create device, devfn: %x, type: %s\n", devfn, type);
  342. dev->bus = bus;
  343. dev->sysdata = node;
  344. dev->dev.parent = bus->bridge;
  345. dev->dev.bus = &pci_bus_type;
  346. dev->devfn = devfn;
  347. dev->multifunction = 0; /* maybe a lie? */
  348. dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
  349. dev->device = of_getintprop_default(node, "device-id", 0xffff);
  350. dev->subsystem_vendor =
  351. of_getintprop_default(node, "subsystem-vendor-id", 0);
  352. dev->subsystem_device =
  353. of_getintprop_default(node, "subsystem-id", 0);
  354. dev->cfg_size = pci_cfg_space_size(dev);
  355. sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
  356. dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
  357. /* dev->class = of_getintprop_default(node, "class-code", 0); */
  358. /* We can't actually use the firmware value, we have to read what
  359. * is in the register right now. One reason is that in the case
  360. * of IDE interfaces the firmware can sample the value before the
  361. * the IDE interface is programmed into native mode.
  362. */
  363. pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
  364. dev->class = class >> 8;
  365. printk(" class: 0x%x\n", dev->class);
  366. dev->current_state = 4; /* unknown power state */
  367. dev->error_state = pci_channel_io_normal;
  368. if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
  369. /* a PCI-PCI bridge */
  370. dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
  371. dev->rom_base_reg = PCI_ROM_ADDRESS1;
  372. } else if (!strcmp(type, "cardbus")) {
  373. dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
  374. } else {
  375. dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
  376. dev->rom_base_reg = PCI_ROM_ADDRESS;
  377. dev->irq = sd->op->irqs[0];
  378. if (dev->irq == 0xffffffff)
  379. dev->irq = PCI_IRQ_NONE;
  380. }
  381. pci_parse_of_addrs(sd->op, node, dev);
  382. printk(" adding to system ...\n");
  383. pci_device_add(dev, bus);
  384. return dev;
  385. }
  386. static void __init apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
  387. {
  388. u32 idx, first, last;
  389. first = 8;
  390. last = 0;
  391. for (idx = 0; idx < 8; idx++) {
  392. if ((map & (1 << idx)) != 0) {
  393. if (first > idx)
  394. first = idx;
  395. if (last < idx)
  396. last = idx;
  397. }
  398. }
  399. *first_p = first;
  400. *last_p = last;
  401. }
  402. /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
  403. * a proper 'ranges' property.
  404. */
  405. static void __init apb_fake_ranges(struct pci_dev *dev,
  406. struct pci_bus *bus,
  407. struct pci_pbm_info *pbm)
  408. {
  409. struct resource *res;
  410. u32 first, last;
  411. u8 map;
  412. pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
  413. apb_calc_first_last(map, &first, &last);
  414. res = bus->resource[0];
  415. res->start = (first << 21);
  416. res->end = (last << 21) + ((1 << 21) - 1);
  417. res->flags = IORESOURCE_IO;
  418. pbm->parent->resource_adjust(dev, res, &pbm->io_space);
  419. pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
  420. apb_calc_first_last(map, &first, &last);
  421. res = bus->resource[1];
  422. res->start = (first << 21);
  423. res->end = (last << 21) + ((1 << 21) - 1);
  424. res->flags = IORESOURCE_MEM;
  425. pbm->parent->resource_adjust(dev, res, &pbm->mem_space);
  426. }
  427. static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
  428. struct device_node *node,
  429. struct pci_bus *bus);
  430. #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
  431. void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
  432. struct device_node *node,
  433. struct pci_dev *dev)
  434. {
  435. struct pci_bus *bus;
  436. const u32 *busrange, *ranges;
  437. int len, i, simba;
  438. struct resource *res;
  439. unsigned int flags;
  440. u64 size;
  441. printk("of_scan_pci_bridge(%s)\n", node->full_name);
  442. /* parse bus-range property */
  443. busrange = of_get_property(node, "bus-range", &len);
  444. if (busrange == NULL || len != 8) {
  445. printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
  446. node->full_name);
  447. return;
  448. }
  449. ranges = of_get_property(node, "ranges", &len);
  450. simba = 0;
  451. if (ranges == NULL) {
  452. char *model = of_get_property(node, "model", NULL);
  453. if (model && !strcmp(model, "SUNW,simba")) {
  454. simba = 1;
  455. } else {
  456. printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
  457. node->full_name);
  458. return;
  459. }
  460. }
  461. bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
  462. if (!bus) {
  463. printk(KERN_ERR "Failed to create pci bus for %s\n",
  464. node->full_name);
  465. return;
  466. }
  467. bus->primary = dev->bus->number;
  468. bus->subordinate = busrange[1];
  469. bus->bridge_ctl = 0;
  470. /* parse ranges property, or cook one up by hand for Simba */
  471. /* PCI #address-cells == 3 and #size-cells == 2 always */
  472. res = &dev->resource[PCI_BRIDGE_RESOURCES];
  473. for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
  474. res->flags = 0;
  475. bus->resource[i] = res;
  476. ++res;
  477. }
  478. if (simba) {
  479. apb_fake_ranges(dev, bus, pbm);
  480. goto simba_cont;
  481. }
  482. i = 1;
  483. for (; len >= 32; len -= 32, ranges += 8) {
  484. struct resource *root;
  485. flags = pci_parse_of_flags(ranges[0]);
  486. size = GET_64BIT(ranges, 6);
  487. if (flags == 0 || size == 0)
  488. continue;
  489. if (flags & IORESOURCE_IO) {
  490. res = bus->resource[0];
  491. if (res->flags) {
  492. printk(KERN_ERR "PCI: ignoring extra I/O range"
  493. " for bridge %s\n", node->full_name);
  494. continue;
  495. }
  496. root = &pbm->io_space;
  497. } else {
  498. if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
  499. printk(KERN_ERR "PCI: too many memory ranges"
  500. " for bridge %s\n", node->full_name);
  501. continue;
  502. }
  503. res = bus->resource[i];
  504. ++i;
  505. root = &pbm->mem_space;
  506. }
  507. res->start = GET_64BIT(ranges, 1);
  508. res->end = res->start + size - 1;
  509. res->flags = flags;
  510. /* Another way to implement this would be to add an of_device
  511. * layer routine that can calculate a resource for a given
  512. * range property value in a PCI device.
  513. */
  514. pbm->parent->resource_adjust(dev, res, root);
  515. }
  516. simba_cont:
  517. sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
  518. bus->number);
  519. printk(" bus name: %s\n", bus->name);
  520. pci_of_scan_bus(pbm, node, bus);
  521. }
  522. static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
  523. struct device_node *node,
  524. struct pci_bus *bus)
  525. {
  526. struct device_node *child;
  527. const u32 *reg;
  528. int reglen, devfn;
  529. struct pci_dev *dev;
  530. printk("PCI: scan_bus[%s] bus no %d\n",
  531. node->full_name, bus->number);
  532. child = NULL;
  533. while ((child = of_get_next_child(node, child)) != NULL) {
  534. printk(" * %s\n", child->full_name);
  535. reg = of_get_property(child, "reg", &reglen);
  536. if (reg == NULL || reglen < 20)
  537. continue;
  538. devfn = (reg[0] >> 8) & 0xff;
  539. /* create a new pci_dev for this device */
  540. dev = of_create_pci_dev(pbm, child, bus, devfn);
  541. if (!dev)
  542. continue;
  543. printk("PCI: dev header type: %x\n", dev->hdr_type);
  544. if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
  545. dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
  546. of_scan_pci_bridge(pbm, child, dev);
  547. }
  548. }
  549. static ssize_t
  550. show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
  551. {
  552. struct pci_dev *pdev;
  553. struct device_node *dp;
  554. pdev = to_pci_dev(dev);
  555. dp = pdev->dev.archdata.prom_node;
  556. return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
  557. }
  558. static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
  559. static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
  560. {
  561. struct pci_dev *dev;
  562. struct pci_bus *child_bus;
  563. int err;
  564. list_for_each_entry(dev, &bus->devices, bus_list) {
  565. /* we don't really care if we can create this file or
  566. * not, but we need to assign the result of the call
  567. * or the world will fall under alien invasion and
  568. * everybody will be frozen on a spaceship ready to be
  569. * eaten on alpha centauri by some green and jelly
  570. * humanoid.
  571. */
  572. err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
  573. }
  574. list_for_each_entry(child_bus, &bus->children, node)
  575. pci_bus_register_of_sysfs(child_bus);
  576. }
  577. struct pci_bus * __init pci_scan_one_pbm(struct pci_pbm_info *pbm)
  578. {
  579. struct pci_controller_info *p = pbm->parent;
  580. struct device_node *node = pbm->prom_node;
  581. struct pci_bus *bus;
  582. printk("PCI: Scanning PBM %s\n", node->full_name);
  583. /* XXX parent device? XXX */
  584. bus = pci_create_bus(NULL, pbm->pci_first_busno, p->pci_ops, pbm);
  585. if (!bus) {
  586. printk(KERN_ERR "Failed to create bus for %s\n",
  587. node->full_name);
  588. return NULL;
  589. }
  590. bus->secondary = pbm->pci_first_busno;
  591. bus->subordinate = pbm->pci_last_busno;
  592. bus->resource[0] = &pbm->io_space;
  593. bus->resource[1] = &pbm->mem_space;
  594. pci_of_scan_bus(pbm, node, bus);
  595. pci_bus_add_devices(bus);
  596. pci_bus_register_of_sysfs(bus);
  597. return bus;
  598. }
  599. static void __init pci_scan_each_controller_bus(void)
  600. {
  601. struct pci_controller_info *p;
  602. for (p = pci_controller_root; p; p = p->next)
  603. p->scan_bus(p);
  604. }
  605. extern void power_init(void);
  606. static int __init pcibios_init(void)
  607. {
  608. pci_controller_probe();
  609. if (pci_controller_root == NULL)
  610. return 0;
  611. pci_scan_each_controller_bus();
  612. isa_init();
  613. ebus_init();
  614. power_init();
  615. return 0;
  616. }
  617. subsys_initcall(pcibios_init);
  618. void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
  619. {
  620. struct pci_pbm_info *pbm = pbus->sysdata;
  621. /* Generic PCI bus probing sets these to point at
  622. * &io{port,mem}_resouce which is wrong for us.
  623. */
  624. pbus->resource[0] = &pbm->io_space;
  625. pbus->resource[1] = &pbm->mem_space;
  626. }
  627. struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
  628. {
  629. struct pci_pbm_info *pbm = pdev->bus->sysdata;
  630. struct resource *root = NULL;
  631. if (r->flags & IORESOURCE_IO)
  632. root = &pbm->io_space;
  633. if (r->flags & IORESOURCE_MEM)
  634. root = &pbm->mem_space;
  635. return root;
  636. }
  637. void pcibios_update_irq(struct pci_dev *pdev, int irq)
  638. {
  639. }
  640. void pcibios_align_resource(void *data, struct resource *res,
  641. resource_size_t size, resource_size_t align)
  642. {
  643. }
  644. int pcibios_enable_device(struct pci_dev *dev, int mask)
  645. {
  646. u16 cmd, oldcmd;
  647. int i;
  648. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  649. oldcmd = cmd;
  650. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  651. struct resource *res = &dev->resource[i];
  652. /* Only set up the requested stuff */
  653. if (!(mask & (1<<i)))
  654. continue;
  655. if (res->flags & IORESOURCE_IO)
  656. cmd |= PCI_COMMAND_IO;
  657. if (res->flags & IORESOURCE_MEM)
  658. cmd |= PCI_COMMAND_MEMORY;
  659. }
  660. if (cmd != oldcmd) {
  661. printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
  662. pci_name(dev), cmd);
  663. /* Enable the appropriate bits in the PCI command register. */
  664. pci_write_config_word(dev, PCI_COMMAND, cmd);
  665. }
  666. return 0;
  667. }
  668. void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
  669. struct resource *res)
  670. {
  671. struct pci_pbm_info *pbm = pdev->bus->sysdata;
  672. struct resource zero_res, *root;
  673. zero_res.start = 0;
  674. zero_res.end = 0;
  675. zero_res.flags = res->flags;
  676. if (res->flags & IORESOURCE_IO)
  677. root = &pbm->io_space;
  678. else
  679. root = &pbm->mem_space;
  680. pbm->parent->resource_adjust(pdev, &zero_res, root);
  681. region->start = res->start - zero_res.start;
  682. region->end = res->end - zero_res.start;
  683. }
  684. EXPORT_SYMBOL(pcibios_resource_to_bus);
  685. void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
  686. struct pci_bus_region *region)
  687. {
  688. struct pci_pbm_info *pbm = pdev->bus->sysdata;
  689. struct resource *root;
  690. res->start = region->start;
  691. res->end = region->end;
  692. if (res->flags & IORESOURCE_IO)
  693. root = &pbm->io_space;
  694. else
  695. root = &pbm->mem_space;
  696. pbm->parent->resource_adjust(pdev, res, root);
  697. }
  698. EXPORT_SYMBOL(pcibios_bus_to_resource);
  699. char * __devinit pcibios_setup(char *str)
  700. {
  701. return str;
  702. }
  703. /* Platform support for /proc/bus/pci/X/Y mmap()s. */
  704. /* If the user uses a host-bridge as the PCI device, he may use
  705. * this to perform a raw mmap() of the I/O or MEM space behind
  706. * that controller.
  707. *
  708. * This can be useful for execution of x86 PCI bios initialization code
  709. * on a PCI card, like the xfree86 int10 stuff does.
  710. */
  711. static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
  712. enum pci_mmap_state mmap_state)
  713. {
  714. struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
  715. struct pci_controller_info *p;
  716. unsigned long space_size, user_offset, user_size;
  717. p = pbm->parent;
  718. if (p->pbms_same_domain) {
  719. unsigned long lowest, highest;
  720. lowest = ~0UL; highest = 0UL;
  721. if (mmap_state == pci_mmap_io) {
  722. if (p->pbm_A.io_space.flags) {
  723. lowest = p->pbm_A.io_space.start;
  724. highest = p->pbm_A.io_space.end + 1;
  725. }
  726. if (p->pbm_B.io_space.flags) {
  727. if (lowest > p->pbm_B.io_space.start)
  728. lowest = p->pbm_B.io_space.start;
  729. if (highest < p->pbm_B.io_space.end + 1)
  730. highest = p->pbm_B.io_space.end + 1;
  731. }
  732. space_size = highest - lowest;
  733. } else {
  734. if (p->pbm_A.mem_space.flags) {
  735. lowest = p->pbm_A.mem_space.start;
  736. highest = p->pbm_A.mem_space.end + 1;
  737. }
  738. if (p->pbm_B.mem_space.flags) {
  739. if (lowest > p->pbm_B.mem_space.start)
  740. lowest = p->pbm_B.mem_space.start;
  741. if (highest < p->pbm_B.mem_space.end + 1)
  742. highest = p->pbm_B.mem_space.end + 1;
  743. }
  744. space_size = highest - lowest;
  745. }
  746. } else {
  747. if (mmap_state == pci_mmap_io) {
  748. space_size = (pbm->io_space.end -
  749. pbm->io_space.start) + 1;
  750. } else {
  751. space_size = (pbm->mem_space.end -
  752. pbm->mem_space.start) + 1;
  753. }
  754. }
  755. /* Make sure the request is in range. */
  756. user_offset = vma->vm_pgoff << PAGE_SHIFT;
  757. user_size = vma->vm_end - vma->vm_start;
  758. if (user_offset >= space_size ||
  759. (user_offset + user_size) > space_size)
  760. return -EINVAL;
  761. if (p->pbms_same_domain) {
  762. unsigned long lowest = ~0UL;
  763. if (mmap_state == pci_mmap_io) {
  764. if (p->pbm_A.io_space.flags)
  765. lowest = p->pbm_A.io_space.start;
  766. if (p->pbm_B.io_space.flags &&
  767. lowest > p->pbm_B.io_space.start)
  768. lowest = p->pbm_B.io_space.start;
  769. } else {
  770. if (p->pbm_A.mem_space.flags)
  771. lowest = p->pbm_A.mem_space.start;
  772. if (p->pbm_B.mem_space.flags &&
  773. lowest > p->pbm_B.mem_space.start)
  774. lowest = p->pbm_B.mem_space.start;
  775. }
  776. vma->vm_pgoff = (lowest + user_offset) >> PAGE_SHIFT;
  777. } else {
  778. if (mmap_state == pci_mmap_io) {
  779. vma->vm_pgoff = (pbm->io_space.start +
  780. user_offset) >> PAGE_SHIFT;
  781. } else {
  782. vma->vm_pgoff = (pbm->mem_space.start +
  783. user_offset) >> PAGE_SHIFT;
  784. }
  785. }
  786. return 0;
  787. }
  788. /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
  789. * to the 32-bit pci bus offset for DEV requested by the user.
  790. *
  791. * Basically, the user finds the base address for his device which he wishes
  792. * to mmap. They read the 32-bit value from the config space base register,
  793. * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
  794. * offset parameter of mmap on /proc/bus/pci/XXX for that device.
  795. *
  796. * Returns negative error code on failure, zero on success.
  797. */
  798. static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
  799. enum pci_mmap_state mmap_state)
  800. {
  801. unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
  802. unsigned long user32 = user_offset & pci_memspace_mask;
  803. unsigned long largest_base, this_base, addr32;
  804. int i;
  805. if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
  806. return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
  807. /* Figure out which base address this is for. */
  808. largest_base = 0UL;
  809. for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
  810. struct resource *rp = &dev->resource[i];
  811. /* Active? */
  812. if (!rp->flags)
  813. continue;
  814. /* Same type? */
  815. if (i == PCI_ROM_RESOURCE) {
  816. if (mmap_state != pci_mmap_mem)
  817. continue;
  818. } else {
  819. if ((mmap_state == pci_mmap_io &&
  820. (rp->flags & IORESOURCE_IO) == 0) ||
  821. (mmap_state == pci_mmap_mem &&
  822. (rp->flags & IORESOURCE_MEM) == 0))
  823. continue;
  824. }
  825. this_base = rp->start;
  826. addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
  827. if (mmap_state == pci_mmap_io)
  828. addr32 &= 0xffffff;
  829. if (addr32 <= user32 && this_base > largest_base)
  830. largest_base = this_base;
  831. }
  832. if (largest_base == 0UL)
  833. return -EINVAL;
  834. /* Now construct the final physical address. */
  835. if (mmap_state == pci_mmap_io)
  836. vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
  837. else
  838. vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
  839. return 0;
  840. }
  841. /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
  842. * mapping.
  843. */
  844. static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
  845. enum pci_mmap_state mmap_state)
  846. {
  847. vma->vm_flags |= (VM_IO | VM_RESERVED);
  848. }
  849. /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
  850. * device mapping.
  851. */
  852. static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
  853. enum pci_mmap_state mmap_state)
  854. {
  855. /* Our io_remap_pfn_range takes care of this, do nothing. */
  856. }
  857. /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
  858. * for this architecture. The region in the process to map is described by vm_start
  859. * and vm_end members of VMA, the base physical address is found in vm_pgoff.
  860. * The pci device structure is provided so that architectures may make mapping
  861. * decisions on a per-device or per-bus basis.
  862. *
  863. * Returns a negative error code on failure, zero on success.
  864. */
  865. int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
  866. enum pci_mmap_state mmap_state,
  867. int write_combine)
  868. {
  869. int ret;
  870. ret = __pci_mmap_make_offset(dev, vma, mmap_state);
  871. if (ret < 0)
  872. return ret;
  873. __pci_mmap_set_flags(dev, vma, mmap_state);
  874. __pci_mmap_set_pgprot(dev, vma, mmap_state);
  875. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  876. ret = io_remap_pfn_range(vma, vma->vm_start,
  877. vma->vm_pgoff,
  878. vma->vm_end - vma->vm_start,
  879. vma->vm_page_prot);
  880. if (ret)
  881. return ret;
  882. return 0;
  883. }
  884. /* Return the domain nuber for this pci bus */
  885. int pci_domain_nr(struct pci_bus *pbus)
  886. {
  887. struct pci_pbm_info *pbm = pbus->sysdata;
  888. int ret;
  889. if (pbm == NULL || pbm->parent == NULL) {
  890. ret = -ENXIO;
  891. } else {
  892. struct pci_controller_info *p = pbm->parent;
  893. ret = p->index;
  894. if (p->pbms_same_domain == 0)
  895. ret = ((ret << 1) +
  896. ((pbm == &pbm->parent->pbm_B) ? 1 : 0));
  897. }
  898. return ret;
  899. }
  900. EXPORT_SYMBOL(pci_domain_nr);
  901. #ifdef CONFIG_PCI_MSI
  902. int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
  903. {
  904. struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
  905. struct pci_controller_info *p = pbm->parent;
  906. int virt_irq, err;
  907. if (!pbm->msi_num || !p->setup_msi_irq)
  908. return -EINVAL;
  909. err = p->setup_msi_irq(&virt_irq, pdev, desc);
  910. if (err < 0)
  911. return err;
  912. return virt_irq;
  913. }
  914. void arch_teardown_msi_irq(unsigned int virt_irq)
  915. {
  916. struct msi_desc *entry = get_irq_msi(virt_irq);
  917. struct pci_dev *pdev = entry->dev;
  918. struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
  919. struct pci_controller_info *p = pbm->parent;
  920. if (!pbm->msi_num || !p->setup_msi_irq)
  921. return;
  922. return p->teardown_msi_irq(virt_irq, pdev);
  923. }
  924. #endif /* !(CONFIG_PCI_MSI) */
  925. struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
  926. {
  927. return pdev->dev.archdata.prom_node;
  928. }
  929. EXPORT_SYMBOL(pci_device_to_OF_node);
  930. #endif /* !(CONFIG_PCI) */