ci13xxx_udc.c 72 KB

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  1. /*
  2. * ci13xxx_udc.c - MIPS USB IP core family device controller
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. /*
  13. * Description: MIPS USB IP core family device controller
  14. * Currently it only supports IP part number CI13412
  15. *
  16. * This driver is composed of several blocks:
  17. * - HW: hardware interface
  18. * - DBG: debug facilities (optional)
  19. * - UTIL: utilities
  20. * - ISR: interrupts handling
  21. * - ENDPT: endpoint operations (Gadget API)
  22. * - GADGET: gadget operations (Gadget API)
  23. * - BUS: bus glue code, bus abstraction layer
  24. *
  25. * Compile Options
  26. * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
  27. * - STALL_IN: non-empty bulk-in pipes cannot be halted
  28. * if defined mass storage compliance succeeds but with warnings
  29. * => case 4: Hi > Dn
  30. * => case 5: Hi > Di
  31. * => case 8: Hi <> Do
  32. * if undefined usbtest 13 fails
  33. * - TRACE: enable function tracing (depends on DEBUG)
  34. *
  35. * Main Features
  36. * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
  37. * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
  38. * - Normal & LPM support
  39. *
  40. * USBTEST Report
  41. * - OK: 0-12, 13 (STALL_IN defined) & 14
  42. * - Not Supported: 15 & 16 (ISO)
  43. *
  44. * TODO List
  45. * - OTG
  46. * - Isochronous & Interrupt Traffic
  47. * - Handle requests which spawns into several TDs
  48. * - GET_STATUS(device) - always reports 0
  49. * - Gadget API (majority of optional features)
  50. * - Suspend & Remote Wakeup
  51. */
  52. #include <linux/delay.h>
  53. #include <linux/device.h>
  54. #include <linux/dmapool.h>
  55. #include <linux/dma-mapping.h>
  56. #include <linux/init.h>
  57. #include <linux/interrupt.h>
  58. #include <linux/io.h>
  59. #include <linux/irq.h>
  60. #include <linux/kernel.h>
  61. #include <linux/slab.h>
  62. #include <linux/pm_runtime.h>
  63. #include <linux/usb/ch9.h>
  64. #include <linux/usb/gadget.h>
  65. #include <linux/usb/otg.h>
  66. #include "ci13xxx_udc.h"
  67. /******************************************************************************
  68. * DEFINE
  69. *****************************************************************************/
  70. #define DMA_ADDR_INVALID (~(dma_addr_t)0)
  71. /* ctrl register bank access */
  72. static DEFINE_SPINLOCK(udc_lock);
  73. /* control endpoint description */
  74. static const struct usb_endpoint_descriptor
  75. ctrl_endpt_out_desc = {
  76. .bLength = USB_DT_ENDPOINT_SIZE,
  77. .bDescriptorType = USB_DT_ENDPOINT,
  78. .bEndpointAddress = USB_DIR_OUT,
  79. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  80. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  81. };
  82. static const struct usb_endpoint_descriptor
  83. ctrl_endpt_in_desc = {
  84. .bLength = USB_DT_ENDPOINT_SIZE,
  85. .bDescriptorType = USB_DT_ENDPOINT,
  86. .bEndpointAddress = USB_DIR_IN,
  87. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  88. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  89. };
  90. /* UDC descriptor */
  91. static struct ci13xxx *_udc;
  92. /* Interrupt statistics */
  93. #define ISR_MASK 0x1F
  94. static struct {
  95. u32 test;
  96. u32 ui;
  97. u32 uei;
  98. u32 pci;
  99. u32 uri;
  100. u32 sli;
  101. u32 none;
  102. struct {
  103. u32 cnt;
  104. u32 buf[ISR_MASK+1];
  105. u32 idx;
  106. } hndl;
  107. } isr_statistics;
  108. /**
  109. * ffs_nr: find first (least significant) bit set
  110. * @x: the word to search
  111. *
  112. * This function returns bit number (instead of position)
  113. */
  114. static int ffs_nr(u32 x)
  115. {
  116. int n = ffs(x);
  117. return n ? n-1 : 32;
  118. }
  119. /******************************************************************************
  120. * HW block
  121. *****************************************************************************/
  122. /* register bank descriptor */
  123. static struct {
  124. unsigned lpm; /* is LPM? */
  125. void __iomem *abs; /* bus map offset */
  126. void __iomem *cap; /* bus map offset + CAP offset + CAP data */
  127. size_t size; /* bank size */
  128. } hw_bank;
  129. /* MSM specific */
  130. #define ABS_AHBBURST (0x0090UL)
  131. #define ABS_AHBMODE (0x0098UL)
  132. /* UDC register map */
  133. #define ABS_CAPLENGTH (0x100UL)
  134. #define ABS_HCCPARAMS (0x108UL)
  135. #define ABS_DCCPARAMS (0x124UL)
  136. #define ABS_TESTMODE (hw_bank.lpm ? 0x0FCUL : 0x138UL)
  137. /* offset to CAPLENTGH (addr + data) */
  138. #define CAP_USBCMD (0x000UL)
  139. #define CAP_USBSTS (0x004UL)
  140. #define CAP_USBINTR (0x008UL)
  141. #define CAP_DEVICEADDR (0x014UL)
  142. #define CAP_ENDPTLISTADDR (0x018UL)
  143. #define CAP_PORTSC (0x044UL)
  144. #define CAP_DEVLC (0x084UL)
  145. #define CAP_USBMODE (hw_bank.lpm ? 0x0C8UL : 0x068UL)
  146. #define CAP_ENDPTSETUPSTAT (hw_bank.lpm ? 0x0D8UL : 0x06CUL)
  147. #define CAP_ENDPTPRIME (hw_bank.lpm ? 0x0DCUL : 0x070UL)
  148. #define CAP_ENDPTFLUSH (hw_bank.lpm ? 0x0E0UL : 0x074UL)
  149. #define CAP_ENDPTSTAT (hw_bank.lpm ? 0x0E4UL : 0x078UL)
  150. #define CAP_ENDPTCOMPLETE (hw_bank.lpm ? 0x0E8UL : 0x07CUL)
  151. #define CAP_ENDPTCTRL (hw_bank.lpm ? 0x0ECUL : 0x080UL)
  152. #define CAP_LAST (hw_bank.lpm ? 0x12CUL : 0x0C0UL)
  153. /* maximum number of enpoints: valid only after hw_device_reset() */
  154. static unsigned hw_ep_max;
  155. /**
  156. * hw_ep_bit: calculates the bit number
  157. * @num: endpoint number
  158. * @dir: endpoint direction
  159. *
  160. * This function returns bit number
  161. */
  162. static inline int hw_ep_bit(int num, int dir)
  163. {
  164. return num + (dir ? 16 : 0);
  165. }
  166. static int ep_to_bit(int n)
  167. {
  168. int fill = 16 - hw_ep_max / 2;
  169. if (n >= hw_ep_max / 2)
  170. n += fill;
  171. return n;
  172. }
  173. /**
  174. * hw_aread: reads from register bitfield
  175. * @addr: address relative to bus map
  176. * @mask: bitfield mask
  177. *
  178. * This function returns register bitfield data
  179. */
  180. static u32 hw_aread(u32 addr, u32 mask)
  181. {
  182. return ioread32(addr + hw_bank.abs) & mask;
  183. }
  184. /**
  185. * hw_awrite: writes to register bitfield
  186. * @addr: address relative to bus map
  187. * @mask: bitfield mask
  188. * @data: new data
  189. */
  190. static void hw_awrite(u32 addr, u32 mask, u32 data)
  191. {
  192. iowrite32(hw_aread(addr, ~mask) | (data & mask),
  193. addr + hw_bank.abs);
  194. }
  195. /**
  196. * hw_cread: reads from register bitfield
  197. * @addr: address relative to CAP offset plus content
  198. * @mask: bitfield mask
  199. *
  200. * This function returns register bitfield data
  201. */
  202. static u32 hw_cread(u32 addr, u32 mask)
  203. {
  204. return ioread32(addr + hw_bank.cap) & mask;
  205. }
  206. /**
  207. * hw_cwrite: writes to register bitfield
  208. * @addr: address relative to CAP offset plus content
  209. * @mask: bitfield mask
  210. * @data: new data
  211. */
  212. static void hw_cwrite(u32 addr, u32 mask, u32 data)
  213. {
  214. iowrite32(hw_cread(addr, ~mask) | (data & mask),
  215. addr + hw_bank.cap);
  216. }
  217. /**
  218. * hw_ctest_and_clear: tests & clears register bitfield
  219. * @addr: address relative to CAP offset plus content
  220. * @mask: bitfield mask
  221. *
  222. * This function returns register bitfield data
  223. */
  224. static u32 hw_ctest_and_clear(u32 addr, u32 mask)
  225. {
  226. u32 reg = hw_cread(addr, mask);
  227. iowrite32(reg, addr + hw_bank.cap);
  228. return reg;
  229. }
  230. /**
  231. * hw_ctest_and_write: tests & writes register bitfield
  232. * @addr: address relative to CAP offset plus content
  233. * @mask: bitfield mask
  234. * @data: new data
  235. *
  236. * This function returns register bitfield data
  237. */
  238. static u32 hw_ctest_and_write(u32 addr, u32 mask, u32 data)
  239. {
  240. u32 reg = hw_cread(addr, ~0);
  241. iowrite32((reg & ~mask) | (data & mask), addr + hw_bank.cap);
  242. return (reg & mask) >> ffs_nr(mask);
  243. }
  244. static int hw_device_init(void __iomem *base)
  245. {
  246. u32 reg;
  247. /* bank is a module variable */
  248. hw_bank.abs = base;
  249. hw_bank.cap = hw_bank.abs;
  250. hw_bank.cap += ABS_CAPLENGTH;
  251. hw_bank.cap += ioread8(hw_bank.cap);
  252. reg = hw_aread(ABS_HCCPARAMS, HCCPARAMS_LEN) >> ffs_nr(HCCPARAMS_LEN);
  253. hw_bank.lpm = reg;
  254. hw_bank.size = hw_bank.cap - hw_bank.abs;
  255. hw_bank.size += CAP_LAST;
  256. hw_bank.size /= sizeof(u32);
  257. reg = hw_aread(ABS_DCCPARAMS, DCCPARAMS_DEN) >> ffs_nr(DCCPARAMS_DEN);
  258. hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
  259. if (hw_ep_max == 0 || hw_ep_max > ENDPT_MAX)
  260. return -ENODEV;
  261. /* setup lock mode ? */
  262. /* ENDPTSETUPSTAT is '0' by default */
  263. /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
  264. return 0;
  265. }
  266. /**
  267. * hw_device_reset: resets chip (execute without interruption)
  268. * @base: register base address
  269. *
  270. * This function returns an error code
  271. */
  272. static int hw_device_reset(struct ci13xxx *udc)
  273. {
  274. /* should flush & stop before reset */
  275. hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0);
  276. hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
  277. hw_cwrite(CAP_USBCMD, USBCMD_RST, USBCMD_RST);
  278. while (hw_cread(CAP_USBCMD, USBCMD_RST))
  279. udelay(10); /* not RTOS friendly */
  280. if (udc->udc_driver->notify_event)
  281. udc->udc_driver->notify_event(udc,
  282. CI13XXX_CONTROLLER_RESET_EVENT);
  283. if (udc->udc_driver->flags & CI13XXX_DISABLE_STREAMING)
  284. hw_cwrite(CAP_USBMODE, USBMODE_SDIS, USBMODE_SDIS);
  285. /* USBMODE should be configured step by step */
  286. hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
  287. hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
  288. hw_cwrite(CAP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); /* HW >= 2.3 */
  289. if (hw_cread(CAP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
  290. pr_err("cannot enter in device mode");
  291. pr_err("lpm = %i", hw_bank.lpm);
  292. return -ENODEV;
  293. }
  294. return 0;
  295. }
  296. /**
  297. * hw_device_state: enables/disables interrupts & starts/stops device (execute
  298. * without interruption)
  299. * @dma: 0 => disable, !0 => enable and set dma engine
  300. *
  301. * This function returns an error code
  302. */
  303. static int hw_device_state(u32 dma)
  304. {
  305. if (dma) {
  306. hw_cwrite(CAP_ENDPTLISTADDR, ~0, dma);
  307. /* interrupt, error, port change, reset, sleep/suspend */
  308. hw_cwrite(CAP_USBINTR, ~0,
  309. USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
  310. hw_cwrite(CAP_USBCMD, USBCMD_RS, USBCMD_RS);
  311. } else {
  312. hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
  313. hw_cwrite(CAP_USBINTR, ~0, 0);
  314. }
  315. return 0;
  316. }
  317. /**
  318. * hw_ep_flush: flush endpoint fifo (execute without interruption)
  319. * @num: endpoint number
  320. * @dir: endpoint direction
  321. *
  322. * This function returns an error code
  323. */
  324. static int hw_ep_flush(int num, int dir)
  325. {
  326. int n = hw_ep_bit(num, dir);
  327. do {
  328. /* flush any pending transfer */
  329. hw_cwrite(CAP_ENDPTFLUSH, BIT(n), BIT(n));
  330. while (hw_cread(CAP_ENDPTFLUSH, BIT(n)))
  331. cpu_relax();
  332. } while (hw_cread(CAP_ENDPTSTAT, BIT(n)));
  333. return 0;
  334. }
  335. /**
  336. * hw_ep_disable: disables endpoint (execute without interruption)
  337. * @num: endpoint number
  338. * @dir: endpoint direction
  339. *
  340. * This function returns an error code
  341. */
  342. static int hw_ep_disable(int num, int dir)
  343. {
  344. hw_ep_flush(num, dir);
  345. hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32),
  346. dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
  347. return 0;
  348. }
  349. /**
  350. * hw_ep_enable: enables endpoint (execute without interruption)
  351. * @num: endpoint number
  352. * @dir: endpoint direction
  353. * @type: endpoint type
  354. *
  355. * This function returns an error code
  356. */
  357. static int hw_ep_enable(int num, int dir, int type)
  358. {
  359. u32 mask, data;
  360. if (dir) {
  361. mask = ENDPTCTRL_TXT; /* type */
  362. data = type << ffs_nr(mask);
  363. mask |= ENDPTCTRL_TXS; /* unstall */
  364. mask |= ENDPTCTRL_TXR; /* reset data toggle */
  365. data |= ENDPTCTRL_TXR;
  366. mask |= ENDPTCTRL_TXE; /* enable */
  367. data |= ENDPTCTRL_TXE;
  368. } else {
  369. mask = ENDPTCTRL_RXT; /* type */
  370. data = type << ffs_nr(mask);
  371. mask |= ENDPTCTRL_RXS; /* unstall */
  372. mask |= ENDPTCTRL_RXR; /* reset data toggle */
  373. data |= ENDPTCTRL_RXR;
  374. mask |= ENDPTCTRL_RXE; /* enable */
  375. data |= ENDPTCTRL_RXE;
  376. }
  377. hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32), mask, data);
  378. return 0;
  379. }
  380. /**
  381. * hw_ep_get_halt: return endpoint halt status
  382. * @num: endpoint number
  383. * @dir: endpoint direction
  384. *
  385. * This function returns 1 if endpoint halted
  386. */
  387. static int hw_ep_get_halt(int num, int dir)
  388. {
  389. u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  390. return hw_cread(CAP_ENDPTCTRL + num * sizeof(u32), mask) ? 1 : 0;
  391. }
  392. /**
  393. * hw_test_and_clear_setup_status: test & clear setup status (execute without
  394. * interruption)
  395. * @n: endpoint number
  396. *
  397. * This function returns setup status
  398. */
  399. static int hw_test_and_clear_setup_status(int n)
  400. {
  401. n = ep_to_bit(n);
  402. return hw_ctest_and_clear(CAP_ENDPTSETUPSTAT, BIT(n));
  403. }
  404. /**
  405. * hw_ep_prime: primes endpoint (execute without interruption)
  406. * @num: endpoint number
  407. * @dir: endpoint direction
  408. * @is_ctrl: true if control endpoint
  409. *
  410. * This function returns an error code
  411. */
  412. static int hw_ep_prime(int num, int dir, int is_ctrl)
  413. {
  414. int n = hw_ep_bit(num, dir);
  415. if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
  416. return -EAGAIN;
  417. hw_cwrite(CAP_ENDPTPRIME, BIT(n), BIT(n));
  418. while (hw_cread(CAP_ENDPTPRIME, BIT(n)))
  419. cpu_relax();
  420. if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
  421. return -EAGAIN;
  422. /* status shoult be tested according with manual but it doesn't work */
  423. return 0;
  424. }
  425. /**
  426. * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
  427. * without interruption)
  428. * @num: endpoint number
  429. * @dir: endpoint direction
  430. * @value: true => stall, false => unstall
  431. *
  432. * This function returns an error code
  433. */
  434. static int hw_ep_set_halt(int num, int dir, int value)
  435. {
  436. if (value != 0 && value != 1)
  437. return -EINVAL;
  438. do {
  439. u32 addr = CAP_ENDPTCTRL + num * sizeof(u32);
  440. u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  441. u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
  442. /* data toggle - reserved for EP0 but it's in ESS */
  443. hw_cwrite(addr, mask_xs|mask_xr, value ? mask_xs : mask_xr);
  444. } while (value != hw_ep_get_halt(num, dir));
  445. return 0;
  446. }
  447. /**
  448. * hw_intr_clear: disables interrupt & clears interrupt status (execute without
  449. * interruption)
  450. * @n: interrupt bit
  451. *
  452. * This function returns an error code
  453. */
  454. static int hw_intr_clear(int n)
  455. {
  456. if (n >= REG_BITS)
  457. return -EINVAL;
  458. hw_cwrite(CAP_USBINTR, BIT(n), 0);
  459. hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
  460. return 0;
  461. }
  462. /**
  463. * hw_intr_force: enables interrupt & forces interrupt status (execute without
  464. * interruption)
  465. * @n: interrupt bit
  466. *
  467. * This function returns an error code
  468. */
  469. static int hw_intr_force(int n)
  470. {
  471. if (n >= REG_BITS)
  472. return -EINVAL;
  473. hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
  474. hw_cwrite(CAP_USBINTR, BIT(n), BIT(n));
  475. hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
  476. hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, 0);
  477. return 0;
  478. }
  479. /**
  480. * hw_is_port_high_speed: test if port is high speed
  481. *
  482. * This function returns true if high speed port
  483. */
  484. static int hw_port_is_high_speed(void)
  485. {
  486. return hw_bank.lpm ? hw_cread(CAP_DEVLC, DEVLC_PSPD) :
  487. hw_cread(CAP_PORTSC, PORTSC_HSP);
  488. }
  489. /**
  490. * hw_port_test_get: reads port test mode value
  491. *
  492. * This function returns port test mode value
  493. */
  494. static u8 hw_port_test_get(void)
  495. {
  496. return hw_cread(CAP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
  497. }
  498. /**
  499. * hw_port_test_set: writes port test mode (execute without interruption)
  500. * @mode: new value
  501. *
  502. * This function returns an error code
  503. */
  504. static int hw_port_test_set(u8 mode)
  505. {
  506. const u8 TEST_MODE_MAX = 7;
  507. if (mode > TEST_MODE_MAX)
  508. return -EINVAL;
  509. hw_cwrite(CAP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
  510. return 0;
  511. }
  512. /**
  513. * hw_read_intr_enable: returns interrupt enable register
  514. *
  515. * This function returns register data
  516. */
  517. static u32 hw_read_intr_enable(void)
  518. {
  519. return hw_cread(CAP_USBINTR, ~0);
  520. }
  521. /**
  522. * hw_read_intr_status: returns interrupt status register
  523. *
  524. * This function returns register data
  525. */
  526. static u32 hw_read_intr_status(void)
  527. {
  528. return hw_cread(CAP_USBSTS, ~0);
  529. }
  530. /**
  531. * hw_register_read: reads all device registers (execute without interruption)
  532. * @buf: destination buffer
  533. * @size: buffer size
  534. *
  535. * This function returns number of registers read
  536. */
  537. static size_t hw_register_read(u32 *buf, size_t size)
  538. {
  539. unsigned i;
  540. if (size > hw_bank.size)
  541. size = hw_bank.size;
  542. for (i = 0; i < size; i++)
  543. buf[i] = hw_aread(i * sizeof(u32), ~0);
  544. return size;
  545. }
  546. /**
  547. * hw_register_write: writes to register
  548. * @addr: register address
  549. * @data: register value
  550. *
  551. * This function returns an error code
  552. */
  553. static int hw_register_write(u16 addr, u32 data)
  554. {
  555. /* align */
  556. addr /= sizeof(u32);
  557. if (addr >= hw_bank.size)
  558. return -EINVAL;
  559. /* align */
  560. addr *= sizeof(u32);
  561. hw_awrite(addr, ~0, data);
  562. return 0;
  563. }
  564. /**
  565. * hw_test_and_clear_complete: test & clear complete status (execute without
  566. * interruption)
  567. * @n: endpoint number
  568. *
  569. * This function returns complete status
  570. */
  571. static int hw_test_and_clear_complete(int n)
  572. {
  573. n = ep_to_bit(n);
  574. return hw_ctest_and_clear(CAP_ENDPTCOMPLETE, BIT(n));
  575. }
  576. /**
  577. * hw_test_and_clear_intr_active: test & clear active interrupts (execute
  578. * without interruption)
  579. *
  580. * This function returns active interrutps
  581. */
  582. static u32 hw_test_and_clear_intr_active(void)
  583. {
  584. u32 reg = hw_read_intr_status() & hw_read_intr_enable();
  585. hw_cwrite(CAP_USBSTS, ~0, reg);
  586. return reg;
  587. }
  588. /**
  589. * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
  590. * interruption)
  591. *
  592. * This function returns guard value
  593. */
  594. static int hw_test_and_clear_setup_guard(void)
  595. {
  596. return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, 0);
  597. }
  598. /**
  599. * hw_test_and_set_setup_guard: test & set setup guard (execute without
  600. * interruption)
  601. *
  602. * This function returns guard value
  603. */
  604. static int hw_test_and_set_setup_guard(void)
  605. {
  606. return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
  607. }
  608. /**
  609. * hw_usb_set_address: configures USB address (execute without interruption)
  610. * @value: new USB address
  611. *
  612. * This function returns an error code
  613. */
  614. static int hw_usb_set_address(u8 value)
  615. {
  616. /* advance */
  617. hw_cwrite(CAP_DEVICEADDR, DEVICEADDR_USBADR | DEVICEADDR_USBADRA,
  618. value << ffs_nr(DEVICEADDR_USBADR) | DEVICEADDR_USBADRA);
  619. return 0;
  620. }
  621. /**
  622. * hw_usb_reset: restart device after a bus reset (execute without
  623. * interruption)
  624. *
  625. * This function returns an error code
  626. */
  627. static int hw_usb_reset(void)
  628. {
  629. hw_usb_set_address(0);
  630. /* ESS flushes only at end?!? */
  631. hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0); /* flush all EPs */
  632. /* clear setup token semaphores */
  633. hw_cwrite(CAP_ENDPTSETUPSTAT, 0, 0); /* writes its content */
  634. /* clear complete status */
  635. hw_cwrite(CAP_ENDPTCOMPLETE, 0, 0); /* writes its content */
  636. /* wait until all bits cleared */
  637. while (hw_cread(CAP_ENDPTPRIME, ~0))
  638. udelay(10); /* not RTOS friendly */
  639. /* reset all endpoints ? */
  640. /* reset internal status and wait for further instructions
  641. no need to verify the port reset status (ESS does it) */
  642. return 0;
  643. }
  644. /******************************************************************************
  645. * DBG block
  646. *****************************************************************************/
  647. /**
  648. * show_device: prints information about device capabilities and status
  649. *
  650. * Check "device.h" for details
  651. */
  652. static ssize_t show_device(struct device *dev, struct device_attribute *attr,
  653. char *buf)
  654. {
  655. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  656. struct usb_gadget *gadget = &udc->gadget;
  657. int n = 0;
  658. dbg_trace("[%s] %p\n", __func__, buf);
  659. if (attr == NULL || buf == NULL) {
  660. dev_err(dev, "[%s] EINVAL\n", __func__);
  661. return 0;
  662. }
  663. n += scnprintf(buf + n, PAGE_SIZE - n, "speed = %d\n",
  664. gadget->speed);
  665. n += scnprintf(buf + n, PAGE_SIZE - n, "max_speed = %d\n",
  666. gadget->max_speed);
  667. /* TODO: Scheduled for removal in 3.8. */
  668. n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed = %d\n",
  669. gadget_is_dualspeed(gadget));
  670. n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg = %d\n",
  671. gadget->is_otg);
  672. n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral = %d\n",
  673. gadget->is_a_peripheral);
  674. n += scnprintf(buf + n, PAGE_SIZE - n, "b_hnp_enable = %d\n",
  675. gadget->b_hnp_enable);
  676. n += scnprintf(buf + n, PAGE_SIZE - n, "a_hnp_support = %d\n",
  677. gadget->a_hnp_support);
  678. n += scnprintf(buf + n, PAGE_SIZE - n, "a_alt_hnp_support = %d\n",
  679. gadget->a_alt_hnp_support);
  680. n += scnprintf(buf + n, PAGE_SIZE - n, "name = %s\n",
  681. (gadget->name ? gadget->name : ""));
  682. return n;
  683. }
  684. static DEVICE_ATTR(device, S_IRUSR, show_device, NULL);
  685. /**
  686. * show_driver: prints information about attached gadget (if any)
  687. *
  688. * Check "device.h" for details
  689. */
  690. static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
  691. char *buf)
  692. {
  693. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  694. struct usb_gadget_driver *driver = udc->driver;
  695. int n = 0;
  696. dbg_trace("[%s] %p\n", __func__, buf);
  697. if (attr == NULL || buf == NULL) {
  698. dev_err(dev, "[%s] EINVAL\n", __func__);
  699. return 0;
  700. }
  701. if (driver == NULL)
  702. return scnprintf(buf, PAGE_SIZE,
  703. "There is no gadget attached!\n");
  704. n += scnprintf(buf + n, PAGE_SIZE - n, "function = %s\n",
  705. (driver->function ? driver->function : ""));
  706. n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
  707. driver->max_speed);
  708. return n;
  709. }
  710. static DEVICE_ATTR(driver, S_IRUSR, show_driver, NULL);
  711. /* Maximum event message length */
  712. #define DBG_DATA_MSG 64UL
  713. /* Maximum event messages */
  714. #define DBG_DATA_MAX 128UL
  715. /* Event buffer descriptor */
  716. static struct {
  717. char (buf[DBG_DATA_MAX])[DBG_DATA_MSG]; /* buffer */
  718. unsigned idx; /* index */
  719. unsigned tty; /* print to console? */
  720. rwlock_t lck; /* lock */
  721. } dbg_data = {
  722. .idx = 0,
  723. .tty = 0,
  724. .lck = __RW_LOCK_UNLOCKED(lck)
  725. };
  726. /**
  727. * dbg_dec: decrements debug event index
  728. * @idx: buffer index
  729. */
  730. static void dbg_dec(unsigned *idx)
  731. {
  732. *idx = (*idx - 1) & (DBG_DATA_MAX-1);
  733. }
  734. /**
  735. * dbg_inc: increments debug event index
  736. * @idx: buffer index
  737. */
  738. static void dbg_inc(unsigned *idx)
  739. {
  740. *idx = (*idx + 1) & (DBG_DATA_MAX-1);
  741. }
  742. /**
  743. * dbg_print: prints the common part of the event
  744. * @addr: endpoint address
  745. * @name: event name
  746. * @status: status
  747. * @extra: extra information
  748. */
  749. static void dbg_print(u8 addr, const char *name, int status, const char *extra)
  750. {
  751. struct timeval tval;
  752. unsigned int stamp;
  753. unsigned long flags;
  754. write_lock_irqsave(&dbg_data.lck, flags);
  755. do_gettimeofday(&tval);
  756. stamp = tval.tv_sec & 0xFFFF; /* 2^32 = 4294967296. Limit to 4096s */
  757. stamp = stamp * 1000000 + tval.tv_usec;
  758. scnprintf(dbg_data.buf[dbg_data.idx], DBG_DATA_MSG,
  759. "%04X\t? %02X %-7.7s %4i ?\t%s\n",
  760. stamp, addr, name, status, extra);
  761. dbg_inc(&dbg_data.idx);
  762. write_unlock_irqrestore(&dbg_data.lck, flags);
  763. if (dbg_data.tty != 0)
  764. pr_notice("%04X\t? %02X %-7.7s %4i ?\t%s\n",
  765. stamp, addr, name, status, extra);
  766. }
  767. /**
  768. * dbg_done: prints a DONE event
  769. * @addr: endpoint address
  770. * @td: transfer descriptor
  771. * @status: status
  772. */
  773. static void dbg_done(u8 addr, const u32 token, int status)
  774. {
  775. char msg[DBG_DATA_MSG];
  776. scnprintf(msg, sizeof(msg), "%d %02X",
  777. (int)(token & TD_TOTAL_BYTES) >> ffs_nr(TD_TOTAL_BYTES),
  778. (int)(token & TD_STATUS) >> ffs_nr(TD_STATUS));
  779. dbg_print(addr, "DONE", status, msg);
  780. }
  781. /**
  782. * dbg_event: prints a generic event
  783. * @addr: endpoint address
  784. * @name: event name
  785. * @status: status
  786. */
  787. static void dbg_event(u8 addr, const char *name, int status)
  788. {
  789. if (name != NULL)
  790. dbg_print(addr, name, status, "");
  791. }
  792. /*
  793. * dbg_queue: prints a QUEUE event
  794. * @addr: endpoint address
  795. * @req: USB request
  796. * @status: status
  797. */
  798. static void dbg_queue(u8 addr, const struct usb_request *req, int status)
  799. {
  800. char msg[DBG_DATA_MSG];
  801. if (req != NULL) {
  802. scnprintf(msg, sizeof(msg),
  803. "%d %d", !req->no_interrupt, req->length);
  804. dbg_print(addr, "QUEUE", status, msg);
  805. }
  806. }
  807. /**
  808. * dbg_setup: prints a SETUP event
  809. * @addr: endpoint address
  810. * @req: setup request
  811. */
  812. static void dbg_setup(u8 addr, const struct usb_ctrlrequest *req)
  813. {
  814. char msg[DBG_DATA_MSG];
  815. if (req != NULL) {
  816. scnprintf(msg, sizeof(msg),
  817. "%02X %02X %04X %04X %d", req->bRequestType,
  818. req->bRequest, le16_to_cpu(req->wValue),
  819. le16_to_cpu(req->wIndex), le16_to_cpu(req->wLength));
  820. dbg_print(addr, "SETUP", 0, msg);
  821. }
  822. }
  823. /**
  824. * show_events: displays the event buffer
  825. *
  826. * Check "device.h" for details
  827. */
  828. static ssize_t show_events(struct device *dev, struct device_attribute *attr,
  829. char *buf)
  830. {
  831. unsigned long flags;
  832. unsigned i, j, n = 0;
  833. dbg_trace("[%s] %p\n", __func__, buf);
  834. if (attr == NULL || buf == NULL) {
  835. dev_err(dev, "[%s] EINVAL\n", __func__);
  836. return 0;
  837. }
  838. read_lock_irqsave(&dbg_data.lck, flags);
  839. i = dbg_data.idx;
  840. for (dbg_dec(&i); i != dbg_data.idx; dbg_dec(&i)) {
  841. n += strlen(dbg_data.buf[i]);
  842. if (n >= PAGE_SIZE) {
  843. n -= strlen(dbg_data.buf[i]);
  844. break;
  845. }
  846. }
  847. for (j = 0, dbg_inc(&i); j < n; dbg_inc(&i))
  848. j += scnprintf(buf + j, PAGE_SIZE - j,
  849. "%s", dbg_data.buf[i]);
  850. read_unlock_irqrestore(&dbg_data.lck, flags);
  851. return n;
  852. }
  853. /**
  854. * store_events: configure if events are going to be also printed to console
  855. *
  856. * Check "device.h" for details
  857. */
  858. static ssize_t store_events(struct device *dev, struct device_attribute *attr,
  859. const char *buf, size_t count)
  860. {
  861. unsigned tty;
  862. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  863. if (attr == NULL || buf == NULL) {
  864. dev_err(dev, "[%s] EINVAL\n", __func__);
  865. goto done;
  866. }
  867. if (sscanf(buf, "%u", &tty) != 1 || tty > 1) {
  868. dev_err(dev, "<1|0>: enable|disable console log\n");
  869. goto done;
  870. }
  871. dbg_data.tty = tty;
  872. dev_info(dev, "tty = %u", dbg_data.tty);
  873. done:
  874. return count;
  875. }
  876. static DEVICE_ATTR(events, S_IRUSR | S_IWUSR, show_events, store_events);
  877. /**
  878. * show_inters: interrupt status, enable status and historic
  879. *
  880. * Check "device.h" for details
  881. */
  882. static ssize_t show_inters(struct device *dev, struct device_attribute *attr,
  883. char *buf)
  884. {
  885. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  886. unsigned long flags;
  887. u32 intr;
  888. unsigned i, j, n = 0;
  889. dbg_trace("[%s] %p\n", __func__, buf);
  890. if (attr == NULL || buf == NULL) {
  891. dev_err(dev, "[%s] EINVAL\n", __func__);
  892. return 0;
  893. }
  894. spin_lock_irqsave(udc->lock, flags);
  895. n += scnprintf(buf + n, PAGE_SIZE - n,
  896. "status = %08x\n", hw_read_intr_status());
  897. n += scnprintf(buf + n, PAGE_SIZE - n,
  898. "enable = %08x\n", hw_read_intr_enable());
  899. n += scnprintf(buf + n, PAGE_SIZE - n, "*test = %d\n",
  900. isr_statistics.test);
  901. n += scnprintf(buf + n, PAGE_SIZE - n, "? ui = %d\n",
  902. isr_statistics.ui);
  903. n += scnprintf(buf + n, PAGE_SIZE - n, "? uei = %d\n",
  904. isr_statistics.uei);
  905. n += scnprintf(buf + n, PAGE_SIZE - n, "? pci = %d\n",
  906. isr_statistics.pci);
  907. n += scnprintf(buf + n, PAGE_SIZE - n, "? uri = %d\n",
  908. isr_statistics.uri);
  909. n += scnprintf(buf + n, PAGE_SIZE - n, "? sli = %d\n",
  910. isr_statistics.sli);
  911. n += scnprintf(buf + n, PAGE_SIZE - n, "*none = %d\n",
  912. isr_statistics.none);
  913. n += scnprintf(buf + n, PAGE_SIZE - n, "*hndl = %d\n",
  914. isr_statistics.hndl.cnt);
  915. for (i = isr_statistics.hndl.idx, j = 0; j <= ISR_MASK; j++, i++) {
  916. i &= ISR_MASK;
  917. intr = isr_statistics.hndl.buf[i];
  918. if (USBi_UI & intr)
  919. n += scnprintf(buf + n, PAGE_SIZE - n, "ui ");
  920. intr &= ~USBi_UI;
  921. if (USBi_UEI & intr)
  922. n += scnprintf(buf + n, PAGE_SIZE - n, "uei ");
  923. intr &= ~USBi_UEI;
  924. if (USBi_PCI & intr)
  925. n += scnprintf(buf + n, PAGE_SIZE - n, "pci ");
  926. intr &= ~USBi_PCI;
  927. if (USBi_URI & intr)
  928. n += scnprintf(buf + n, PAGE_SIZE - n, "uri ");
  929. intr &= ~USBi_URI;
  930. if (USBi_SLI & intr)
  931. n += scnprintf(buf + n, PAGE_SIZE - n, "sli ");
  932. intr &= ~USBi_SLI;
  933. if (intr)
  934. n += scnprintf(buf + n, PAGE_SIZE - n, "??? ");
  935. if (isr_statistics.hndl.buf[i])
  936. n += scnprintf(buf + n, PAGE_SIZE - n, "\n");
  937. }
  938. spin_unlock_irqrestore(udc->lock, flags);
  939. return n;
  940. }
  941. /**
  942. * store_inters: enable & force or disable an individual interrutps
  943. * (to be used for test purposes only)
  944. *
  945. * Check "device.h" for details
  946. */
  947. static ssize_t store_inters(struct device *dev, struct device_attribute *attr,
  948. const char *buf, size_t count)
  949. {
  950. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  951. unsigned long flags;
  952. unsigned en, bit;
  953. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  954. if (attr == NULL || buf == NULL) {
  955. dev_err(dev, "[%s] EINVAL\n", __func__);
  956. goto done;
  957. }
  958. if (sscanf(buf, "%u %u", &en, &bit) != 2 || en > 1) {
  959. dev_err(dev, "<1|0> <bit>: enable|disable interrupt");
  960. goto done;
  961. }
  962. spin_lock_irqsave(udc->lock, flags);
  963. if (en) {
  964. if (hw_intr_force(bit))
  965. dev_err(dev, "invalid bit number\n");
  966. else
  967. isr_statistics.test++;
  968. } else {
  969. if (hw_intr_clear(bit))
  970. dev_err(dev, "invalid bit number\n");
  971. }
  972. spin_unlock_irqrestore(udc->lock, flags);
  973. done:
  974. return count;
  975. }
  976. static DEVICE_ATTR(inters, S_IRUSR | S_IWUSR, show_inters, store_inters);
  977. /**
  978. * show_port_test: reads port test mode
  979. *
  980. * Check "device.h" for details
  981. */
  982. static ssize_t show_port_test(struct device *dev,
  983. struct device_attribute *attr, char *buf)
  984. {
  985. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  986. unsigned long flags;
  987. unsigned mode;
  988. dbg_trace("[%s] %p\n", __func__, buf);
  989. if (attr == NULL || buf == NULL) {
  990. dev_err(dev, "[%s] EINVAL\n", __func__);
  991. return 0;
  992. }
  993. spin_lock_irqsave(udc->lock, flags);
  994. mode = hw_port_test_get();
  995. spin_unlock_irqrestore(udc->lock, flags);
  996. return scnprintf(buf, PAGE_SIZE, "mode = %u\n", mode);
  997. }
  998. /**
  999. * store_port_test: writes port test mode
  1000. *
  1001. * Check "device.h" for details
  1002. */
  1003. static ssize_t store_port_test(struct device *dev,
  1004. struct device_attribute *attr,
  1005. const char *buf, size_t count)
  1006. {
  1007. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1008. unsigned long flags;
  1009. unsigned mode;
  1010. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  1011. if (attr == NULL || buf == NULL) {
  1012. dev_err(dev, "[%s] EINVAL\n", __func__);
  1013. goto done;
  1014. }
  1015. if (sscanf(buf, "%u", &mode) != 1) {
  1016. dev_err(dev, "<mode>: set port test mode");
  1017. goto done;
  1018. }
  1019. spin_lock_irqsave(udc->lock, flags);
  1020. if (hw_port_test_set(mode))
  1021. dev_err(dev, "invalid mode\n");
  1022. spin_unlock_irqrestore(udc->lock, flags);
  1023. done:
  1024. return count;
  1025. }
  1026. static DEVICE_ATTR(port_test, S_IRUSR | S_IWUSR,
  1027. show_port_test, store_port_test);
  1028. /**
  1029. * show_qheads: DMA contents of all queue heads
  1030. *
  1031. * Check "device.h" for details
  1032. */
  1033. static ssize_t show_qheads(struct device *dev, struct device_attribute *attr,
  1034. char *buf)
  1035. {
  1036. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1037. unsigned long flags;
  1038. unsigned i, j, n = 0;
  1039. dbg_trace("[%s] %p\n", __func__, buf);
  1040. if (attr == NULL || buf == NULL) {
  1041. dev_err(dev, "[%s] EINVAL\n", __func__);
  1042. return 0;
  1043. }
  1044. spin_lock_irqsave(udc->lock, flags);
  1045. for (i = 0; i < hw_ep_max/2; i++) {
  1046. struct ci13xxx_ep *mEpRx = &udc->ci13xxx_ep[i];
  1047. struct ci13xxx_ep *mEpTx = &udc->ci13xxx_ep[i + hw_ep_max/2];
  1048. n += scnprintf(buf + n, PAGE_SIZE - n,
  1049. "EP=%02i: RX=%08X TX=%08X\n",
  1050. i, (u32)mEpRx->qh.dma, (u32)mEpTx->qh.dma);
  1051. for (j = 0; j < (sizeof(struct ci13xxx_qh)/sizeof(u32)); j++) {
  1052. n += scnprintf(buf + n, PAGE_SIZE - n,
  1053. " %04X: %08X %08X\n", j,
  1054. *((u32 *)mEpRx->qh.ptr + j),
  1055. *((u32 *)mEpTx->qh.ptr + j));
  1056. }
  1057. }
  1058. spin_unlock_irqrestore(udc->lock, flags);
  1059. return n;
  1060. }
  1061. static DEVICE_ATTR(qheads, S_IRUSR, show_qheads, NULL);
  1062. /**
  1063. * show_registers: dumps all registers
  1064. *
  1065. * Check "device.h" for details
  1066. */
  1067. #define DUMP_ENTRIES 512
  1068. static ssize_t show_registers(struct device *dev,
  1069. struct device_attribute *attr, char *buf)
  1070. {
  1071. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1072. unsigned long flags;
  1073. u32 *dump;
  1074. unsigned i, k, n = 0;
  1075. dbg_trace("[%s] %p\n", __func__, buf);
  1076. if (attr == NULL || buf == NULL) {
  1077. dev_err(dev, "[%s] EINVAL\n", __func__);
  1078. return 0;
  1079. }
  1080. dump = kmalloc(sizeof(u32) * DUMP_ENTRIES, GFP_KERNEL);
  1081. if (!dump) {
  1082. dev_err(dev, "%s: out of memory\n", __func__);
  1083. return 0;
  1084. }
  1085. spin_lock_irqsave(udc->lock, flags);
  1086. k = hw_register_read(dump, DUMP_ENTRIES);
  1087. spin_unlock_irqrestore(udc->lock, flags);
  1088. for (i = 0; i < k; i++) {
  1089. n += scnprintf(buf + n, PAGE_SIZE - n,
  1090. "reg[0x%04X] = 0x%08X\n",
  1091. i * (unsigned)sizeof(u32), dump[i]);
  1092. }
  1093. kfree(dump);
  1094. return n;
  1095. }
  1096. /**
  1097. * store_registers: writes value to register address
  1098. *
  1099. * Check "device.h" for details
  1100. */
  1101. static ssize_t store_registers(struct device *dev,
  1102. struct device_attribute *attr,
  1103. const char *buf, size_t count)
  1104. {
  1105. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1106. unsigned long addr, data, flags;
  1107. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  1108. if (attr == NULL || buf == NULL) {
  1109. dev_err(dev, "[%s] EINVAL\n", __func__);
  1110. goto done;
  1111. }
  1112. if (sscanf(buf, "%li %li", &addr, &data) != 2) {
  1113. dev_err(dev, "<addr> <data>: write data to register address");
  1114. goto done;
  1115. }
  1116. spin_lock_irqsave(udc->lock, flags);
  1117. if (hw_register_write(addr, data))
  1118. dev_err(dev, "invalid address range\n");
  1119. spin_unlock_irqrestore(udc->lock, flags);
  1120. done:
  1121. return count;
  1122. }
  1123. static DEVICE_ATTR(registers, S_IRUSR | S_IWUSR,
  1124. show_registers, store_registers);
  1125. /**
  1126. * show_requests: DMA contents of all requests currently queued (all endpts)
  1127. *
  1128. * Check "device.h" for details
  1129. */
  1130. static ssize_t show_requests(struct device *dev, struct device_attribute *attr,
  1131. char *buf)
  1132. {
  1133. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1134. unsigned long flags;
  1135. struct list_head *ptr = NULL;
  1136. struct ci13xxx_req *req = NULL;
  1137. unsigned i, j, n = 0, qSize = sizeof(struct ci13xxx_td)/sizeof(u32);
  1138. dbg_trace("[%s] %p\n", __func__, buf);
  1139. if (attr == NULL || buf == NULL) {
  1140. dev_err(dev, "[%s] EINVAL\n", __func__);
  1141. return 0;
  1142. }
  1143. spin_lock_irqsave(udc->lock, flags);
  1144. for (i = 0; i < hw_ep_max; i++)
  1145. list_for_each(ptr, &udc->ci13xxx_ep[i].qh.queue)
  1146. {
  1147. req = list_entry(ptr, struct ci13xxx_req, queue);
  1148. n += scnprintf(buf + n, PAGE_SIZE - n,
  1149. "EP=%02i: TD=%08X %s\n",
  1150. i % hw_ep_max/2, (u32)req->dma,
  1151. ((i < hw_ep_max/2) ? "RX" : "TX"));
  1152. for (j = 0; j < qSize; j++)
  1153. n += scnprintf(buf + n, PAGE_SIZE - n,
  1154. " %04X: %08X\n", j,
  1155. *((u32 *)req->ptr + j));
  1156. }
  1157. spin_unlock_irqrestore(udc->lock, flags);
  1158. return n;
  1159. }
  1160. static DEVICE_ATTR(requests, S_IRUSR, show_requests, NULL);
  1161. /**
  1162. * dbg_create_files: initializes the attribute interface
  1163. * @dev: device
  1164. *
  1165. * This function returns an error code
  1166. */
  1167. __maybe_unused static int dbg_create_files(struct device *dev)
  1168. {
  1169. int retval = 0;
  1170. if (dev == NULL)
  1171. return -EINVAL;
  1172. retval = device_create_file(dev, &dev_attr_device);
  1173. if (retval)
  1174. goto done;
  1175. retval = device_create_file(dev, &dev_attr_driver);
  1176. if (retval)
  1177. goto rm_device;
  1178. retval = device_create_file(dev, &dev_attr_events);
  1179. if (retval)
  1180. goto rm_driver;
  1181. retval = device_create_file(dev, &dev_attr_inters);
  1182. if (retval)
  1183. goto rm_events;
  1184. retval = device_create_file(dev, &dev_attr_port_test);
  1185. if (retval)
  1186. goto rm_inters;
  1187. retval = device_create_file(dev, &dev_attr_qheads);
  1188. if (retval)
  1189. goto rm_port_test;
  1190. retval = device_create_file(dev, &dev_attr_registers);
  1191. if (retval)
  1192. goto rm_qheads;
  1193. retval = device_create_file(dev, &dev_attr_requests);
  1194. if (retval)
  1195. goto rm_registers;
  1196. return 0;
  1197. rm_registers:
  1198. device_remove_file(dev, &dev_attr_registers);
  1199. rm_qheads:
  1200. device_remove_file(dev, &dev_attr_qheads);
  1201. rm_port_test:
  1202. device_remove_file(dev, &dev_attr_port_test);
  1203. rm_inters:
  1204. device_remove_file(dev, &dev_attr_inters);
  1205. rm_events:
  1206. device_remove_file(dev, &dev_attr_events);
  1207. rm_driver:
  1208. device_remove_file(dev, &dev_attr_driver);
  1209. rm_device:
  1210. device_remove_file(dev, &dev_attr_device);
  1211. done:
  1212. return retval;
  1213. }
  1214. /**
  1215. * dbg_remove_files: destroys the attribute interface
  1216. * @dev: device
  1217. *
  1218. * This function returns an error code
  1219. */
  1220. __maybe_unused static int dbg_remove_files(struct device *dev)
  1221. {
  1222. if (dev == NULL)
  1223. return -EINVAL;
  1224. device_remove_file(dev, &dev_attr_requests);
  1225. device_remove_file(dev, &dev_attr_registers);
  1226. device_remove_file(dev, &dev_attr_qheads);
  1227. device_remove_file(dev, &dev_attr_port_test);
  1228. device_remove_file(dev, &dev_attr_inters);
  1229. device_remove_file(dev, &dev_attr_events);
  1230. device_remove_file(dev, &dev_attr_driver);
  1231. device_remove_file(dev, &dev_attr_device);
  1232. return 0;
  1233. }
  1234. /******************************************************************************
  1235. * UTIL block
  1236. *****************************************************************************/
  1237. /**
  1238. * _usb_addr: calculates endpoint address from direction & number
  1239. * @ep: endpoint
  1240. */
  1241. static inline u8 _usb_addr(struct ci13xxx_ep *ep)
  1242. {
  1243. return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
  1244. }
  1245. /**
  1246. * _hardware_queue: configures a request at hardware level
  1247. * @gadget: gadget
  1248. * @mEp: endpoint
  1249. *
  1250. * This function returns an error code
  1251. */
  1252. static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1253. {
  1254. unsigned i;
  1255. int ret = 0;
  1256. unsigned length = mReq->req.length;
  1257. trace("%p, %p", mEp, mReq);
  1258. /* don't queue twice */
  1259. if (mReq->req.status == -EALREADY)
  1260. return -EALREADY;
  1261. mReq->req.status = -EALREADY;
  1262. if (length && mReq->req.dma == DMA_ADDR_INVALID) {
  1263. mReq->req.dma = \
  1264. dma_map_single(mEp->device, mReq->req.buf,
  1265. length, mEp->dir ? DMA_TO_DEVICE :
  1266. DMA_FROM_DEVICE);
  1267. if (mReq->req.dma == 0)
  1268. return -ENOMEM;
  1269. mReq->map = 1;
  1270. }
  1271. if (mReq->req.zero && length && (length % mEp->ep.maxpacket == 0)) {
  1272. mReq->zptr = dma_pool_alloc(mEp->td_pool, GFP_ATOMIC,
  1273. &mReq->zdma);
  1274. if (mReq->zptr == NULL) {
  1275. if (mReq->map) {
  1276. dma_unmap_single(mEp->device, mReq->req.dma,
  1277. length, mEp->dir ? DMA_TO_DEVICE :
  1278. DMA_FROM_DEVICE);
  1279. mReq->req.dma = DMA_ADDR_INVALID;
  1280. mReq->map = 0;
  1281. }
  1282. return -ENOMEM;
  1283. }
  1284. memset(mReq->zptr, 0, sizeof(*mReq->zptr));
  1285. mReq->zptr->next = TD_TERMINATE;
  1286. mReq->zptr->token = TD_STATUS_ACTIVE;
  1287. if (!mReq->req.no_interrupt)
  1288. mReq->zptr->token |= TD_IOC;
  1289. }
  1290. /*
  1291. * TD configuration
  1292. * TODO - handle requests which spawns into several TDs
  1293. */
  1294. memset(mReq->ptr, 0, sizeof(*mReq->ptr));
  1295. mReq->ptr->token = length << ffs_nr(TD_TOTAL_BYTES);
  1296. mReq->ptr->token &= TD_TOTAL_BYTES;
  1297. mReq->ptr->token |= TD_STATUS_ACTIVE;
  1298. if (mReq->zptr) {
  1299. mReq->ptr->next = mReq->zdma;
  1300. } else {
  1301. mReq->ptr->next = TD_TERMINATE;
  1302. if (!mReq->req.no_interrupt)
  1303. mReq->ptr->token |= TD_IOC;
  1304. }
  1305. mReq->ptr->page[0] = mReq->req.dma;
  1306. for (i = 1; i < 5; i++)
  1307. mReq->ptr->page[i] =
  1308. (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK;
  1309. if (!list_empty(&mEp->qh.queue)) {
  1310. struct ci13xxx_req *mReqPrev;
  1311. int n = hw_ep_bit(mEp->num, mEp->dir);
  1312. int tmp_stat;
  1313. mReqPrev = list_entry(mEp->qh.queue.prev,
  1314. struct ci13xxx_req, queue);
  1315. if (mReqPrev->zptr)
  1316. mReqPrev->zptr->next = mReq->dma & TD_ADDR_MASK;
  1317. else
  1318. mReqPrev->ptr->next = mReq->dma & TD_ADDR_MASK;
  1319. wmb();
  1320. if (hw_cread(CAP_ENDPTPRIME, BIT(n)))
  1321. goto done;
  1322. do {
  1323. hw_cwrite(CAP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
  1324. tmp_stat = hw_cread(CAP_ENDPTSTAT, BIT(n));
  1325. } while (!hw_cread(CAP_USBCMD, USBCMD_ATDTW));
  1326. hw_cwrite(CAP_USBCMD, USBCMD_ATDTW, 0);
  1327. if (tmp_stat)
  1328. goto done;
  1329. }
  1330. /* QH configuration */
  1331. mEp->qh.ptr->td.next = mReq->dma; /* TERMINATE = 0 */
  1332. mEp->qh.ptr->td.token &= ~TD_STATUS; /* clear status */
  1333. mEp->qh.ptr->cap |= QH_ZLT;
  1334. wmb(); /* synchronize before ep prime */
  1335. ret = hw_ep_prime(mEp->num, mEp->dir,
  1336. mEp->type == USB_ENDPOINT_XFER_CONTROL);
  1337. done:
  1338. return ret;
  1339. }
  1340. /**
  1341. * _hardware_dequeue: handles a request at hardware level
  1342. * @gadget: gadget
  1343. * @mEp: endpoint
  1344. *
  1345. * This function returns an error code
  1346. */
  1347. static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1348. {
  1349. trace("%p, %p", mEp, mReq);
  1350. if (mReq->req.status != -EALREADY)
  1351. return -EINVAL;
  1352. if ((TD_STATUS_ACTIVE & mReq->ptr->token) != 0)
  1353. return -EBUSY;
  1354. if (mReq->zptr) {
  1355. if ((TD_STATUS_ACTIVE & mReq->zptr->token) != 0)
  1356. return -EBUSY;
  1357. dma_pool_free(mEp->td_pool, mReq->zptr, mReq->zdma);
  1358. mReq->zptr = NULL;
  1359. }
  1360. mReq->req.status = 0;
  1361. if (mReq->map) {
  1362. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  1363. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  1364. mReq->req.dma = DMA_ADDR_INVALID;
  1365. mReq->map = 0;
  1366. }
  1367. mReq->req.status = mReq->ptr->token & TD_STATUS;
  1368. if ((TD_STATUS_HALTED & mReq->req.status) != 0)
  1369. mReq->req.status = -1;
  1370. else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
  1371. mReq->req.status = -1;
  1372. else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
  1373. mReq->req.status = -1;
  1374. mReq->req.actual = mReq->ptr->token & TD_TOTAL_BYTES;
  1375. mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES);
  1376. mReq->req.actual = mReq->req.length - mReq->req.actual;
  1377. mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual;
  1378. return mReq->req.actual;
  1379. }
  1380. /**
  1381. * _ep_nuke: dequeues all endpoint requests
  1382. * @mEp: endpoint
  1383. *
  1384. * This function returns an error code
  1385. * Caller must hold lock
  1386. */
  1387. static int _ep_nuke(struct ci13xxx_ep *mEp)
  1388. __releases(mEp->lock)
  1389. __acquires(mEp->lock)
  1390. {
  1391. trace("%p", mEp);
  1392. if (mEp == NULL)
  1393. return -EINVAL;
  1394. hw_ep_flush(mEp->num, mEp->dir);
  1395. while (!list_empty(&mEp->qh.queue)) {
  1396. /* pop oldest request */
  1397. struct ci13xxx_req *mReq = \
  1398. list_entry(mEp->qh.queue.next,
  1399. struct ci13xxx_req, queue);
  1400. list_del_init(&mReq->queue);
  1401. mReq->req.status = -ESHUTDOWN;
  1402. if (mReq->req.complete != NULL) {
  1403. spin_unlock(mEp->lock);
  1404. mReq->req.complete(&mEp->ep, &mReq->req);
  1405. spin_lock(mEp->lock);
  1406. }
  1407. }
  1408. return 0;
  1409. }
  1410. /**
  1411. * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
  1412. * @gadget: gadget
  1413. *
  1414. * This function returns an error code
  1415. */
  1416. static int _gadget_stop_activity(struct usb_gadget *gadget)
  1417. {
  1418. struct usb_ep *ep;
  1419. struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
  1420. unsigned long flags;
  1421. trace("%p", gadget);
  1422. if (gadget == NULL)
  1423. return -EINVAL;
  1424. spin_lock_irqsave(udc->lock, flags);
  1425. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1426. udc->remote_wakeup = 0;
  1427. udc->suspended = 0;
  1428. spin_unlock_irqrestore(udc->lock, flags);
  1429. /* flush all endpoints */
  1430. gadget_for_each_ep(ep, gadget) {
  1431. usb_ep_fifo_flush(ep);
  1432. }
  1433. usb_ep_fifo_flush(&udc->ep0out.ep);
  1434. usb_ep_fifo_flush(&udc->ep0in.ep);
  1435. udc->driver->disconnect(gadget);
  1436. /* make sure to disable all endpoints */
  1437. gadget_for_each_ep(ep, gadget) {
  1438. usb_ep_disable(ep);
  1439. }
  1440. if (udc->status != NULL) {
  1441. usb_ep_free_request(&udc->ep0in.ep, udc->status);
  1442. udc->status = NULL;
  1443. }
  1444. return 0;
  1445. }
  1446. /******************************************************************************
  1447. * ISR block
  1448. *****************************************************************************/
  1449. /**
  1450. * isr_reset_handler: USB reset interrupt handler
  1451. * @udc: UDC device
  1452. *
  1453. * This function resets USB engine after a bus reset occurred
  1454. */
  1455. static void isr_reset_handler(struct ci13xxx *udc)
  1456. __releases(udc->lock)
  1457. __acquires(udc->lock)
  1458. {
  1459. int retval;
  1460. trace("%p", udc);
  1461. if (udc == NULL) {
  1462. err("EINVAL");
  1463. return;
  1464. }
  1465. dbg_event(0xFF, "BUS RST", 0);
  1466. spin_unlock(udc->lock);
  1467. retval = _gadget_stop_activity(&udc->gadget);
  1468. if (retval)
  1469. goto done;
  1470. retval = hw_usb_reset();
  1471. if (retval)
  1472. goto done;
  1473. udc->status = usb_ep_alloc_request(&udc->ep0in.ep, GFP_ATOMIC);
  1474. if (udc->status == NULL)
  1475. retval = -ENOMEM;
  1476. spin_lock(udc->lock);
  1477. done:
  1478. if (retval)
  1479. err("error: %i", retval);
  1480. }
  1481. /**
  1482. * isr_get_status_complete: get_status request complete function
  1483. * @ep: endpoint
  1484. * @req: request handled
  1485. *
  1486. * Caller must release lock
  1487. */
  1488. static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
  1489. {
  1490. trace("%p, %p", ep, req);
  1491. if (ep == NULL || req == NULL) {
  1492. err("EINVAL");
  1493. return;
  1494. }
  1495. kfree(req->buf);
  1496. usb_ep_free_request(ep, req);
  1497. }
  1498. /**
  1499. * isr_get_status_response: get_status request response
  1500. * @udc: udc struct
  1501. * @setup: setup request packet
  1502. *
  1503. * This function returns an error code
  1504. */
  1505. static int isr_get_status_response(struct ci13xxx *udc,
  1506. struct usb_ctrlrequest *setup)
  1507. __releases(mEp->lock)
  1508. __acquires(mEp->lock)
  1509. {
  1510. struct ci13xxx_ep *mEp = &udc->ep0in;
  1511. struct usb_request *req = NULL;
  1512. gfp_t gfp_flags = GFP_ATOMIC;
  1513. int dir, num, retval;
  1514. trace("%p, %p", mEp, setup);
  1515. if (mEp == NULL || setup == NULL)
  1516. return -EINVAL;
  1517. spin_unlock(mEp->lock);
  1518. req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
  1519. spin_lock(mEp->lock);
  1520. if (req == NULL)
  1521. return -ENOMEM;
  1522. req->complete = isr_get_status_complete;
  1523. req->length = 2;
  1524. req->buf = kzalloc(req->length, gfp_flags);
  1525. if (req->buf == NULL) {
  1526. retval = -ENOMEM;
  1527. goto err_free_req;
  1528. }
  1529. if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  1530. /* Assume that device is bus powered for now. */
  1531. *((u16 *)req->buf) = _udc->remote_wakeup << 1;
  1532. retval = 0;
  1533. } else if ((setup->bRequestType & USB_RECIP_MASK) \
  1534. == USB_RECIP_ENDPOINT) {
  1535. dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
  1536. TX : RX;
  1537. num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
  1538. *((u16 *)req->buf) = hw_ep_get_halt(num, dir);
  1539. }
  1540. /* else do nothing; reserved for future use */
  1541. spin_unlock(mEp->lock);
  1542. retval = usb_ep_queue(&mEp->ep, req, gfp_flags);
  1543. spin_lock(mEp->lock);
  1544. if (retval)
  1545. goto err_free_buf;
  1546. return 0;
  1547. err_free_buf:
  1548. kfree(req->buf);
  1549. err_free_req:
  1550. spin_unlock(mEp->lock);
  1551. usb_ep_free_request(&mEp->ep, req);
  1552. spin_lock(mEp->lock);
  1553. return retval;
  1554. }
  1555. /**
  1556. * isr_setup_status_complete: setup_status request complete function
  1557. * @ep: endpoint
  1558. * @req: request handled
  1559. *
  1560. * Caller must release lock. Put the port in test mode if test mode
  1561. * feature is selected.
  1562. */
  1563. static void
  1564. isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
  1565. {
  1566. struct ci13xxx *udc = req->context;
  1567. unsigned long flags;
  1568. trace("%p, %p", ep, req);
  1569. spin_lock_irqsave(udc->lock, flags);
  1570. if (udc->test_mode)
  1571. hw_port_test_set(udc->test_mode);
  1572. spin_unlock_irqrestore(udc->lock, flags);
  1573. }
  1574. /**
  1575. * isr_setup_status_phase: queues the status phase of a setup transation
  1576. * @udc: udc struct
  1577. *
  1578. * This function returns an error code
  1579. */
  1580. static int isr_setup_status_phase(struct ci13xxx *udc)
  1581. __releases(mEp->lock)
  1582. __acquires(mEp->lock)
  1583. {
  1584. int retval;
  1585. struct ci13xxx_ep *mEp;
  1586. trace("%p", udc);
  1587. mEp = (udc->ep0_dir == TX) ? &udc->ep0out : &udc->ep0in;
  1588. udc->status->context = udc;
  1589. udc->status->complete = isr_setup_status_complete;
  1590. spin_unlock(mEp->lock);
  1591. retval = usb_ep_queue(&mEp->ep, udc->status, GFP_ATOMIC);
  1592. spin_lock(mEp->lock);
  1593. return retval;
  1594. }
  1595. /**
  1596. * isr_tr_complete_low: transaction complete low level handler
  1597. * @mEp: endpoint
  1598. *
  1599. * This function returns an error code
  1600. * Caller must hold lock
  1601. */
  1602. static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
  1603. __releases(mEp->lock)
  1604. __acquires(mEp->lock)
  1605. {
  1606. struct ci13xxx_req *mReq, *mReqTemp;
  1607. struct ci13xxx_ep *mEpTemp = mEp;
  1608. int uninitialized_var(retval);
  1609. trace("%p", mEp);
  1610. if (list_empty(&mEp->qh.queue))
  1611. return -EINVAL;
  1612. list_for_each_entry_safe(mReq, mReqTemp, &mEp->qh.queue,
  1613. queue) {
  1614. retval = _hardware_dequeue(mEp, mReq);
  1615. if (retval < 0)
  1616. break;
  1617. list_del_init(&mReq->queue);
  1618. dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
  1619. if (mReq->req.complete != NULL) {
  1620. spin_unlock(mEp->lock);
  1621. if ((mEp->type == USB_ENDPOINT_XFER_CONTROL) &&
  1622. mReq->req.length)
  1623. mEpTemp = &_udc->ep0in;
  1624. mReq->req.complete(&mEpTemp->ep, &mReq->req);
  1625. spin_lock(mEp->lock);
  1626. }
  1627. }
  1628. if (retval == -EBUSY)
  1629. retval = 0;
  1630. if (retval < 0)
  1631. dbg_event(_usb_addr(mEp), "DONE", retval);
  1632. return retval;
  1633. }
  1634. /**
  1635. * isr_tr_complete_handler: transaction complete interrupt handler
  1636. * @udc: UDC descriptor
  1637. *
  1638. * This function handles traffic events
  1639. */
  1640. static void isr_tr_complete_handler(struct ci13xxx *udc)
  1641. __releases(udc->lock)
  1642. __acquires(udc->lock)
  1643. {
  1644. unsigned i;
  1645. u8 tmode = 0;
  1646. trace("%p", udc);
  1647. if (udc == NULL) {
  1648. err("EINVAL");
  1649. return;
  1650. }
  1651. for (i = 0; i < hw_ep_max; i++) {
  1652. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  1653. int type, num, dir, err = -EINVAL;
  1654. struct usb_ctrlrequest req;
  1655. if (mEp->desc == NULL)
  1656. continue; /* not configured */
  1657. if (hw_test_and_clear_complete(i)) {
  1658. err = isr_tr_complete_low(mEp);
  1659. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1660. if (err > 0) /* needs status phase */
  1661. err = isr_setup_status_phase(udc);
  1662. if (err < 0) {
  1663. dbg_event(_usb_addr(mEp),
  1664. "ERROR", err);
  1665. spin_unlock(udc->lock);
  1666. if (usb_ep_set_halt(&mEp->ep))
  1667. err("error: ep_set_halt");
  1668. spin_lock(udc->lock);
  1669. }
  1670. }
  1671. }
  1672. if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
  1673. !hw_test_and_clear_setup_status(i))
  1674. continue;
  1675. if (i != 0) {
  1676. warn("ctrl traffic received at endpoint");
  1677. continue;
  1678. }
  1679. /*
  1680. * Flush data and handshake transactions of previous
  1681. * setup packet.
  1682. */
  1683. _ep_nuke(&udc->ep0out);
  1684. _ep_nuke(&udc->ep0in);
  1685. /* read_setup_packet */
  1686. do {
  1687. hw_test_and_set_setup_guard();
  1688. memcpy(&req, &mEp->qh.ptr->setup, sizeof(req));
  1689. } while (!hw_test_and_clear_setup_guard());
  1690. type = req.bRequestType;
  1691. udc->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
  1692. dbg_setup(_usb_addr(mEp), &req);
  1693. switch (req.bRequest) {
  1694. case USB_REQ_CLEAR_FEATURE:
  1695. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1696. le16_to_cpu(req.wValue) ==
  1697. USB_ENDPOINT_HALT) {
  1698. if (req.wLength != 0)
  1699. break;
  1700. num = le16_to_cpu(req.wIndex);
  1701. dir = num & USB_ENDPOINT_DIR_MASK;
  1702. num &= USB_ENDPOINT_NUMBER_MASK;
  1703. if (dir) /* TX */
  1704. num += hw_ep_max/2;
  1705. if (!udc->ci13xxx_ep[num].wedge) {
  1706. spin_unlock(udc->lock);
  1707. err = usb_ep_clear_halt(
  1708. &udc->ci13xxx_ep[num].ep);
  1709. spin_lock(udc->lock);
  1710. if (err)
  1711. break;
  1712. }
  1713. err = isr_setup_status_phase(udc);
  1714. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
  1715. le16_to_cpu(req.wValue) ==
  1716. USB_DEVICE_REMOTE_WAKEUP) {
  1717. if (req.wLength != 0)
  1718. break;
  1719. udc->remote_wakeup = 0;
  1720. err = isr_setup_status_phase(udc);
  1721. } else {
  1722. goto delegate;
  1723. }
  1724. break;
  1725. case USB_REQ_GET_STATUS:
  1726. if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
  1727. type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
  1728. type != (USB_DIR_IN|USB_RECIP_INTERFACE))
  1729. goto delegate;
  1730. if (le16_to_cpu(req.wLength) != 2 ||
  1731. le16_to_cpu(req.wValue) != 0)
  1732. break;
  1733. err = isr_get_status_response(udc, &req);
  1734. break;
  1735. case USB_REQ_SET_ADDRESS:
  1736. if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
  1737. goto delegate;
  1738. if (le16_to_cpu(req.wLength) != 0 ||
  1739. le16_to_cpu(req.wIndex) != 0)
  1740. break;
  1741. err = hw_usb_set_address((u8)le16_to_cpu(req.wValue));
  1742. if (err)
  1743. break;
  1744. err = isr_setup_status_phase(udc);
  1745. break;
  1746. case USB_REQ_SET_FEATURE:
  1747. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1748. le16_to_cpu(req.wValue) ==
  1749. USB_ENDPOINT_HALT) {
  1750. if (req.wLength != 0)
  1751. break;
  1752. num = le16_to_cpu(req.wIndex);
  1753. dir = num & USB_ENDPOINT_DIR_MASK;
  1754. num &= USB_ENDPOINT_NUMBER_MASK;
  1755. if (dir) /* TX */
  1756. num += hw_ep_max/2;
  1757. spin_unlock(udc->lock);
  1758. err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
  1759. spin_lock(udc->lock);
  1760. if (!err)
  1761. isr_setup_status_phase(udc);
  1762. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
  1763. if (req.wLength != 0)
  1764. break;
  1765. switch (le16_to_cpu(req.wValue)) {
  1766. case USB_DEVICE_REMOTE_WAKEUP:
  1767. udc->remote_wakeup = 1;
  1768. err = isr_setup_status_phase(udc);
  1769. break;
  1770. case USB_DEVICE_TEST_MODE:
  1771. tmode = le16_to_cpu(req.wIndex) >> 8;
  1772. switch (tmode) {
  1773. case TEST_J:
  1774. case TEST_K:
  1775. case TEST_SE0_NAK:
  1776. case TEST_PACKET:
  1777. case TEST_FORCE_EN:
  1778. udc->test_mode = tmode;
  1779. err = isr_setup_status_phase(
  1780. udc);
  1781. break;
  1782. default:
  1783. break;
  1784. }
  1785. default:
  1786. goto delegate;
  1787. }
  1788. } else {
  1789. goto delegate;
  1790. }
  1791. break;
  1792. default:
  1793. delegate:
  1794. if (req.wLength == 0) /* no data phase */
  1795. udc->ep0_dir = TX;
  1796. spin_unlock(udc->lock);
  1797. err = udc->driver->setup(&udc->gadget, &req);
  1798. spin_lock(udc->lock);
  1799. break;
  1800. }
  1801. if (err < 0) {
  1802. dbg_event(_usb_addr(mEp), "ERROR", err);
  1803. spin_unlock(udc->lock);
  1804. if (usb_ep_set_halt(&mEp->ep))
  1805. err("error: ep_set_halt");
  1806. spin_lock(udc->lock);
  1807. }
  1808. }
  1809. }
  1810. /******************************************************************************
  1811. * ENDPT block
  1812. *****************************************************************************/
  1813. /**
  1814. * ep_enable: configure endpoint, making it usable
  1815. *
  1816. * Check usb_ep_enable() at "usb_gadget.h" for details
  1817. */
  1818. static int ep_enable(struct usb_ep *ep,
  1819. const struct usb_endpoint_descriptor *desc)
  1820. {
  1821. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1822. int retval = 0;
  1823. unsigned long flags;
  1824. trace("%p, %p", ep, desc);
  1825. if (ep == NULL || desc == NULL)
  1826. return -EINVAL;
  1827. spin_lock_irqsave(mEp->lock, flags);
  1828. /* only internal SW should enable ctrl endpts */
  1829. mEp->desc = desc;
  1830. if (!list_empty(&mEp->qh.queue))
  1831. warn("enabling a non-empty endpoint!");
  1832. mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
  1833. mEp->num = usb_endpoint_num(desc);
  1834. mEp->type = usb_endpoint_type(desc);
  1835. mEp->ep.maxpacket = usb_endpoint_maxp(desc);
  1836. dbg_event(_usb_addr(mEp), "ENABLE", 0);
  1837. mEp->qh.ptr->cap = 0;
  1838. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1839. mEp->qh.ptr->cap |= QH_IOS;
  1840. else if (mEp->type == USB_ENDPOINT_XFER_ISOC)
  1841. mEp->qh.ptr->cap &= ~QH_MULT;
  1842. else
  1843. mEp->qh.ptr->cap &= ~QH_ZLT;
  1844. mEp->qh.ptr->cap |=
  1845. (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
  1846. mEp->qh.ptr->td.next |= TD_TERMINATE; /* needed? */
  1847. /*
  1848. * Enable endpoints in the HW other than ep0 as ep0
  1849. * is always enabled
  1850. */
  1851. if (mEp->num)
  1852. retval |= hw_ep_enable(mEp->num, mEp->dir, mEp->type);
  1853. spin_unlock_irqrestore(mEp->lock, flags);
  1854. return retval;
  1855. }
  1856. /**
  1857. * ep_disable: endpoint is no longer usable
  1858. *
  1859. * Check usb_ep_disable() at "usb_gadget.h" for details
  1860. */
  1861. static int ep_disable(struct usb_ep *ep)
  1862. {
  1863. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1864. int direction, retval = 0;
  1865. unsigned long flags;
  1866. trace("%p", ep);
  1867. if (ep == NULL)
  1868. return -EINVAL;
  1869. else if (mEp->desc == NULL)
  1870. return -EBUSY;
  1871. spin_lock_irqsave(mEp->lock, flags);
  1872. /* only internal SW should disable ctrl endpts */
  1873. direction = mEp->dir;
  1874. do {
  1875. dbg_event(_usb_addr(mEp), "DISABLE", 0);
  1876. retval |= _ep_nuke(mEp);
  1877. retval |= hw_ep_disable(mEp->num, mEp->dir);
  1878. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1879. mEp->dir = (mEp->dir == TX) ? RX : TX;
  1880. } while (mEp->dir != direction);
  1881. mEp->desc = NULL;
  1882. spin_unlock_irqrestore(mEp->lock, flags);
  1883. return retval;
  1884. }
  1885. /**
  1886. * ep_alloc_request: allocate a request object to use with this endpoint
  1887. *
  1888. * Check usb_ep_alloc_request() at "usb_gadget.h" for details
  1889. */
  1890. static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  1891. {
  1892. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1893. struct ci13xxx_req *mReq = NULL;
  1894. trace("%p, %i", ep, gfp_flags);
  1895. if (ep == NULL) {
  1896. err("EINVAL");
  1897. return NULL;
  1898. }
  1899. mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
  1900. if (mReq != NULL) {
  1901. INIT_LIST_HEAD(&mReq->queue);
  1902. mReq->req.dma = DMA_ADDR_INVALID;
  1903. mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
  1904. &mReq->dma);
  1905. if (mReq->ptr == NULL) {
  1906. kfree(mReq);
  1907. mReq = NULL;
  1908. }
  1909. }
  1910. dbg_event(_usb_addr(mEp), "ALLOC", mReq == NULL);
  1911. return (mReq == NULL) ? NULL : &mReq->req;
  1912. }
  1913. /**
  1914. * ep_free_request: frees a request object
  1915. *
  1916. * Check usb_ep_free_request() at "usb_gadget.h" for details
  1917. */
  1918. static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
  1919. {
  1920. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1921. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1922. unsigned long flags;
  1923. trace("%p, %p", ep, req);
  1924. if (ep == NULL || req == NULL) {
  1925. err("EINVAL");
  1926. return;
  1927. } else if (!list_empty(&mReq->queue)) {
  1928. err("EBUSY");
  1929. return;
  1930. }
  1931. spin_lock_irqsave(mEp->lock, flags);
  1932. if (mReq->ptr)
  1933. dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
  1934. kfree(mReq);
  1935. dbg_event(_usb_addr(mEp), "FREE", 0);
  1936. spin_unlock_irqrestore(mEp->lock, flags);
  1937. }
  1938. /**
  1939. * ep_queue: queues (submits) an I/O request to an endpoint
  1940. *
  1941. * Check usb_ep_queue()* at usb_gadget.h" for details
  1942. */
  1943. static int ep_queue(struct usb_ep *ep, struct usb_request *req,
  1944. gfp_t __maybe_unused gfp_flags)
  1945. {
  1946. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1947. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1948. int retval = 0;
  1949. unsigned long flags;
  1950. trace("%p, %p, %X", ep, req, gfp_flags);
  1951. if (ep == NULL || req == NULL || mEp->desc == NULL)
  1952. return -EINVAL;
  1953. spin_lock_irqsave(mEp->lock, flags);
  1954. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1955. if (req->length)
  1956. mEp = (_udc->ep0_dir == RX) ?
  1957. &_udc->ep0out : &_udc->ep0in;
  1958. if (!list_empty(&mEp->qh.queue)) {
  1959. _ep_nuke(mEp);
  1960. retval = -EOVERFLOW;
  1961. warn("endpoint ctrl %X nuked", _usb_addr(mEp));
  1962. }
  1963. }
  1964. /* first nuke then test link, e.g. previous status has not sent */
  1965. if (!list_empty(&mReq->queue)) {
  1966. retval = -EBUSY;
  1967. err("request already in queue");
  1968. goto done;
  1969. }
  1970. if (req->length > (4 * CI13XXX_PAGE_SIZE)) {
  1971. req->length = (4 * CI13XXX_PAGE_SIZE);
  1972. retval = -EMSGSIZE;
  1973. warn("request length truncated");
  1974. }
  1975. dbg_queue(_usb_addr(mEp), req, retval);
  1976. /* push request */
  1977. mReq->req.status = -EINPROGRESS;
  1978. mReq->req.actual = 0;
  1979. retval = _hardware_enqueue(mEp, mReq);
  1980. if (retval == -EALREADY) {
  1981. dbg_event(_usb_addr(mEp), "QUEUE", retval);
  1982. retval = 0;
  1983. }
  1984. if (!retval)
  1985. list_add_tail(&mReq->queue, &mEp->qh.queue);
  1986. done:
  1987. spin_unlock_irqrestore(mEp->lock, flags);
  1988. return retval;
  1989. }
  1990. /**
  1991. * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
  1992. *
  1993. * Check usb_ep_dequeue() at "usb_gadget.h" for details
  1994. */
  1995. static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
  1996. {
  1997. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1998. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1999. unsigned long flags;
  2000. trace("%p, %p", ep, req);
  2001. if (ep == NULL || req == NULL || mReq->req.status != -EALREADY ||
  2002. mEp->desc == NULL || list_empty(&mReq->queue) ||
  2003. list_empty(&mEp->qh.queue))
  2004. return -EINVAL;
  2005. spin_lock_irqsave(mEp->lock, flags);
  2006. dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
  2007. hw_ep_flush(mEp->num, mEp->dir);
  2008. /* pop request */
  2009. list_del_init(&mReq->queue);
  2010. if (mReq->map) {
  2011. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  2012. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  2013. mReq->req.dma = DMA_ADDR_INVALID;
  2014. mReq->map = 0;
  2015. }
  2016. req->status = -ECONNRESET;
  2017. if (mReq->req.complete != NULL) {
  2018. spin_unlock(mEp->lock);
  2019. mReq->req.complete(&mEp->ep, &mReq->req);
  2020. spin_lock(mEp->lock);
  2021. }
  2022. spin_unlock_irqrestore(mEp->lock, flags);
  2023. return 0;
  2024. }
  2025. /**
  2026. * ep_set_halt: sets the endpoint halt feature
  2027. *
  2028. * Check usb_ep_set_halt() at "usb_gadget.h" for details
  2029. */
  2030. static int ep_set_halt(struct usb_ep *ep, int value)
  2031. {
  2032. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2033. int direction, retval = 0;
  2034. unsigned long flags;
  2035. trace("%p, %i", ep, value);
  2036. if (ep == NULL || mEp->desc == NULL)
  2037. return -EINVAL;
  2038. spin_lock_irqsave(mEp->lock, flags);
  2039. #ifndef STALL_IN
  2040. /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
  2041. if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
  2042. !list_empty(&mEp->qh.queue)) {
  2043. spin_unlock_irqrestore(mEp->lock, flags);
  2044. return -EAGAIN;
  2045. }
  2046. #endif
  2047. direction = mEp->dir;
  2048. do {
  2049. dbg_event(_usb_addr(mEp), "HALT", value);
  2050. retval |= hw_ep_set_halt(mEp->num, mEp->dir, value);
  2051. if (!value)
  2052. mEp->wedge = 0;
  2053. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  2054. mEp->dir = (mEp->dir == TX) ? RX : TX;
  2055. } while (mEp->dir != direction);
  2056. spin_unlock_irqrestore(mEp->lock, flags);
  2057. return retval;
  2058. }
  2059. /**
  2060. * ep_set_wedge: sets the halt feature and ignores clear requests
  2061. *
  2062. * Check usb_ep_set_wedge() at "usb_gadget.h" for details
  2063. */
  2064. static int ep_set_wedge(struct usb_ep *ep)
  2065. {
  2066. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2067. unsigned long flags;
  2068. trace("%p", ep);
  2069. if (ep == NULL || mEp->desc == NULL)
  2070. return -EINVAL;
  2071. spin_lock_irqsave(mEp->lock, flags);
  2072. dbg_event(_usb_addr(mEp), "WEDGE", 0);
  2073. mEp->wedge = 1;
  2074. spin_unlock_irqrestore(mEp->lock, flags);
  2075. return usb_ep_set_halt(ep);
  2076. }
  2077. /**
  2078. * ep_fifo_flush: flushes contents of a fifo
  2079. *
  2080. * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
  2081. */
  2082. static void ep_fifo_flush(struct usb_ep *ep)
  2083. {
  2084. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2085. unsigned long flags;
  2086. trace("%p", ep);
  2087. if (ep == NULL) {
  2088. err("%02X: -EINVAL", _usb_addr(mEp));
  2089. return;
  2090. }
  2091. spin_lock_irqsave(mEp->lock, flags);
  2092. dbg_event(_usb_addr(mEp), "FFLUSH", 0);
  2093. hw_ep_flush(mEp->num, mEp->dir);
  2094. spin_unlock_irqrestore(mEp->lock, flags);
  2095. }
  2096. /**
  2097. * Endpoint-specific part of the API to the USB controller hardware
  2098. * Check "usb_gadget.h" for details
  2099. */
  2100. static const struct usb_ep_ops usb_ep_ops = {
  2101. .enable = ep_enable,
  2102. .disable = ep_disable,
  2103. .alloc_request = ep_alloc_request,
  2104. .free_request = ep_free_request,
  2105. .queue = ep_queue,
  2106. .dequeue = ep_dequeue,
  2107. .set_halt = ep_set_halt,
  2108. .set_wedge = ep_set_wedge,
  2109. .fifo_flush = ep_fifo_flush,
  2110. };
  2111. /******************************************************************************
  2112. * GADGET block
  2113. *****************************************************************************/
  2114. static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
  2115. {
  2116. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2117. unsigned long flags;
  2118. int gadget_ready = 0;
  2119. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS))
  2120. return -EOPNOTSUPP;
  2121. spin_lock_irqsave(udc->lock, flags);
  2122. udc->vbus_active = is_active;
  2123. if (udc->driver)
  2124. gadget_ready = 1;
  2125. spin_unlock_irqrestore(udc->lock, flags);
  2126. if (gadget_ready) {
  2127. if (is_active) {
  2128. pm_runtime_get_sync(&_gadget->dev);
  2129. hw_device_reset(udc);
  2130. hw_device_state(udc->ep0out.qh.dma);
  2131. } else {
  2132. hw_device_state(0);
  2133. if (udc->udc_driver->notify_event)
  2134. udc->udc_driver->notify_event(udc,
  2135. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2136. _gadget_stop_activity(&udc->gadget);
  2137. pm_runtime_put_sync(&_gadget->dev);
  2138. }
  2139. }
  2140. return 0;
  2141. }
  2142. static int ci13xxx_wakeup(struct usb_gadget *_gadget)
  2143. {
  2144. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2145. unsigned long flags;
  2146. int ret = 0;
  2147. trace();
  2148. spin_lock_irqsave(udc->lock, flags);
  2149. if (!udc->remote_wakeup) {
  2150. ret = -EOPNOTSUPP;
  2151. trace("remote wakeup feature is not enabled\n");
  2152. goto out;
  2153. }
  2154. if (!hw_cread(CAP_PORTSC, PORTSC_SUSP)) {
  2155. ret = -EINVAL;
  2156. trace("port is not suspended\n");
  2157. goto out;
  2158. }
  2159. hw_cwrite(CAP_PORTSC, PORTSC_FPR, PORTSC_FPR);
  2160. out:
  2161. spin_unlock_irqrestore(udc->lock, flags);
  2162. return ret;
  2163. }
  2164. static int ci13xxx_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
  2165. {
  2166. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2167. if (udc->transceiver)
  2168. return otg_set_power(udc->transceiver, mA);
  2169. return -ENOTSUPP;
  2170. }
  2171. static int ci13xxx_start(struct usb_gadget_driver *driver,
  2172. int (*bind)(struct usb_gadget *));
  2173. static int ci13xxx_stop(struct usb_gadget_driver *driver);
  2174. /**
  2175. * Device operations part of the API to the USB controller hardware,
  2176. * which don't involve endpoints (or i/o)
  2177. * Check "usb_gadget.h" for details
  2178. */
  2179. static const struct usb_gadget_ops usb_gadget_ops = {
  2180. .vbus_session = ci13xxx_vbus_session,
  2181. .wakeup = ci13xxx_wakeup,
  2182. .vbus_draw = ci13xxx_vbus_draw,
  2183. .start = ci13xxx_start,
  2184. .stop = ci13xxx_stop,
  2185. };
  2186. /**
  2187. * ci13xxx_start: register a gadget driver
  2188. * @driver: the driver being registered
  2189. * @bind: the driver's bind callback
  2190. *
  2191. * Check ci13xxx_start() at <linux/usb/gadget.h> for details.
  2192. * Interrupts are enabled here.
  2193. */
  2194. static int ci13xxx_start(struct usb_gadget_driver *driver,
  2195. int (*bind)(struct usb_gadget *))
  2196. {
  2197. struct ci13xxx *udc = _udc;
  2198. unsigned long flags;
  2199. int i, j;
  2200. int retval = -ENOMEM;
  2201. trace("%p", driver);
  2202. if (driver == NULL ||
  2203. bind == NULL ||
  2204. driver->setup == NULL ||
  2205. driver->disconnect == NULL)
  2206. return -EINVAL;
  2207. else if (udc == NULL)
  2208. return -ENODEV;
  2209. else if (udc->driver != NULL)
  2210. return -EBUSY;
  2211. /* alloc resources */
  2212. udc->qh_pool = dma_pool_create("ci13xxx_qh", &udc->gadget.dev,
  2213. sizeof(struct ci13xxx_qh),
  2214. 64, CI13XXX_PAGE_SIZE);
  2215. if (udc->qh_pool == NULL)
  2216. return -ENOMEM;
  2217. udc->td_pool = dma_pool_create("ci13xxx_td", &udc->gadget.dev,
  2218. sizeof(struct ci13xxx_td),
  2219. 64, CI13XXX_PAGE_SIZE);
  2220. if (udc->td_pool == NULL) {
  2221. dma_pool_destroy(udc->qh_pool);
  2222. udc->qh_pool = NULL;
  2223. return -ENOMEM;
  2224. }
  2225. spin_lock_irqsave(udc->lock, flags);
  2226. info("hw_ep_max = %d", hw_ep_max);
  2227. udc->gadget.dev.driver = NULL;
  2228. retval = 0;
  2229. for (i = 0; i < hw_ep_max/2; i++) {
  2230. for (j = RX; j <= TX; j++) {
  2231. int k = i + j * hw_ep_max/2;
  2232. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[k];
  2233. scnprintf(mEp->name, sizeof(mEp->name), "ep%i%s", i,
  2234. (j == TX) ? "in" : "out");
  2235. mEp->lock = udc->lock;
  2236. mEp->device = &udc->gadget.dev;
  2237. mEp->td_pool = udc->td_pool;
  2238. mEp->ep.name = mEp->name;
  2239. mEp->ep.ops = &usb_ep_ops;
  2240. mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
  2241. INIT_LIST_HEAD(&mEp->qh.queue);
  2242. spin_unlock_irqrestore(udc->lock, flags);
  2243. mEp->qh.ptr = dma_pool_alloc(udc->qh_pool, GFP_KERNEL,
  2244. &mEp->qh.dma);
  2245. spin_lock_irqsave(udc->lock, flags);
  2246. if (mEp->qh.ptr == NULL)
  2247. retval = -ENOMEM;
  2248. else
  2249. memset(mEp->qh.ptr, 0, sizeof(*mEp->qh.ptr));
  2250. /* skip ep0 out and in endpoints */
  2251. if (i == 0)
  2252. continue;
  2253. list_add_tail(&mEp->ep.ep_list, &udc->gadget.ep_list);
  2254. }
  2255. }
  2256. if (retval)
  2257. goto done;
  2258. spin_unlock_irqrestore(udc->lock, flags);
  2259. udc->ep0out.ep.desc = &ctrl_endpt_out_desc;
  2260. retval = usb_ep_enable(&udc->ep0out.ep);
  2261. if (retval)
  2262. return retval;
  2263. udc->ep0in.ep.desc = &ctrl_endpt_in_desc;
  2264. retval = usb_ep_enable(&udc->ep0in.ep);
  2265. if (retval)
  2266. return retval;
  2267. spin_lock_irqsave(udc->lock, flags);
  2268. udc->gadget.ep0 = &udc->ep0in.ep;
  2269. /* bind gadget */
  2270. driver->driver.bus = NULL;
  2271. udc->gadget.dev.driver = &driver->driver;
  2272. spin_unlock_irqrestore(udc->lock, flags);
  2273. retval = bind(&udc->gadget); /* MAY SLEEP */
  2274. spin_lock_irqsave(udc->lock, flags);
  2275. if (retval) {
  2276. udc->gadget.dev.driver = NULL;
  2277. goto done;
  2278. }
  2279. udc->driver = driver;
  2280. pm_runtime_get_sync(&udc->gadget.dev);
  2281. if (udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) {
  2282. if (udc->vbus_active) {
  2283. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED)
  2284. hw_device_reset(udc);
  2285. } else {
  2286. pm_runtime_put_sync(&udc->gadget.dev);
  2287. goto done;
  2288. }
  2289. }
  2290. retval = hw_device_state(udc->ep0out.qh.dma);
  2291. if (retval)
  2292. pm_runtime_put_sync(&udc->gadget.dev);
  2293. done:
  2294. spin_unlock_irqrestore(udc->lock, flags);
  2295. return retval;
  2296. }
  2297. /**
  2298. * ci13xxx_stop: unregister a gadget driver
  2299. *
  2300. * Check usb_gadget_unregister_driver() at "usb_gadget.h" for details
  2301. */
  2302. static int ci13xxx_stop(struct usb_gadget_driver *driver)
  2303. {
  2304. struct ci13xxx *udc = _udc;
  2305. unsigned long i, flags;
  2306. trace("%p", driver);
  2307. if (driver == NULL ||
  2308. driver->unbind == NULL ||
  2309. driver->setup == NULL ||
  2310. driver->disconnect == NULL ||
  2311. driver != udc->driver)
  2312. return -EINVAL;
  2313. spin_lock_irqsave(udc->lock, flags);
  2314. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) ||
  2315. udc->vbus_active) {
  2316. hw_device_state(0);
  2317. if (udc->udc_driver->notify_event)
  2318. udc->udc_driver->notify_event(udc,
  2319. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2320. spin_unlock_irqrestore(udc->lock, flags);
  2321. _gadget_stop_activity(&udc->gadget);
  2322. spin_lock_irqsave(udc->lock, flags);
  2323. pm_runtime_put(&udc->gadget.dev);
  2324. }
  2325. /* unbind gadget */
  2326. spin_unlock_irqrestore(udc->lock, flags);
  2327. driver->unbind(&udc->gadget); /* MAY SLEEP */
  2328. spin_lock_irqsave(udc->lock, flags);
  2329. udc->gadget.dev.driver = NULL;
  2330. /* free resources */
  2331. for (i = 0; i < hw_ep_max; i++) {
  2332. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  2333. if (!list_empty(&mEp->ep.ep_list))
  2334. list_del_init(&mEp->ep.ep_list);
  2335. if (mEp->qh.ptr != NULL)
  2336. dma_pool_free(udc->qh_pool, mEp->qh.ptr, mEp->qh.dma);
  2337. }
  2338. udc->gadget.ep0 = NULL;
  2339. udc->driver = NULL;
  2340. spin_unlock_irqrestore(udc->lock, flags);
  2341. if (udc->td_pool != NULL) {
  2342. dma_pool_destroy(udc->td_pool);
  2343. udc->td_pool = NULL;
  2344. }
  2345. if (udc->qh_pool != NULL) {
  2346. dma_pool_destroy(udc->qh_pool);
  2347. udc->qh_pool = NULL;
  2348. }
  2349. return 0;
  2350. }
  2351. /******************************************************************************
  2352. * BUS block
  2353. *****************************************************************************/
  2354. /**
  2355. * udc_irq: global interrupt handler
  2356. *
  2357. * This function returns IRQ_HANDLED if the IRQ has been handled
  2358. * It locks access to registers
  2359. */
  2360. static irqreturn_t udc_irq(void)
  2361. {
  2362. struct ci13xxx *udc = _udc;
  2363. irqreturn_t retval;
  2364. u32 intr;
  2365. trace();
  2366. if (udc == NULL) {
  2367. err("ENODEV");
  2368. return IRQ_HANDLED;
  2369. }
  2370. spin_lock(udc->lock);
  2371. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED) {
  2372. if (hw_cread(CAP_USBMODE, USBMODE_CM) !=
  2373. USBMODE_CM_DEVICE) {
  2374. spin_unlock(udc->lock);
  2375. return IRQ_NONE;
  2376. }
  2377. }
  2378. intr = hw_test_and_clear_intr_active();
  2379. if (intr) {
  2380. isr_statistics.hndl.buf[isr_statistics.hndl.idx++] = intr;
  2381. isr_statistics.hndl.idx &= ISR_MASK;
  2382. isr_statistics.hndl.cnt++;
  2383. /* order defines priority - do NOT change it */
  2384. if (USBi_URI & intr) {
  2385. isr_statistics.uri++;
  2386. isr_reset_handler(udc);
  2387. }
  2388. if (USBi_PCI & intr) {
  2389. isr_statistics.pci++;
  2390. udc->gadget.speed = hw_port_is_high_speed() ?
  2391. USB_SPEED_HIGH : USB_SPEED_FULL;
  2392. if (udc->suspended && udc->driver->resume) {
  2393. spin_unlock(udc->lock);
  2394. udc->driver->resume(&udc->gadget);
  2395. spin_lock(udc->lock);
  2396. udc->suspended = 0;
  2397. }
  2398. }
  2399. if (USBi_UEI & intr)
  2400. isr_statistics.uei++;
  2401. if (USBi_UI & intr) {
  2402. isr_statistics.ui++;
  2403. isr_tr_complete_handler(udc);
  2404. }
  2405. if (USBi_SLI & intr) {
  2406. if (udc->gadget.speed != USB_SPEED_UNKNOWN &&
  2407. udc->driver->suspend) {
  2408. udc->suspended = 1;
  2409. spin_unlock(udc->lock);
  2410. udc->driver->suspend(&udc->gadget);
  2411. spin_lock(udc->lock);
  2412. }
  2413. isr_statistics.sli++;
  2414. }
  2415. retval = IRQ_HANDLED;
  2416. } else {
  2417. isr_statistics.none++;
  2418. retval = IRQ_NONE;
  2419. }
  2420. spin_unlock(udc->lock);
  2421. return retval;
  2422. }
  2423. /**
  2424. * udc_release: driver release function
  2425. * @dev: device
  2426. *
  2427. * Currently does nothing
  2428. */
  2429. static void udc_release(struct device *dev)
  2430. {
  2431. trace("%p", dev);
  2432. if (dev == NULL)
  2433. err("EINVAL");
  2434. }
  2435. /**
  2436. * udc_probe: parent probe must call this to initialize UDC
  2437. * @dev: parent device
  2438. * @regs: registers base address
  2439. * @name: driver name
  2440. *
  2441. * This function returns an error code
  2442. * No interrupts active, the IRQ has not been requested yet
  2443. * Kernel assumes 32-bit DMA operations by default, no need to dma_set_mask
  2444. */
  2445. static int udc_probe(struct ci13xxx_udc_driver *driver, struct device *dev,
  2446. void __iomem *regs)
  2447. {
  2448. struct ci13xxx *udc;
  2449. int retval = 0;
  2450. trace("%p, %p, %p", dev, regs, driver->name);
  2451. if (dev == NULL || regs == NULL || driver == NULL ||
  2452. driver->name == NULL)
  2453. return -EINVAL;
  2454. udc = kzalloc(sizeof(struct ci13xxx), GFP_KERNEL);
  2455. if (udc == NULL)
  2456. return -ENOMEM;
  2457. udc->lock = &udc_lock;
  2458. udc->regs = regs;
  2459. udc->udc_driver = driver;
  2460. udc->gadget.ops = &usb_gadget_ops;
  2461. udc->gadget.speed = USB_SPEED_UNKNOWN;
  2462. udc->gadget.max_speed = USB_SPEED_HIGH;
  2463. udc->gadget.is_otg = 0;
  2464. udc->gadget.name = driver->name;
  2465. INIT_LIST_HEAD(&udc->gadget.ep_list);
  2466. udc->gadget.ep0 = NULL;
  2467. dev_set_name(&udc->gadget.dev, "gadget");
  2468. udc->gadget.dev.dma_mask = dev->dma_mask;
  2469. udc->gadget.dev.coherent_dma_mask = dev->coherent_dma_mask;
  2470. udc->gadget.dev.parent = dev;
  2471. udc->gadget.dev.release = udc_release;
  2472. retval = hw_device_init(regs);
  2473. if (retval < 0)
  2474. goto free_udc;
  2475. udc->transceiver = otg_get_transceiver();
  2476. if (udc->udc_driver->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
  2477. if (udc->transceiver == NULL) {
  2478. retval = -ENODEV;
  2479. goto free_udc;
  2480. }
  2481. }
  2482. if (!(udc->udc_driver->flags & CI13XXX_REGS_SHARED)) {
  2483. retval = hw_device_reset(udc);
  2484. if (retval)
  2485. goto put_transceiver;
  2486. }
  2487. retval = device_register(&udc->gadget.dev);
  2488. if (retval) {
  2489. put_device(&udc->gadget.dev);
  2490. goto put_transceiver;
  2491. }
  2492. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2493. retval = dbg_create_files(&udc->gadget.dev);
  2494. #endif
  2495. if (retval)
  2496. goto unreg_device;
  2497. if (udc->transceiver) {
  2498. retval = otg_set_peripheral(udc->transceiver, &udc->gadget);
  2499. if (retval)
  2500. goto remove_dbg;
  2501. }
  2502. retval = usb_add_gadget_udc(dev, &udc->gadget);
  2503. if (retval)
  2504. goto remove_trans;
  2505. pm_runtime_no_callbacks(&udc->gadget.dev);
  2506. pm_runtime_enable(&udc->gadget.dev);
  2507. _udc = udc;
  2508. return retval;
  2509. remove_trans:
  2510. if (udc->transceiver) {
  2511. otg_set_peripheral(udc->transceiver, &udc->gadget);
  2512. otg_put_transceiver(udc->transceiver);
  2513. }
  2514. err("error = %i", retval);
  2515. remove_dbg:
  2516. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2517. dbg_remove_files(&udc->gadget.dev);
  2518. #endif
  2519. unreg_device:
  2520. device_unregister(&udc->gadget.dev);
  2521. put_transceiver:
  2522. if (udc->transceiver)
  2523. otg_put_transceiver(udc->transceiver);
  2524. free_udc:
  2525. kfree(udc);
  2526. _udc = NULL;
  2527. return retval;
  2528. }
  2529. /**
  2530. * udc_remove: parent remove must call this to remove UDC
  2531. *
  2532. * No interrupts active, the IRQ has been released
  2533. */
  2534. static void udc_remove(void)
  2535. {
  2536. struct ci13xxx *udc = _udc;
  2537. if (udc == NULL) {
  2538. err("EINVAL");
  2539. return;
  2540. }
  2541. usb_del_gadget_udc(&udc->gadget);
  2542. if (udc->transceiver) {
  2543. otg_set_peripheral(udc->transceiver, &udc->gadget);
  2544. otg_put_transceiver(udc->transceiver);
  2545. }
  2546. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2547. dbg_remove_files(&udc->gadget.dev);
  2548. #endif
  2549. device_unregister(&udc->gadget.dev);
  2550. kfree(udc);
  2551. _udc = NULL;
  2552. }